JPS61147551A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61147551A
JPS61147551A JP59269910A JP26991084A JPS61147551A JP S61147551 A JPS61147551 A JP S61147551A JP 59269910 A JP59269910 A JP 59269910A JP 26991084 A JP26991084 A JP 26991084A JP S61147551 A JPS61147551 A JP S61147551A
Authority
JP
Japan
Prior art keywords
wiring
holes
upper layer
layer wiring
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59269910A
Other languages
Japanese (ja)
Other versions
JPH0374032B2 (en
Inventor
Isao Kano
鹿野　功
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59269910A priority Critical patent/JPS61147551A/en
Publication of JPS61147551A publication Critical patent/JPS61147551A/en
Publication of JPH0374032B2 publication Critical patent/JPH0374032B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the imitation and copying of a wiring pattern by a method wherein false through holes, with which no electric connection is performed, is provided in a multilayer wiring structure. CONSTITUTION:A plurality of false through holes 6a and 6b, of almost same apparent size as through holes 5a-5e, with which the lower layer wirings 3a-3e and the upper layer wirings 7a-7c are not electrically connected, are formed. As result, the wirings 3a, 3b, 3c, 3d and 3e are looked like as if they are connected to the wirings 7a via the through holes 5a, 5b, 5c, 6a and 6b by a third person who has no circuit diagram. As a result, the wiring pattern can be prevented from imitation and copying.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、特に配線パター７の模倣
、コピーを防止するための配線層間絶縁膜に１１．する
スルーホールに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a wiring interlayer insulating film for preventing imitation or copying of a wiring pattern 7. This relates to through-holes.

〔従来の技術〕[Conventional technology]

従来、多層配線構造を有する半導体装置は、例えば第２
図（ａ）、　（ｂ）の構造を有している。すなわち、第
２図（ａ）、　（ｂ）に示すように、＃−導体基板２１
の上に設けられた絶縁膜２２上に下層配線２３ａ〜２３
６が形成されその上に層間絶縁膜２４が形成され、前記
層間絶縁膜２４には、下層配線と上層配＃！を電気的に
接続するスルーホール２５ａ〜２５ｅ　−ＩＪ１形成さ
れ、その上に上層配線２７ａ〜２７ｃが形成される。第
２図（ｂ）は従来例の平面図であり、第２図（ａ）は、
第２図（ｂ）のＡ−人′間の断面図である。Conventionally, a semiconductor device having a multilayer wiring structure has, for example, a second
It has the structure shown in Figures (a) and (b). That is, as shown in FIGS. 2(a) and 2(b), the #-conductor substrate 21
Lower layer wirings 23a to 23 are formed on the insulating film 22 provided above.
6 is formed, and an interlayer insulating film 24 is formed thereon, and the interlayer insulating film 24 includes a lower layer wiring and an upper layer wiring #! Through holes 25a to 25e -IJ1 are formed to electrically connect them, and upper layer wirings 27a to 27c are formed thereon. FIG. 2(b) is a plan view of the conventional example, and FIG. 2(a) is a
It is a sectional view between A-person' in FIG. 2(b).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の多層配線構造では、平面図の第２図（ｂ）　ｉ見
れば回路図を持っていない第３者でも、２３Ｃの配線と
２３　ｂ１２）配線、２３ａの配線が、それぞれスルー
ホール２５ａ、２５ｂ、２５Ｃ１−介して上層配線２７
ａに電気的に接続していることがわかる。即ち第３者で
も半導体基板の平面写真あるいは平面図が手に入ること
により、あるいは顕微鏡により上から観察することによ
り従来技術では多層配線において、層間絶縁膜ＶＣ士層
配線と上層配線間のスルーホールが電気的に接続さ几て
いることが確実であるため、他業者は順次上層パターン
から下層パターンまた下層パター７から上層パター／へ
スルーホールを通して配線を追ってゆけば、その製品の
回路パターンを解読することが比較的容易にできる。In the conventional multilayer wiring structure, if you look at the plan view of FIG. , 25C1- via upper layer wiring 27
It can be seen that it is electrically connected to a. In other words, if a third party can obtain a planar photograph or plan view of the semiconductor substrate, or observe it from above using a microscope, the conventional technology can detect through-holes between the interlayer insulating film VC layer wiring and the upper layer wiring in multilayer wiring. Since it is certain that the is electrically connected, other manufacturers can decipher the circuit pattern of the product by sequentially tracing the wiring from the upper layer pattern to the lower layer pattern and from the lower layer pattern 7 to the upper layer pattern through the through hole. This can be done relatively easily.

一万、半導体装置の高集積化が進むにつれ開発工数、開
発費は著しく増大しつつある。ところが競合他業者は、
開発された半導体装置の配線パターン、及び回路を上記
したように解読し、複製することによりわずかの費用−
工数で同等の製品を開発できるという問題が生じてきた
。However, as semiconductor devices become more highly integrated, the number of development steps and costs are increasing significantly. However, competitors
By deciphering and duplicating the wiring patterns and circuits of developed semiconductor devices as described above, costs can be reduced at a fraction of the cost.
The problem has arisen that it is possible to develop an equivalent product with fewer man-hours.

本発明に上記問題点に対処してなされたもので、多層配
線構造の配線パター７の解読、模倣、コピーを防止する
ことができる半導体装ｆｆ１ｌｔ−提供することを目的
とする。The present invention has been made to address the above-mentioned problems, and an object of the present invention is to provide a semiconductor device ff1lt- that can prevent wiring pattern 7 of a multilayer wiring structure from being decoded, imitated, or copied.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置は、多層配線構造を有する半導体装
置において、下層配線と上層配線全接続するスルーホー
ルを有し、かつ前記スルーホールと見かけの寸法はほぼ
同等で下層配線と上層配線とを電気的に接続しない複数
の擬似スルーホールを有することにより構成される。The semiconductor device of the present invention is a semiconductor device having a multilayer wiring structure, which has a through hole that connects all of the lower layer wiring and the upper layer wiring, and which has approximately the same apparent size as the through hole and which electrically connects the lower layer wiring and the upper layer wiring. It is constructed by having a plurality of pseudo through holes that are not directly connected.

〔実施例Ｊ 次に、本発明の実施例について５図面全参照して説明す
る。第１図（ａ）、　（ｂ）は本発明の一実施例の平面
図およびＡ−Ａ’間の断面図である。[Example J Next, an example of the present invention will be described with reference to all five drawings. FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along line AA' of an embodiment of the present invention.

第１図（ａｌ、　（ｂ）において、半導体基板１の上に
設けられた絶縁膜２の上に下層配線３ａ〜３６が形成さ
れ、その上に層間絶縁膜４が形成され１層間絶縁膜４に
は下層配線と上層配線全電気的に接続するスルーホール
５８〜５ｅが形成さｎると共に、スルーホール５３〜５
ｅと見かけの寸法はほぼ同等で、下層配線と上層配線を
電気的に接続しない複数の擬似スルーホール６ａ、６ｂ
が形成され、さらにその上に上層配線７ａ〜７ｃが形成
されている。In FIGS. 1A and 1B, lower layer wirings 3a to 36 are formed on an insulating film 2 provided on a semiconductor substrate 1, and an interlayer insulating film 4 is formed thereon. Through holes 58 to 5e are formed to electrically connect the lower layer wiring and the upper layer wiring, and the through holes 53 to 5
A plurality of pseudo through holes 6a, 6b that have approximately the same apparent dimensions as e and do not electrically connect the lower layer wiring and the upper layer wiring.
are formed, and upper layer wirings 7a to 7c are further formed thereon.

今、第１図（ａ）の平面図金兄るとき、回路図を持って
いない第３者ｌＣは３ｅ、　　３ｄ、　　３ｃ、　　３
ｂ。Now, when looking at the plan view of Figure 1(a), a third party IC who does not have the circuit diagram will write 3e, 3d, 3c, 3.
b.

３１１（Ｄ配線がそれぞし５　ａ、　　６　ａ、　　６
　ｂ、　　５　ｂ。311 (D wiring is respectively 5 a, 6 a, 6
b, 5 b.

５Ｃの孔を通じて７ａの上層配線に接続しているように
見える。しかしながら実際には３ｅ、３ｂ。It appears to be connected to the upper layer wiring 7a through the hole 5C. However, it is actually 3e and 3b.

３！ＩＯ配線が、そｎぞれ５ａ、５ｂ、５ｃのスルーホ
ールを介して７ａの上層配線に接続しているだけで他の
３ｄ、３ｃの配線は７ａとは、電気的に接続されていな
いのである。3! The IO wiring is only connected to the upper layer wiring of 7a through the through holes of 5a, 5b, and 5c, and the other wirings of 3d and 3c are not electrically connected to 7a. be.

従って、第３者が本半導体装置の回路図を解読すること
は、技術的に困難であり、解読し得るとしても従来例の
半導体装置の回路図を知り得るに要する時間とコストの
何倍もの時間とコストヲ要すること＼考えられ、特に集
積回路の大規模化にともないその効果は大きくなる。す
なわち、半導体装置の配線パターン及び回路模倣の防止
に役立つものである。Therefore, it is technically difficult for a third party to decipher the circuit diagram of the present semiconductor device, and even if it were possible, it would take many times the time and cost to know the circuit diagram of the conventional semiconductor device. It is thought that it takes time and cost, and its effects become particularly large as the scale of integrated circuits increases. That is, it is useful for preventing imitation of wiring patterns and circuits of semiconductor devices.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は多層配線構造において電
気的接続を行なわない擬似スルーホールを設けることに
より、配線パターンの模倣、コピー１−防止することが
でき集積回路装置の開発者の保ｉｔ−することができる
。As explained above, the present invention prevents imitation and copying of wiring patterns by providing pseudo through-holes that do not make electrical connections in a multilayer wiring structure. can do.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）、　（ｂ）ｆ１本発明の一実施例の平面図
およびＡ−Ａ’線に於ける断面図、第２図（ａ）、　（
ｂ）は従来構造の多層配線を有する半導体装置の一例の
平面図及びそのＡ−Ａ’線に於ける断面図である。 １．２１・・・・・・半導体基板、２．２２・・・・・
・絶縁膜、３ａ、３ｂ、３ｃ、３ｄ、３ｅ、２３ａ、２
３ｂ。 ２３　ｃ、　　２３　ｄ、　　２３　ａ・・・・・・下
層配線ｂ４＊２４・・・・・・層間絶縁膜、５ａ、　　
５ｂ、　　５ｃ、　　５ｄ、　　５ｅ。 ２５ａ、２５ｂ、２５ｃ、２５ｄ、２５ｅ・−・−スル
ーホール、５ａ、５ｂ・・・・・・擬似スルーホール、
７ａ、７ｂ、７ｃ、２７ａ、２７ｂ、２７ｃｍ−・・・
・上層配線。Fig. 1(a), (b) f1 A plan view of an embodiment of the present invention and a sectional view taken along the line A-A', Fig. 2(a), (
b) is a plan view of an example of a semiconductor device having a conventional multilayer interconnection structure, and a cross-sectional view thereof taken along the line AA'. 1.21... Semiconductor substrate, 2.22...
・Insulating film, 3a, 3b, 3c, 3d, 3e, 23a, 2
3b. 23 c, 23 d, 23 a...Lower wiring b4*24...Interlayer insulating film, 5a,
5b, 5c, 5d, 5e. 25a, 25b, 25c, 25d, 25e...-Through hole, 5a, 5b...Pseudo through hole,
7a, 7b, 7c, 27a, 27b, 27cm-...
・Upper layer wiring.

Claims (1)

【特許請求の範囲】[Claims] 多層配線構造を有する半導体装置において、下層配線と
上層配線間の層間絶縁膜に下層配線と上層配線を電気的
に接続するスルーホールを有し、かつ前記スルーホール
と見かけの寸法はほぼ同等で下層配線と上層配線とを電
気的に接続しない複数の擬似スルーホールを有すること
を特徴とする半導体装置。In a semiconductor device having a multilayer wiring structure, a through hole for electrically connecting the lower layer wiring and the upper layer wiring is provided in an interlayer insulating film between the lower layer wiring and the upper layer wiring, and the apparent dimensions of the through hole are approximately the same as that of the lower layer wiring. A semiconductor device characterized by having a plurality of pseudo through holes that do not electrically connect wiring and upper layer wiring.
JP59269910A 1984-12-21 1984-12-21 Semiconductor device Granted JPS61147551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59269910A JPS61147551A (en) 1984-12-21 1984-12-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59269910A JPS61147551A (en) 1984-12-21 1984-12-21 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS61147551A true JPS61147551A (en) 1986-07-05
JPH0374032B2 JPH0374032B2 (en) 1991-11-25

Family

ID=17478921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59269910A Granted JPS61147551A (en) 1984-12-21 1984-12-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61147551A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5821582A (en) * 1993-07-22 1998-10-13 National Semiconductor Corp. Structures for preventing reverse engineering of integrated circuits
WO1998057373A1 (en) * 1997-06-13 1998-12-17 Inside Technologies Method for making an integrated circuit and integrated circuit produced by said method
EP1193758A1 (en) * 2000-10-02 2002-04-03 STMicroelectronics S.r.l. Anti-deciphering contacts
EP1202353A1 (en) * 2000-10-27 2002-05-02 STMicroelectronics S.r.l. Mask programmed ROM and method of fabrication
WO2002059967A3 (en) * 2001-01-24 2003-02-20 Hrl Lab Llc Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
WO2002103785A3 (en) * 2001-06-15 2003-08-14 Hrl Lab Llc Cmos process
WO2003098692A1 (en) * 2002-05-14 2003-11-27 Hrl Laboratories, Llc Integrated circuit with reverse engineering protection
US6740942B2 (en) 2001-06-15 2004-05-25 Hrl Laboratories, Llc. Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
FR3059145A1 (en) * 2016-11-22 2018-05-25 Stmicroelectronics (Rousset) Sas METHOD OF FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT
FR3059144A1 (en) * 2016-11-22 2018-05-25 Stmicroelectronics (Rousset) Sas METHOD OF FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTERCONNECTION PART OF AN INTEGRATED CIRCUIT WITHOUT ADDING ADDITIONAL MATERIAL, AND CORRESPONDING INTEGRATED CIRCUIT
US10049991B2 (en) 2016-11-22 2018-08-14 Stmicroelectronics (Rousset) Sas Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit, and corresponding integrated circuit

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5821582A (en) * 1993-07-22 1998-10-13 National Semiconductor Corp. Structures for preventing reverse engineering of integrated circuits
WO1998057373A1 (en) * 1997-06-13 1998-12-17 Inside Technologies Method for making an integrated circuit and integrated circuit produced by said method
EP1193758A1 (en) * 2000-10-02 2002-04-03 STMicroelectronics S.r.l. Anti-deciphering contacts
EP1202353A1 (en) * 2000-10-27 2002-05-02 STMicroelectronics S.r.l. Mask programmed ROM and method of fabrication
US6791191B2 (en) * 2001-01-24 2004-09-14 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
WO2002059967A3 (en) * 2001-01-24 2003-02-20 Hrl Lab Llc Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
WO2002103785A3 (en) * 2001-06-15 2003-08-14 Hrl Lab Llc Cmos process
US6740942B2 (en) 2001-06-15 2004-05-25 Hrl Laboratories, Llc. Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
JP2005526401A (en) * 2002-05-14 2005-09-02 エイチアールエル　ラボラトリーズ，エルエルシー Integrated circuits with protection against reverse engineering
GB2405531A (en) * 2002-05-14 2005-03-02 Hrl Lab Llc Integrated circuit with reverse engineering protection
WO2003098692A1 (en) * 2002-05-14 2003-11-27 Hrl Laboratories, Llc Integrated circuit with reverse engineering protection
GB2405531B (en) * 2002-05-14 2006-04-12 Hrl Lab Llc Integrated circuit with reverse engineering protection
JP4729303B2 (en) * 2002-05-14 2011-07-20 エイチアールエル ラボラトリーズ，エルエルシー Integrated circuits with protection against reverse engineering
FR3059145A1 (en) * 2016-11-22 2018-05-25 Stmicroelectronics (Rousset) Sas METHOD OF FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT
FR3059144A1 (en) * 2016-11-22 2018-05-25 Stmicroelectronics (Rousset) Sas METHOD OF FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTERCONNECTION PART OF AN INTEGRATED CIRCUIT WITHOUT ADDING ADDITIONAL MATERIAL, AND CORRESPONDING INTEGRATED CIRCUIT
CN108091576A (en) * 2016-11-22 2018-05-29 意法半导体(鲁塞)公司 Method and the corresponding integrated circuit that at least one electricity interrupts are formed in integrated circuits
US10049991B2 (en) 2016-11-22 2018-08-14 Stmicroelectronics (Rousset) Sas Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit, and corresponding integrated circuit
US10049982B2 (en) 2016-11-22 2018-08-14 Stmicroelectronics (Rousset) Sas Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit without addition of additional material, and corresponding integrated circuit
US10177101B2 (en) 2016-11-22 2019-01-08 Stmicroelectronics (Rousset) Sas Method for forming at least one electrical discontinuity in an integrated circuit, and corresponding integrated circuit
US10861802B2 (en) 2016-11-22 2020-12-08 Stmicroelectronics (Rousset) Sas Method for forming at least one electrical discontinuity in an integrated circuit, and corresponding integrated circuit

Also Published As

Publication number Publication date
JPH0374032B2 (en) 1991-11-25

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