GB2405531A - Integrated circuit with reverse engineering protection - Google Patents

Integrated circuit with reverse engineering protection Download PDF

Info

Publication number
GB2405531A
GB2405531A GB0427115A GB0427115A GB2405531A GB 2405531 A GB2405531 A GB 2405531A GB 0427115 A GB0427115 A GB 0427115A GB 0427115 A GB0427115 A GB 0427115A GB 2405531 A GB2405531 A GB 2405531A
Authority
GB
United Kingdom
Prior art keywords
integrated circuit
reverse engineering
engineering protection
circuit structure
controlled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0427115A
Other versions
GB2405531B (en
GB0427115D0 (en
Inventor
Lap-Wai Chow
Jr William M Clark
James P Baukus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HRL Laboratories LLC
Raytheon Co
Original Assignee
HRL Laboratories LLC
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HRL Laboratories LLC, Raytheon Co filed Critical HRL Laboratories LLC
Publication of GB0427115D0 publication Critical patent/GB0427115D0/en
Publication of GB2405531A publication Critical patent/GB2405531A/en
Application granted granted Critical
Publication of GB2405531B publication Critical patent/GB2405531B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Power Engineering (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Bipolar Transistors (AREA)
  • Non-Volatile Memory (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness is disposed among said plurality of layers to thereby render the integrated circuit structure intentionally inoperable.

Description

GB 2405531 A continuation (71) cont Raytheon Company (Incorporated in USA
- Delaware} 141 Spring Street, Lexington, Massachusetts 02173, United States of America (72) Inventor(s): Lap-Wai Chow William M Clark Jr James P Baukus (74) Agent and/or Address for Service: Langner Parry High Holborn House, 52-54 High Holborn, LONDON, WC1V ERR, United Kingdom
GB0427115A 2002-05-14 2003-05-06 Integrated circuit with reverse engineering protection Expired - Fee Related GB2405531B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37815502P 2002-05-14 2002-05-14
PCT/US2003/014058 WO2003098692A1 (en) 2002-05-14 2003-05-06 Integrated circuit with reverse engineering protection

Publications (3)

Publication Number Publication Date
GB0427115D0 GB0427115D0 (en) 2005-01-12
GB2405531A true GB2405531A (en) 2005-03-02
GB2405531B GB2405531B (en) 2006-04-12

Family

ID=29549915

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0427115A Expired - Fee Related GB2405531B (en) 2002-05-14 2003-05-06 Integrated circuit with reverse engineering protection

Country Status (5)

Country Link
JP (1) JP4729303B2 (en)
AU (1) AU2003245265A1 (en)
GB (1) GB2405531B (en)
TW (1) TWI226697B (en)
WO (1) WO2003098692A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008507851A (en) * 2004-07-26 2008-03-13 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Chip with light protection layer
FR3069370B1 (en) 2017-07-21 2021-10-22 St Microelectronics Rousset INTEGRATED CIRCUIT CONTAINING A LURE STRUCTURE
US11257769B2 (en) * 2019-06-28 2022-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit layout, integrated circuit, and method for fabricating the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61147551A (en) * 1984-12-21 1986-07-05 Nec Corp Semiconductor device
EP0186855A2 (en) * 1984-12-25 1986-07-09 Kabushiki Kaisha Toshiba Semiconductor read only memory device and method of manufacturing the same
WO1998057373A1 (en) * 1997-06-13 1998-12-17 Inside Technologies Method for making an integrated circuit and integrated circuit produced by said method
US5895241A (en) * 1997-03-28 1999-04-20 Lu; Tao Cheng Method for fabricating a cell structure for mask ROM
EP1193758A1 (en) * 2000-10-02 2002-04-03 STMicroelectronics S.r.l. Anti-deciphering contacts
EP1202353A1 (en) * 2000-10-27 2002-05-02 STMicroelectronics S.r.l. Mask programmed ROM and method of fabrication

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63296368A (en) * 1987-05-28 1988-12-02 Matsushita Electronics Corp Complementary type mos semiconductor device
JPH02192761A (en) * 1989-01-20 1990-07-30 Sony Corp Manufacture of semiconductor device
JP4931267B2 (en) * 1998-01-29 2012-05-16 ルネサスエレクトロニクス株式会社 Semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61147551A (en) * 1984-12-21 1986-07-05 Nec Corp Semiconductor device
EP0186855A2 (en) * 1984-12-25 1986-07-09 Kabushiki Kaisha Toshiba Semiconductor read only memory device and method of manufacturing the same
US5895241A (en) * 1997-03-28 1999-04-20 Lu; Tao Cheng Method for fabricating a cell structure for mask ROM
WO1998057373A1 (en) * 1997-06-13 1998-12-17 Inside Technologies Method for making an integrated circuit and integrated circuit produced by said method
EP1193758A1 (en) * 2000-10-02 2002-04-03 STMicroelectronics S.r.l. Anti-deciphering contacts
EP1202353A1 (en) * 2000-10-27 2002-05-02 STMicroelectronics S.r.l. Mask programmed ROM and method of fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN, Vol. 0103, No. 43 (E-456), 19 November 1986; & JP 61 147551 A (NEC CORP), 5 July 1986 *

Also Published As

Publication number Publication date
AU2003245265A1 (en) 2003-12-02
JP4729303B2 (en) 2011-07-20
GB2405531B (en) 2006-04-12
TW200400611A (en) 2004-01-01
GB0427115D0 (en) 2005-01-12
WO2003098692A1 (en) 2003-11-27
TWI226697B (en) 2005-01-11
JP2005526401A (en) 2005-09-02

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20150506