200400611 玖、發明說明： 相關申請案之交互參照 本木％求美國臨時專利申請案6〇/378，丨55，申請日2〇〇2 年5月14日之權益’該案以引用方式併入此處。 5【發明所屬之技術領域】 發明領域 本發明概略係有關積體電路及半導體元件(ICs)及其製 造方法，其中該積體電路及半導體元件採用偽裝技術，因 此讓還原工程師難以辨識該半導體元件之製造方式。 10 树_有關下列美@專利案，各案皆由相同申請人 提出申請。 ⑴美國專利第5,866,933 ; 5,973,375及6,294,816號說明 CMOS電路之電晶體如何藉修改p+及源/没罩而經由植入 (因此隱藏且埋置）線路於電晶體間而連結。此等植入式互連 15結構用於製造對還原工程師而言，外觀實質上相同的3-輸 入端AND電路及3-輸入端〇R電路。此外，埋置的互連裝置 迫使退原工程師以較深深度檢驗IC，嘗試找出電晶體間之 連結性因而找出電晶體。200400611 发明 Description of the invention: Cross-references to related applications for this application% Seeking US Provisional Patent Application No. 60/378, 丨 55, Rights of Application Date May 14, 2002 'This case is incorporated by reference Here. 5 [Technical field to which the invention belongs] Field of the invention The outline of the present invention relates to integrated circuits and semiconductor elements (ICs) and manufacturing methods thereof, wherein the integrated circuits and semiconductor elements use camouflage technology, so that it is difficult for a reduction engineer to identify the semiconductor element. Of manufacturing methods. 10 树 _For the following US @ patent cases, each case is filed by the same applicant. ⑴U.S. Patent Nos. 5,866,933; 5,973,375 and 6,294,816 show how transistors in CMOS circuits can be connected between transistors by modifying p + and source / no mask via implanted (thus hidden and buried) circuits. These implantable interconnections 15 structures are used to manufacture 3-input AND circuits and 3-input OR circuits that have substantially the same appearance to the restoration engineer. In addition, the buried interconnects forced retired engineers to examine the IC at a deeper level, trying to find the connectivity between the transistors and thus the transistors.
(2)美國專利第 5,783,846 ; 5,930,663 及 6,064，110 號教示 20 源/没植入罩之另一種修改，讓植入的電晶體間之連結線中 有間隙，該間隙長度近似使用之CM0S技術最小結構大小。 若此間隙係以一種植體「填補」，則線路為導通；但若該間 隙係以另一種植體「填補」，則該線路未導通。蓄意間隙稱 作為「通道阻斷」。還原工程師被迫基於解出於使用之CMOS 5 200400611 方法之最小結構尺寸的植體類型來決定連結性。 (3)美國專利第6，117,762號教示一種保護半導體積體電 路防止還原工程之方法及裝置。半導體主動區形成於基材 上，矽化金屬層形成於半導體主動區之至少一主動區上， 5 以及一選定基材區域上，該選定基材區係供透過形成於基 材選定區之石夕化金屬區而互連至少一主動區與另一區之 用。(2) U.S. Patent Nos. 5,783,846; 5,930,663 and 6,064,110 teach another modification of the source / non-implanted cover, so that there is a gap in the connection line between the implanted transistors, and the gap length is approximately the smallest using the CMOS technology Structure size. If the gap is "filled" with one implant, the line is conducting; but if the gap is "filled" with another implant, the line is not conducting. A deliberate gap is called a "channel block." Reduction engineers were forced to determine connectivity based on the type of implant that had the minimum structural size of the CMOS 5 200400611 method used. (3) U.S. Patent No. 6,117,762 teaches a method and apparatus for protecting a semiconductor integrated circuit from a reduction process. A semiconductor active region is formed on the substrate, a silicided metal layer is formed on at least one active region of the semiconductor active region, and 5 and a selected substrate region, the selected substrate region is provided for transmission through the stone evening formed on the selected region of the substrate. The metal region is used to interconnect at least one active region and another region.
C 發明背景 10 複雜積體電路及半導體元件之形成於此種裝置設計上 需要大量複雜的工程技能小時時可能極為昂貴。此外，積 體電路可包括唯讀記憶體(R0M)及/或EEPROMs，於其中以 韌體形式編碼軟體。此外，積體電路常用於涉及資訊加密 之應用用途，因此為了維持資訊的保密，可能需要維持半 15導體元件防止還原工程。如此有多項理由需要保護積體電 路及其它半導體防止還原工程。 為了防止還原工程，業界已知多種不同技術來讓積體 :路對還原工程師而言變成更難以進行。其中一項技術係 2〇疒^ S肢間的連結難以決定，迫使還原工程師審慎分析各 固=晶體(特別對CM〇S元件之各個CMOS電晶體對）。經由 晶體間的連結，還原工程師無法使用自動電路技術 有圖案4別技術來還原工程一積體電路。因積體電路可能 折數十萬或甚至數百萬粒電晶體，迫使還原工程師審慎分 元件内的各個電晶體，可有效成功地挫折還原工程師 6 200400611 對元件還原工程的能力。 前述先前技術若成功時，將迫使還原工程師研究金屬 連結，試圖解出標準電路邊界及其功能。例如閘連結利用 複晶矽層（典型為於具有二或二以上複晶矽層方法之第一 5 複晶矽層）及還原工程，了解此種閘電接點為典型電晶體輸 入端，因而輸入標準電路將尋找此種電接點。此外透過金 屬互連裝置製作源及汲電接點至基材。還原工程師之一項 工作方式係利用尋找矽-至-閘複晶矽金屬線來尋找晶格邊 界，原因在於尋找矽-至-閘複晶矽金屬線提示一電晶體晶格 10 之輸出端（汲電接點）至次一電晶體晶格輸入端（閘電接點） 間之接觸之可能。若可如此進行，則還原工程師可藉此等 矽-閘複晶矽金屬線而界定晶格邊界。然後經由觀察晶格邊 界，還原工程師可找出晶格特性（例如電晶體大小及數目）， 如此對晶格功能作出合理假設。然後此項資訊可儲存於資 15 料庫供自動分類其它類似晶格。 本發明之一目的係讓還原工程變得更困難，特別本發 明係迫使還原工程師極為審慎地研究可能之矽-至-閘複晶 矽金屬線，瞭解其是否實際上為真實。相信如此將讓為了 還原工程本發明採用之晶片導致的極為耗時而讓還原工程 20 師之努力更加困難，或許即使並非不可能，也讓還原工程 採用本發明之晶片變成不實際。 本發明人先前提出專利申請，且已經獲得專利，有關 如前文討論偽裝積體電路元件俾讓其更難以還原工程之技 術。本發明可與此等先前美國專利案揭示之技術協調用於 7 進一步造成還原工程師的困擾。 於近代半導體製程，特別是結構尺寸小於0.5微米之製 程，矽化金屬層典型用來改良傳導性。第1圖為一半導體元 件之平面圖。第ΙΑ、1B及1C圖為第1圖之平面圖所示之半 導體元件之剖面圖。典型汲或源電接點顯示於第1A圖，而 典型閘接點顯示於第1B圖。汲、源及閘區係形成於半導體 基材如半導體基材10上，有主動區12、16、18(第1C圖所示) 形成於其中’典型係藉植入適當攙雜劑而形成各主動區於 其中。場氧化物(F〇X)20用來以尋常方式輔助隔開一半導體 元件與另一元件。如第1A圖所示，；:及接點結構有習知石夕化 金屬層26-1形成於其主動區18上方。耐火金屬接點30及插 塞31之組合形成於矽化金屬層26-1上。矽化金屬層26-1提供 耐火金屬閘接點30與插塞3丨之組合之表面，金屬接點經常 包括耐火金屬插塞31，插塞延伸貫穿介電層29(可為沉積二 氧化石夕）之開口。耐火金屬閘接點30及金屬插塞31之組合與 石夕化金屬層26-1作接觸。源結構係類似第1 a圖所示汲結 構’此處主動區18係由主動區16所替代。 如第1B圖所示，閘結構有相對薄之閘氧化物層22，層 22^、由—層複晶矽24-1層所覆蓋，層24-1又係由矽化金屬層 26^所覆蓋(矽化金屬層26-1當如同此處案例用於複晶矽層 24-1時’傳統上稱作為「自我對準矽化物」層）。矽化金屬 層26_1姆耐火金屬閘接點3〇提供一表面，金屬接點經常包 括耐火金屬插塞31，插塞31延伸貫穿介電層29之開口，介 包層29可為沉積二氧化矽。金屬插塞31與矽化金屬層26-1 200400611 接觸。 第1C圖為通過半導體元件之主動區16、18以及閘區12 之剖面圖。側壁隔件21提供處理過程之間區12與主動區 16、18間之分隔。第1C圖之其餘細節同第1A及1B圖。熟諳 5 技藝人士了解其它製造細節可由圖式删除，該等製造細節 之使用為業界眾所周知。 先前技術也常見使用雙重複晶矽CMOS製造方法。此 種方法目前有許多商業iC晶片製造商特別是晶片卡晶片製 造商使用。雙重複晶矽（或簡稱為雙重複晶矽）方法可用來製 10 造多種元件，包括CMOS電晶體對、浮動閘結構，甚至雙極 性電晶體。例如參考Chen等人之美國專利第4,784,966號。 雙重複晶矽CMOS方法也支援EEPROMs之製造，eepr〇Ms 常用於晶片卡晶片等用途。 I：發明内容】 15 發明概要 20 於-方面，本發明提供一種經偽裝之電路結構，包含 一半導體基材；-植人區於該基材；—金屬層其係關聯該 植入區’於平面圖顯然係電_合至該植人區；以及一介 電層’其係設置於雜w與㈣層間，因㈣離層與植 入區’介電層之尺福t於該平面圖觀視時 至少部分被電路結狀1結_隱藏。 、，本發明之另—方面提供—種經偽裝之電路結構，包含 半％•體基材；—絲^該基材；—傳導層，該傳導層 係結合該主動區，以及傳道 、、曰 、¥層於平面圖顯然排列成藉施加 9 2〇〇40〇611 控制電壓可影響經由主動區 〈得v，一控制電極，苴 合該傳導層，該控制電極於平而网a ，、知〜且 ㈣於千面圖呈現電性連結至該傳導 層，以及至少一介電；#罢认斗/;fe 役處 曰叹置於该傳導層與該控制電極間， 1、回應於施加控制電麼至 一 4工制電極，畜意防止該傳導 影響經由主動區之傳導。 心層 本發明之另-方面提供—種防止還原工程師之方法， 该方法包含下❹驟：„至少—傳導性接點與一主動 區，以及經由插人介於其間之絕緣層而防止至少—傳導性 接點與該主動區間之電傳導。 . 10 15 20 面圖觀視時 μ本發明之另一方面提供一種偽電晶體，包含··-主動區 σ又置於-基材，—絕緣之非電性料層設置於該主動區之 至少-部分；_複晶發層設置於該設置於該主動區之至少 一部分上之絕緣非電轉導層之至少-部分上，該絕緣非 電性傳導層電絕緣複㈣層與絲m—金屬層與複 晶石夕層電通訊，而與主動區電隔離，該絕緣之非電性傳導 層、複晶矽層及金屬層各自之尺寸為當於平 该金屬層顯然係與主動區電通訊。 本發明之另一方面提供一種非可操作之半導體閘接 ”、、占^3'金屬層；一第一複晶矽層；一第二複晶矽層設 置於該金屬層與·_複晶碎層間；以及—絕緣之非傳導 性層至少係設置於該第_複晶㈣與該第二複晶碎層間。 本i月之另一方面提供一種製造一偽電晶體之方法，該 方法包含下列步驟:植入一主動區於一基材；安置一介電層於 該主動區之至少—部分上；以及設置一金屬層於該介電層 10 200400611 上，其中該介電層可防止該主動區與該金屬層間之電接觸。 本發明之另一方面提供一種混淆還原工程師之方法， 該方法包含下列步驟:植入一主動區於一基材；關聯一傳導 層與該主動區；設置一介電層於該傳導層上；以及提供一 5 控制電極，其中回應於控制電壓之施加至控制電極，該介 電層可防止傳導層影響經由該主動區之傳導。 本發明係與標準雙重複晶矽CMOS方法相容，其中於 主動區植入亦即於源及汲植入後沉積複晶矽層（典型為第 二複晶矽層或上複晶矽層）中之至少一者。先前技術方法係 10 經由安置一介電層於一名目接觸區而修改，因而廢除作為 標準金屬接點之該金屬接點。如此至少可以如下二方面進行: (1) 第二複晶矽區與氧化物組合沉積於源或汲接觸區上 方，該區隨後將施用金屬接點。藉此方式，金屬接點未電 性連結至下方源區或汲區，因此顯然為接點之處無法發揮 15 接點功能。但對還原工程師而言，金屬接點顯然為正常金 屬接點，因此還原工程師將假設關聯之該電晶體為可操作。 (2) 第二複晶矽區及氧化物組合係設置於一自我校準之 複晶矽閘層上方，造成隨後沉積之金屬閘無法發揮功能。 如此一種還原工程師看來似乎是電晶體之結構（後文 20 稱作為偽電晶體）可於電路内比其顯然具有之功能而發揮 不同功能，該偽電晶體係經由（i)讓其閘變成不具功能，或 (ii)讓其汲接點變成不具功能或（iii)讓其源接點變成不具功 能或（iv)前述之任一種組合發揮效果。由於偽電晶體的存 在’运原工程師當嘗試拷貝原先的積體電路時5傾向於假 11 200400611 設各個偽電晶體為適當電晶體，造成其拷貝的電路無法發 揮正確功能。電路的真實功能係隱藏於使用該偽電晶體之 電路内部。當然若數百或數千個偽電晶體用於或許有數百 萬電晶體之複雜積體電路，還原工程師將該偽電晶體解譯 5 為功能電晶體，還原工程師不僅得知元件無法發揮功能， 同時於分析預備還原工程之晶片與找出誤導之處，嘗試理 出其錯誤時帶來的大量工作。進行此種額外努力，迫使還 原工程師耗費額外的時間嘗試決定該晶片之實際組態。 經由審慎研究，還原工程師偵測出此處揭示之讓偽電 10 晶體變成無法操作之技術。但相信偵測出本發明之技術將 耗費足夠時間來拖延還原工程師。複雜積體電路包含數百 萬個CMOS電晶體，若還原工程師須審慎分析各個CMOS電 晶體對，俾決定本發明是否用來偽裝各個CMOS電晶體，則 此種積體電路還原工程涉及的努力將極為大量。 15 此處揭示之技術可用於讓電路變成不具功能。但相信 揭示之技術較佳係用於應用用途，（並非讓電路變成不具功 能）電路仍然有功能之用途，但係以非期望方式發揮功能。 還原工程師最終將獲得一種拷貝其「似乎」有效，但實際 上無法工作來獲得有用或期望的結果。 20 注意涉及偽電晶體之本發明不僅須找出千分之一有問 題晶片，反而還原工程師必須審慎分析各個電晶體，完全 了解各個電晶體，但電晶體藉本發明修改之機率極低。因 此還原工程師所面對的工作可用俗話大海撈針來形容。 圖式簡單說明 12 200400611 第1圖為第1A、1B及1C圖之半導體元件之平面圖； 第ΙΑ、1B及1C圖為主動區之金屬接點（參考第1A圖）及 閘區之金屬接點（參考第1B圖）之側視平面圖，以及貫穿主 動區及閘區之剖面圖（參考第1C圖）； 5 第2圖為使用習知雙重複晶矽處理通過閘區之剖面圖； 第3圖為半導體元件之平面圖，該半導體元件也顯示於 第3A、3B及3C圖； 第3 A圖為沿第3圖之線3 A-3 A之側視剖面圖，該圖係通 過採用矽化金屬/自我對準矽化物層之CMOS電晶體之汲接 10 點或源接點，其中利用一層氧化物來讓相關接點變成無法 操作； 第3B圖為沿第3圖之線3B-3B之側視剖面圖，該圖毗鄰 於閘區，且顯示矽化金屬/自我對準矽化物層以及毗鄰閘區 之氧化物層如何讓閘接點變成無法操作；以及 15 第3C圖為沿第3圖線3C-3C之剖面圖，顯示通過源、閘 及汲區之各層。 C 万包方式】 較佳實施例之詳細說明 第3圖為半導體元件之平面圖’該半導體元件顯然為場 20 效電晶體(FET)。但如第3A、3B及3C圖之剖面圖可知，該 半導體元件為偽電晶體。第3A圖顯示第1A圖所示接點如何 蓄意藉本發明「破壞」而形成偽電晶體。同理，第3B圖顯 示第1B圖所示閘結構如何蓄意藉本發明「破壞」而形成偽 電晶體。第3C圖為閘區12及主動區16、18之剖面圖，至主 13 200400611 動區18之接點蓄意藉本發明破壞而形成偽電晶體。熟諳技 藝人士了解雖然各圖顯示加強模式元件，但偽電晶體也可 為耗盡模式元件。此時閘、源或汲接點蓄意藉本發明「破 壞」。以耗盡模式電晶體為例，若閘接點被「破壞」，則當 5 名目電壓施加於控制電極時，半導體元件將為「ON」。若 源或汲接點被「破壞」時，則對施加於控制電極之名目電 壓而言，偽耗盡模式電晶體大致為「OFF」。 第2圖顯示近代雙重複晶矽半導體處理使用之典型製 程尺寸。雙重複晶矽處理較佳包括兩層複晶矽24-1、24-2， 10 也有兩層自我對準碎化物26-1、26-2。所顯示之厚度為較佳 厚度。雙重複晶矽處理也可用於獲得第3、3A、3B及3C圖 所示結構。熟諳技藝人士 了解第3、3A、3B及3C圖所示結 構非僅限於第2圖所示厚度尺寸。 第3圖顯示偽-FET電晶體之平面圖，但熟諳技藝人士了 15 解兩極性電晶體之金屬接點極為類似所示源/汲接點。第3A 圖為偽電晶體之側視平面圖，（由第3圖之頂部觀視）該部分 對還原工程師顯示為CMOS FET之主動區金屬層30、31。 另外，元件可為垂直兩極性電晶體，該種情況下金屬層30、 31被還原工程師視為射極接點。如第3A圖所示，對CMOS 20 結構而言，主動區18可以習知方式使用場氧化物20為區域 邊界形成。主動區18係經由閘氧化物22植入（參考第3C 圖），閘氧化物22隨後由主動區上方被去除，選擇性以矽化 金屬替代，然後石夕化金屬被燒結而產生石夕化金屬層26-1。 其次沉積介電層28。較佳具體實施例中，介電層為二氧化 14 200400611 矽（Si02)層28。此外複晶矽層24-2可沉積於二氧化矽層28上 方。複晶矽層24-2較佳為雙重複晶矽處理之第二複晶矽 層。然後選擇性之矽化金屬層26-2形成於複晶矽層24-2上 方。第二二氧化石夕（Si〇2)層29經沉積且經钱刻，俾允許金屬 5 層（包括金屬插塞31及金屬接點30)成形於選擇性之矽化金 屬層26-2上、或接觸複晶矽層24-2(若未利用矽化金屬層 26-2)。氧化物層28及氧化物層29較佳由相同材料（可能具有 不同密度）製成，因此當彼此疊置時對還原工程師而言無法 區別二者。 10 不同的遮罩用來形成複晶矽層24-2及金屬插塞31。為 了維持複晶矽層24-2與金屬插塞31間之對準，平行半導體 基材10之主面11之複晶矽層24-2之截面較佳設計為具有如 同於同一方向所取金屬插塞31之截面之相同尺寸，於製程 校準公差以内。如此，複晶矽層24-2至少部分被金屬插塞 15 31隱藏。於第3、3A、3B及3C圖，複晶矽層24-2顯示比金 屬插塞31遠較大；但各圖經誇大以求清晰。較佳複晶石夕層 24-2係設計成確保金屬插塞3 1之截面係對準複晶矽層24-2 之截面、或選擇性矽化金屬層26-2(若使用時）之截面但又夠 小而難以於顯微鏡下觀視。此外，金屬插塞31底部較佳完 20 全接觸複晶矽層24-2或選擇性之矽化金屬層26-2(若使用 時）。熟諳技藝人士了解製程校準公差因各製程而異。例如 對0.5微米製程而言，典型校準公差為0.1微米至0.15微米。 還原工程師不易獲得一平面圖，例如第2、3A、3B及 3C圖所示平面圖。實際上還原工程師獲得平面圖之典型方 15 200400611 式係透過於各個可能的接點或非接點拍攝的截面掃描電子 顯微相片。於各個可能接點或非接點拍攝顯微相片之程序 極為耗時且昂貴。但還原工程師由頂部觀視時，將看到金 屬接點30頂端，參考第3圖。帶有複晶石夕層24-2及選擇性之 5 矽化金屬層26-2之接觸廢除氧化物層28，將至少部分被電 路結構亦即金屬接點30及金屬插塞31所隱藏。 還原工程處理通常係涉及將半導體元件之各層去除， 去除各層直至矽基材1〇，然後由矽基材10之主面11法線方 向觀視半導體元件。此項處理過程，還原工程師將去除氧 10 化物層28之殘跡，氧化物層28於本發明係用來去能接點。 此外，還原工程師選擇代價更昂貴的方法只由半導體 區去除金屬接點3〇。複晶矽層24-2之截面較佳具有金屬插 塞31截面之大致相等尺寸，於製程校準公差以内。氧化物 層28、29實際上為透明’選擇性之矽化金屬層26_2及複晶 15 矽層24-2之厚度小。典型選擇性矽化金屬層26_2厚度為 100-200埃。典塑複晶石夕層24-2厚度為2500-3500埃。如此由 頂部觀視元件時’還原工程師將假定金屬插塞3丨係接觸石夕 化金屬層26-1 ’因而獲得該元件為可操作之錯疾假設。此 外當使用選擇性之矽化金屬層26-2時’ 一旦金屬插塞31被 2〇 去除，還原工程師觀察元件將更為混淆。當觀視矽化金屬 層26-2留下的閃爍位置’還原工程師將獲得該閃爍位置係 由金屬插塞31留下的錯誤假設。如此還原工程師再度錯誤 假設該接點為可操作。 第3B圖為第3圖之偽電晶體之閘接點之側視平面圖。由 16 200400611 ㈣可知沿物烟取之第糊之視圖係貫 物22、貫穿第-複晶働-1以及貫穿第一魏金;: 26小各層娜成於半導體基㈣(典型為列之場氧化物^ 20與間區12上方介於主動區16與18間（參考第3C圖）。第— 複晶石夕層24·ι係、料傳導層，若此元件之功能正常，貝㈣ 由施加控制電壓，轉導層灣通·㈣之傳導。主: 區16 18及12、間氧化物22、第―複晶硬層24]以及第— ίο 15C BACKGROUND OF THE INVENTION 10 The formation of complex integrated circuits and semiconductor components on such device designs can be extremely expensive when a large number of complex engineering skills are required. In addition, the integrated circuit may include read-only memory (ROM) and / or EEPROMs, in which software is encoded as firmware. In addition, integrated circuits are often used in applications involving information encryption, so in order to maintain the confidentiality of information, it may be necessary to maintain semi-conducting components to prevent restoration projects. There are many reasons for protecting integrated circuits and other semiconductors from reduction projects. To prevent reduction engineering, the industry knows a number of different technologies to make integration: roads more difficult for reduction engineers. One of the technical systems is difficult to determine the connection between the limbs, forcing the reduction engineer to carefully analyze each solid = crystal (especially for each CMOS transistor pair of the CMOS device). Through the connection between the crystals, the restoration engineer cannot use the automatic circuit technology and the pattern technology to restore the integrated circuit. Because the integrated circuit may break hundreds of thousands or even millions of transistors, forcing the reduction engineer to carefully divide the individual transistors in the element, it can effectively and successfully frustrate the reduction engineer's ability to restore the component. If the previous techniques described above are successful, they will force reduction engineers to study metal connections in an attempt to solve standard circuit boundaries and their functions. For example, the gate connection uses a polycrystalline silicon layer (typically the first 5 polycrystalline silicon layer with two or more polycrystalline silicon layers) and a reduction project. It is understood that this type of gate electrical contact is a typical transistor input terminal, so Input standard circuits will look for such electrical contacts. In addition, the source and the drain contact are made to the substrate through a metal interconnection device. One of the working methods of the reduction engineer is to find the lattice boundary by searching for the silicon-to-gate complex silicon metal wire, because the search for the silicon-to-gate complex silicon metal wire prompts the output of a crystal lattice 10 ( The possibility of contact between the drain contact) and the next crystal lattice input (gate contact). If this can be done, the reduction engineer can use this silicon-gate polycrystalline silicon metal line to define the lattice boundary. Then by observing the lattice boundary, the reduction engineer can find out the lattice characteristics (such as the size and number of transistors), so as to make reasonable assumptions about the lattice function. This information can then be stored in the database for automatic classification of other similar lattices. One of the objects of the present invention is to make the reduction engineering more difficult. In particular, the present invention forces the reduction engineer to study the possible silicon-to-gate complex silicon metal wire with great care to know whether it is actually real. It is believed that this will make the restoration engineer's efforts more difficult, if not impossible, and make the restoration process using the wafer of the invention impractical, if not impossible. The present inventor has previously filed a patent application and has already obtained a patent regarding the technology of camouflage integrated circuit elements as discussed above to make it more difficult to restore the engineering. The present invention can be used in harmony with the techniques disclosed in these previous U.S. patents to further cause problems for reduction engineers. In modern semiconductor processes, especially processes with a structure size of less than 0.5 microns, silicided metal layers are typically used to improve conductivity. Figure 1 is a plan view of a semiconductor device. Figures IA, 1B, and 1C are cross-sectional views of the semiconductor element shown in the plan view of Figure 1. A typical drain or source contact is shown in Figure 1A, and a typical gate contact is shown in Figure 1B. The source, gate, and gate regions are formed on a semiconductor substrate such as semiconductor substrate 10, and active regions 12, 16, 18 (shown in FIG. 1C) are formed therein. 'Typical systems are formed by implanting appropriate dopants. District in it. Field oxide (FOX) 20 is used to assist separation of one semiconductor element from another in a conventional manner. As shown in FIG. 1A,; and the contact structure is conventional. The metal layer 26-1 is formed above the active region 18. The combination of the refractory metal contact 30 and the plug 31 is formed on the silicided metal layer 26-1. The silicided metal layer 26-1 provides the surface of the combination of the refractory metal gate contact 30 and the plug 3, the metal contact often includes the refractory metal plug 31, and the plug extends through the dielectric layer 29. ) 'S opening. The combination of the refractory metal gate contact 30 and the metal plug 31 is in contact with the Shixihua metal layer 26-1. The source structure is similar to the drain structure shown in Fig. 1a. Here, the active area 18 is replaced by the active area 16. As shown in Figure 1B, the gate structure has a relatively thin gate oxide layer 22, which is covered by a layer of polycrystalline silicon 24-1, and layer 24-1 is covered by a silicide metal layer 26 ^ (The silicided metal layer 26-1, when used for the polycrystalline silicon layer 24-1 as in the case here, is traditionally referred to as a "self-aligned silicide" layer). The silicided metal layer 26_1 provides a surface of the refractory metal gate contact 30. The metal contact often includes a refractory metal plug 31 that extends through the opening of the dielectric layer 29. The dielectric cladding layer 29 may be deposited silicon dioxide. The metal plug 31 is in contact with the silicided metal layer 26-1 200400611. FIG. 1C is a cross-sectional view of the active regions 16 and 18 and the gate region 12 passing through the semiconductor element. The side wall spacer 21 provides a separation between the area 12 and the active areas 16, 18 between processes. The remaining details of Figure 1C are the same as Figures 1A and 1B. The skilled artisan understands that other manufacturing details can be removed from the drawings, and the use of such manufacturing details is well known in the industry. It is also common in the prior art to use a double-repeated silicon CMOS manufacturing method. This method is currently used by many commercial iC chip makers, especially chip card chip makers. The double-repeated crystalline silicon (or simply double-repeated crystalline silicon) method can be used to fabricate a variety of components, including CMOS transistor pairs, floating gate structures, and even bipolar transistors. See, for example, U.S. Patent No. 4,784,966 to Chen et al. The double-repeated silicon CMOS method also supports the manufacture of EEPROMs, and eeproMs are often used in chip card chips and other applications. I: Summary of the invention 15 Summary of the invention 20 In the aspect, the present invention provides a camouflaged circuit structure including a semiconductor substrate;-an implanted area on the substrate;-a metal layer associated with the implanted area 'on The plan is obviously electrically connected to the planting area; and a dielectric layer 'is arranged between the impurity layer and the pupal layer, because the ruler layer of the dielectric layer in the ionosphere and the implanted area is viewed from the plan view. At least partly hidden by a circuit knot. According to another aspect of the present invention, there is provided a camouflage circuit structure including a half-body substrate; a silk substrate; a conductive layer; the conductive layer is combined with the active area, and the preacher, The ¥ and ¥ layers are obviously arranged in a plan view to influence the application of a control voltage of 9200400611 via the active area. A control electrode is coupled to the conductive layer, and the control electrode is flat and a. It is shown in the thousand-square diagram that it is electrically connected to the conductive layer, and at least one dielectric; #STR recognize bucket /; fe office is sighed between the conductive layer and the control electrode, 1. In response to the application of control electricity What is more, a 4-working electrode prevents the conduction influence from conducting through the active area. Heart layer Another aspect of the present invention provides a method for preventing a reduction engineer, which method comprises the following steps: "at least-a conductive contact and an active area, and preventing at least by interposing an insulating layer interposed therebetween- Electrical conduction between the conductive contact and the active section. 10 15 20 When viewed from the top view, another aspect of the present invention provides a pseudo-transistor, including ...-the active area σ is placed on the-substrate,-insulation A non-electrical material layer is provided on at least a part of the active area; a polycrystalline hair layer is provided on at least a part of the insulating non-electrically conductive layer provided on at least a part of the active area; The conductive layer is electrically insulated from the composite layer and the wire m-metal layer and is in electrical communication with the polycrystalline stone layer, and is electrically isolated from the active area. The dimensions of the insulating non-conductive layer, the polycrystalline silicon layer, and the metal layer are When Yu Ping, the metal layer is clearly in electrical communication with the active area. Another aspect of the present invention provides a non-operational semiconductor gate connection, a metal layer of 3 ', a first polycrystalline silicon layer, and a second The polycrystalline silicon layer is arranged between the metal layer and the polycrystalline broken layer And - an insulating layer of non-conducting line is disposed between the at least first polycrystalline _ (iv) the second layer of polycrystalline broken. Another aspect of this month provides a method of manufacturing a pseudotransistor, the method comprising the steps of: implanting an active region on a substrate; placing a dielectric layer on at least a portion of the active region; and providing A metal layer is on the dielectric layer 10 200400611, wherein the dielectric layer can prevent electrical contact between the active area and the metal layer. Another aspect of the present invention provides a method for confusing a reduction engineer. The method includes the following steps: implanting an active region on a substrate; associating a conductive layer with the active region; and setting a dielectric layer on the conductive layer; And a 5 control electrode is provided, in which the dielectric layer can prevent the conductive layer from affecting the conduction through the active region in response to the control voltage being applied to the control electrode. The present invention is compatible with the standard double-repeated CMOS silicon method, in which a polycrystalline silicon layer (typically a second polycrystalline silicon layer or an upper polycrystalline silicon layer) is deposited after implantation in the active area, that is, after source and drain implantation. At least one of them. The prior art method 10 was modified by placing a dielectric layer in a mesh contact area, thus eliminating the metal contact as a standard metal contact. This can be done in at least the following two aspects: (1) A second polycrystalline silicon region and an oxide combination are deposited above the source or drain contact region, and then a metal contact is applied to this region. In this way, the metal contacts are not electrically connected to the underlying source or drain region, so obviously the 15-contact function cannot be performed for the contacts. However, for the reduction engineer, the metal contact is obviously a normal metal contact, so the reduction engineer will assume that the associated transistor is operable. (2) The second polycrystalline silicon region and oxide combination are placed above a self-calibrated polycrystalline silicon gate layer, causing the subsequently deposited metal gate to fail to function. Such a reduction engineer seems to have a transistor structure (hereinafter referred to as a pseudo transistor) that can perform different functions in the circuit than it obviously has. The pseudo transistor system turns its gate into (i) Non-functional, or (ii) making its drain contacts non-functional or (iii) making its source contacts non-functional or (iv) any combination of the foregoing to work. Because of the existence of the pseudo-transistor, when the original engineer tried to copy the original integrated circuit, 5 tended to be false. 11 200400611 Set each pseudo-transistor as an appropriate transistor, causing the copied circuit to fail to perform the correct function. The true function of the circuit is hidden inside the circuit using the pseudo-transistor. Of course, if hundreds or thousands of pseudo-transistors are used in a complex integrated circuit that may have millions of transistors, the reduction engineer interprets the pseudo-transistor as a functional transistor. The reduction engineer not only knows that the component cannot function At the same time, it analyzes the wafers of the preliminary restoration project and finds the misleading, trying to sort out a lot of work brought by its errors. This additional effort forces the restoration engineer to spend extra time trying to determine the actual configuration of the chip. After careful research, the restoration engineer detected the technology disclosed here that made the pseudo-electrical 10 crystal inoperable. However, it is believed that detecting the technology of the present invention will take sufficient time to delay the restoration engineer. The complex integrated circuit contains millions of CMOS transistors. If the reduction engineer must analyze each CMOS transistor pair carefully and decide whether the present invention is used to disguise each CMOS transistor, the effort involved in this integrated circuit reduction project will Extremely large. 15 The techniques disclosed here can be used to make circuits nonfunctional. However, it is believed that the disclosed technology is better for application purposes (not to make the circuit ineffective), but the circuit still has a functional purpose, but it functions in an unexpected way. The restore engineer will eventually get a copy that "seems" to work, but in reality will not work to obtain useful or desired results. 20 Note that the invention involving pseudo-transistors not only has to find one thousandth of the wafers in question, but the reduction engineer must carefully analyze each transistor and fully understand each transistor, but the probability of the transistor being modified by the present invention is extremely low. Therefore, the work faced by the restoration engineer can be described as the saying goes. Brief description of the drawing 12 200400611 Figure 1 is a plan view of the semiconductor device in Figures 1A, 1B, and 1C; Figures IA, 1B, and 1C are the metal contacts in the active area (refer to Figure 1A) and the metal contacts in the gate area (Refer to Figure 1B) a side plan view, and a cross-sectional view through the active area and the gate area (refer to Figure 1C); 5 Figure 2 is a cross-sectional view through the gate area using the conventional double-repeated crystalline silicon treatment; The figure is a plan view of a semiconductor element, which is also shown in Figures 3A, 3B, and 3C; Figure 3 A is a side cross-sectional view taken along line 3 A-3 A of Figure 3, which is made by using silicided metal / Self-aligned silicide layer of CMOS transistor with 10 points or source contacts, in which a layer of oxide is used to make the related contacts inoperable; Figure 3B is along the line 3B-3B of Figure 3 A cross-sectional view, which is adjacent to the gate and shows how the silicide metal / self-aligned silicide layer and the oxide layer adjacent to the gate make the gate contacts inoperable; and 15 Figure 3C is along line 3 3C-3C cross-sections showing layers passing through the source, gate, and drain zones. C Wanbao method] Detailed description of the preferred embodiment. Fig. 3 is a plan view of a semiconductor element. The semiconductor element is obviously a field effect transistor (FET). However, as can be seen from the sectional views of Figs. 3A, 3B, and 3C, the semiconductor element is a pseudotransistor. Figure 3A shows how the contacts shown in Figure 1A deliberately "break" the invention to form a pseudotransistor. Similarly, Figure 3B shows how the gate structure shown in Figure 1B deliberately "destructs" the invention to form a pseudo-transistor. FIG. 3C is a cross-sectional view of the gate region 12 and the active regions 16 and 18. The contacts to the main region 13 200400611 and the movable region 18 are intentionally damaged by the present invention to form a pseudo-transistor. Those skilled in the art understand that although the figures show enhanced mode elements, pseudo-transistors can also be depletion mode elements. At this time, the brake, source or sink point is deliberately "broken" by the present invention. Taking the depletion mode transistor as an example, if the gate contact is "broken", when 5 mesh voltages are applied to the control electrode, the semiconductor element will be "ON". If the source or sink point is "damaged", the pseudo-depletion mode transistor is approximately "OFF" for the nominal voltage applied to the control electrode. Figure 2 shows a typical process size used in modern double-repeated crystalline semiconductor processing. The double-repeated crystalline silicon treatment preferably includes two layers of polycrystalline silicon 24-1, 24-2, and 10 also has two layers of self-aligned fragments 26-1, 26-2. The thickness shown is the preferred thickness. Double repetitive crystalline silicon processing can also be used to obtain the structures shown in Figures 3, 3A, 3B, and 3C. Those skilled in the art understand that the structures shown in Figures 3, 3A, 3B, and 3C are not limited to the thickness dimensions shown in Figure 2. Figure 3 shows a plan view of a pseudo-FET transistor, but skilled artisans understand that the metal contacts of the bipolar transistor are very similar to the source / drain contacts shown. Figure 3A is a side plan view of the pseudotransistor. (Viewed from the top of Figure 3) This part is shown to the restoration engineer as the active area metal layers 30, 31 of the CMOS FET. In addition, the element may be a vertical bipolar transistor, in which case the metal layers 30, 31 are considered by the reduction engineer as emitter contacts. As shown in FIG. 3A, for the CMOS 20 structure, the active region 18 can be formed in a conventional manner using the field oxide 20 as a region boundary. The active region 18 is implanted through the gate oxide 22 (refer to Figure 3C). The gate oxide 22 is subsequently removed from the top of the active region, and is selectively replaced with a silicided metal. Layer 26-1. Dielectric layer 28 is deposited next. In a preferred embodiment, the dielectric layer is a silicon dioxide (SiO 2) layer 28. In addition, a polycrystalline silicon layer 24-2 may be deposited on the silicon dioxide layer 28. The polycrystalline silicon layer 24-2 is preferably a second polycrystalline silicon layer treated with double repetitive crystalline silicon. A selective silicided metal layer 26-2 is then formed above the polycrystalline silicon layer 24-2. The second silicon dioxide (SiO2) layer 29 is deposited and engraved, allowing 5 layers of metal (including metal plug 31 and metal contact 30) to be formed on the selective silicided metal layer 26-2, Or contact the polycrystalline silicon layer 24-2 (if the silicide metal layer 26-2 is not used). The oxide layer 28 and the oxide layer 29 are preferably made of the same material (possibly having different densities), so it is impossible for a reduction engineer to distinguish the two when stacked on top of each other. 10 Different masks are used to form the polycrystalline silicon layer 24-2 and the metal plug 31. In order to maintain the alignment between the polycrystalline silicon layer 24-2 and the metal plug 31, the cross-section of the polycrystalline silicon layer 24-2 parallel to the main surface 11 of the semiconductor substrate 10 is preferably designed to have metal as taken in the same direction. The same dimensions of the cross section of the plug 31 are within the process calibration tolerances. As such, the polycrystalline silicon layer 24-2 is at least partially hidden by the metal plug 1531. In Figures 3, 3A, 3B, and 3C, the polycrystalline silicon layer 24-2 shows much larger than the metal plug 31; however, the figures are exaggerated for clarity. The preferred polycrystalline stone layer 24-2 is designed to ensure that the cross section of the metal plug 31 is aligned with the cross section of the polycrystalline silicon layer 24-2, or the cross section of the selective silicided metal layer 26-2 (if used). But it is small enough to be viewed under a microscope. In addition, the bottom of the metal plug 31 is preferably completely contacted with the polycrystalline silicon layer 24-2 or the selective silicided metal layer 26-2 (if used). Skilled artisans understand that process calibration tolerances vary from process to process. For example, for a 0.5 micron process, typical calibration tolerances are 0.1 micron to 0.15 micron. It is not easy for the restoration engineer to obtain a floor plan, such as those shown in Figs. 2, 3A, 3B, and 3C. In fact, the typical method for the reduction engineer to obtain a floor plan is the 2004 00611 formula, which is a cross-section scanning electron micrograph taken through each possible contact or non-contact. The process of taking photomicrographs at every possible contact or non-contact is extremely time consuming and expensive. However, when the restoration engineer looks at the top, he will see the top of the metal contact 30, refer to Figure 3. The contact with the polycrystalline stone layer 24-2 and the selective 5 silicided metal layer 26-2 abolished the oxide layer 28, and will be at least partially hidden by the circuit structure, that is, the metal contact 30 and the metal plug 31. Reduction engineering usually involves removing each layer of the semiconductor element, removing each layer up to the silicon substrate 10, and then viewing the semiconductor element from the normal direction of the main surface 11 of the silicon substrate 10. In this process, the reduction engineer will remove the traces of the oxide layer 28, which is used to disable the contacts in the present invention. In addition, the reduction engineer chose a more expensive method to remove the metal contacts 30 only from the semiconductor region. The cross-section of the polycrystalline silicon layer 24-2 preferably has approximately the same size as the cross-section of the metal plug 31, within the process calibration tolerances. The oxide layers 28 and 29 are actually transparent'selective silicide metal layers 26_2 and complex 15 silicon layers 24-2 with small thickness. A typical selective silicided metal layer 26_2 has a thickness of 100-200 Angstroms. The thickness of Diansu polycrystalite layer is 2500-3500 angstroms. In this way, when viewing the component from the top, the 'reduction engineer will assume that the metal plug 3 丨 is in contact with the petrified metal layer 26-1' and thus obtain the false assumption that the component is operable. In addition, when using a selective silicided metal layer 26-2, once the metal plug 31 is removed by 20, the reduction engineer will observe the components more confusingly. When viewing the flickering position left by the silicided metal layer 26-2, the reduction engineer will obtain the false assumption that the flickering position is left by the metal plug 31. This restores the engineer's mistake again, assuming that the contact is operational. FIG. 3B is a side plan view of the gate contact of the pseudo transistor of FIG. 3. From 16 200400611, we can see that the view of the first paste taken along the object smoke is through object 22, through the first-compound crystal -1, and through the first Weijin; 26 small layers are formed on the semiconductor substrate (typically a field of columns) The oxide ^ 20 and the inter-region 12 are between the active regions 16 and 18 (refer to Figure 3C). The first-polycrystalline stone layer 24 · ι series, material conductive layer, if the function of this element is normal, the Applying a control voltage, the transduction layer conducts through the channel. Main: Areas 16 18 and 12, inter-oxide 22, the "multi-crystalline hard layer 24" and the "— 15"
iMti屬層26_UT、使用習知處理技術形成。對正常功能元 件而言，由金屬層3〇、31形成之㈣電極將接财化金屬 層26-i於場氧化物2G上該層。則魏金屬層26]係作為正常 功能元件之控制層。為了形成偽電晶體，沉積至少—介電 層，例如氧化物層28。其次第二複晶矽層24_2及選擇性之 第一矽化金屬層26-2係沉積於氧化物層μ上方。顯示於複 晶矽層24-2與金屬插塞31間之矽化金屬層26_2於某些製造 過程可被刪除，原因在於某些雙重複晶矽處理技術只利用 一層矽化金屬層（當此種處理技術只用於一層時，將使用矽 化金屬層26-1或26-2)。任一種情況下，閘之正常功能係被 氧化物層28所妨礙。 於平行於半導體基材10正常表面11方向之第二複晶石夕 20 層24-2之截面較佳係與於同向所取金屬插塞31截面相同大 小，於製程對準公差以内。如此第二複晶矽層24~2被金屬 插塞31所部分隱藏。於第3、3A、3B及3C圖，複晶矽層24、2 顯示為遠比金屬插塞31更大；但各圖誇大顯示以求清晰。 較佳複晶矽層24-2係設計成確保金屬插塞31之截面完全對 17 200400611 準複晶矽層24-2之截面或選擇性之矽化金屬層26-2(若使用 時）之截面，但有夠小而極難以於顯微鏡下觀視。此外，金 屬插塞31底部較佳完全接觸複晶矽層24-2或選擇性矽化金 屬層26_2(若使用時）。熟諳技藝人士瞭解製程校準公差因製 5 程而異。例如對0.5微米製程而言，典型之校準公差係於0.1 微米至0.15微米之範圍。 額外增加之氧化物層28及複晶矽層24-2係設置成其係 出現於由平面圖觀視時，金屬至複晶矽接點正常之出現位 置。該種定位讓金屬層30、31至少部分隱藏額外增加之氧 10 化物層28及/或複晶矽層24-2，因此該佈局對還原工程師而 言顯然為正常。還原工程師將蝕刻去除金屬層30、31，且 觀察複晶矽層24-2以及可能來自於（若使用時）選擇性矽化 金屬層26-2之殘跡。當觀察到來自選擇性矽化金屬層26-2 之閃亮殘跡時，還原工程師獲得該閃亮殘跡係來自於金屬 15 插塞31之錯誤假設。還原工程師毫無理由相信該接點並非 為複晶矽層24-1或選擇性之矽化金屬層26-1之接點。此外， 當未使用選擇性之矽化金屬層26-2時，由矽基材10之主面 11之法線方向觀視接點，無法清晰看見氧化物層28及複晶 矽層24-2之微小厚度，如此還原工程師將獲得結論，其觀 20 察到正常且有功能之複晶矽閘FET電晶體。 使用時，第3A圖、第3B圖及/或第3C圖之防止還原工 程技術只需要散在使用，但較佳組合其它還原工程技術使 用，例如前文於小標題「先前技術」討論之還原工程技術。 相關技術以及此處揭示技術之基本目的係讓極耗時來解出 18 200400611 電路係如何實作（因而可成功地複製電路），而造成還原工程 師畏怯於須付出大量努力。如此對近代ic之數千個元件而 言，只有其中一小部分係採用此處所述以及第3A、3B及3C 圖所示之偽電晶體來偽裝電路。因此除非還原工程師能夠 5 確定偽電晶體，否則還原工程師所測定之電路將不正確。 此外’偽電晶體較佳並非用於完全去能使用該偽電晶 體之多重電晶體電路，反而係讓該電路以非預期或非直覺 的方式發揮功能。例如對還原工程師顯示為OR閘可能實際 功能為AND閘。或顯示為反相輸入信號可能實際上為非反 10 相。其可能性幾乎為無限，且幾乎確實會造成還原工程師 挫折而放棄，並非迫切積極尋求發現如何還原工程應用此 等技術之積體電路元件。 此外當還原工程師蝕刻去除金屬30、31時，無論接點 是否根據本發明而阻擋，還原工程師將「看到」正常預期 15 層。如此若還原工程師預期於钱刻去除金屬後看到石夕化金 屬，則即使接點被阻擋，還原工程師仍將看到此種情況。 若還原工程師預期於蝕刻去除金屬後看到複晶矽，則即使 接點被阻擋，還原工程師仍將看到此種情況。 熟諳技藝人士瞭解其它介電材料如但化矽Si3N4可用來 20 替代二氧化矽。熟諳技藝人士瞭解矽化金屬層26-1及26-2 無需置於閘區。於近代半導體製程，特別為結構尺寸小於 0.5微米之半導體製程，典型使用矽化金屬層來改良傳導 性。但本發明係針對於接點實際上被去能位置對還原工程 師顯示出現功能電晶體。因傳導性並不重要且實際上可避 19 200400611 免傳導性，故當欲破壞接點時，矽化金屬層26-1及26-2無需 置於閘區。但矽化金屬層26-1及26-2可置於閘區，來簡化需 要的遮罩數目，因而減少半導體製程數目，進一步藉若干 還原工程處理期間留下的閃亮殘餘物來誤導還原工程師。 5 已經就若干較佳具體實施例說明本發明，對熟諳技藝 人士而言修改確實顯然自明。如此除非如隨附之申請專利 範圍特別要求，否則本發明並非囿限於揭示之具體實施例。 【圖式簡單說明】 第1圖為第ΙΑ、1B及1C圖之半導體元件之平面圖； 10 第ΙΑ、1B及1C圖為主動區之金屬接點（參考第1A圖）及 閘區之金屬接點（參考第1B圖）之側視平面圖，以及貫穿主 動區及閘區之剖面圖（參考第1C圖）； 第2圖為使用習知雙重複晶矽處理通過閘區之剖面圖； 第3圖為半導體元件之平面圖，該半導體元件也顯示於 15 第 3A、3B及3C 圖； 第3A圖為沿第3圖之線3A-3A之側視剖面圖，該圖係通 過採用矽化金屬/自我對準矽化物層之CMOS電晶體之汲接 點或源接點，其中利用一層氧化物來讓相關接點變成無法 操作； 20 第3B圖為沿第3圖之線3B-3B之側視剖面圖，該圖毗鄰 於閘區，且顯示矽化金屬/自我對準矽化物層以及毗鄰閘區 之氧化物層如何讓閘接點變成無法操作；以及 第3C圖為沿第3圖線3C-3C之剖面圖，顯示通過源、閘 及没區之各層。 20 200400611 【圖式之主要元件代表符號表】 10…半導體基材/矽 24-1，24-2…複晶矽層 11.. .主面 12…閘區 16，18…主動區 20.. .場氧化物 21.. .側壁隔件 22.. .閘氧化物層 26-1，26-2…矽化金屬層 28.. .介電層 29.. .介電層 30…金屬接點 31.. .金屬插塞iMti belongs to layer 26_UT and is formed using conventional processing techniques. For a normal function element, a rhenium electrode formed by the metal layers 30 and 31 will be connected to the metallized metal layer 26-i on the field oxide 2G. The Wei metal layer 26] is used as a control layer for normal functional elements. To form a pseudo-transistor, at least a dielectric layer, such as an oxide layer 28, is deposited. Secondly, a second polycrystalline silicon layer 24_2 and a selective first silicided metal layer 26-2 are deposited on the oxide layer μ. The silicided metal layer 26_2 shown between the polycrystalline silicon layer 24-2 and the metal plug 31 can be deleted in some manufacturing processes because some double-repeated crystalline silicon processing technologies use only one silicided metal layer (when such processing When the technology is used for only one layer, a silicided metal layer 26-1 or 26-2 will be used. In either case, the normal function of the gate is impeded by the oxide layer 28. The cross section of the second polycrystalite layer 20-2 parallel to the direction parallel to the normal surface 11 of the semiconductor substrate 10 is preferably the same as the cross section of the metal plug 31 taken in the same direction, within the alignment tolerance of the process. In this way, the second polycrystalline silicon layer 24 ~ 2 is partially hidden by the metal plug 31. In Figures 3, 3A, 3B, and 3C, the polycrystalline silicon layers 24 and 2 are shown to be much larger than the metal plug 31; however, the figures are exaggerated for clarity. The preferred polycrystalline silicon layer 24-2 is designed to ensure that the cross section of the metal plug 31 completely matches the cross section of 17 200400611 quasi-multicrystalline silicon layer 24-2 or the cross-section of the selective silicided metal layer 26-2 (if used) , But small enough and extremely difficult to see under a microscope. In addition, the bottom of the metal plug 31 is preferably in full contact with the polycrystalline silicon layer 24-2 or the selective silicided metal layer 26_2 (if used). Skilled artisans understand that process calibration tolerances vary from process to process. For example, for a 0.5 micron process, typical calibration tolerances range from 0.1 micron to 0.15 micron. The additional oxide layer 28 and the polycrystalline silicon layer 24-2 are arranged in such a manner that they appear at the normal position where the metal-to-polycrystalline silicon contact appears when viewed from a plan view. This positioning allows the metal layers 30, 31 to at least partially hide the additional oxygen oxide layer 28 and / or the polycrystalline silicon layer 24-2, so the layout is apparently normal to the reduction engineer. The reduction engineer will remove the metal layers 30, 31 by etching, and observe the polycrystalline silicon layer 24-2 and the residue that may come from (if used) the selective silicidation metal layer 26-2. When the shiny residue from the selective silicided metal layer 26-2 was observed, the reduction engineer obtained the false assumption that the shiny residue was from the metal 15 plug 31. The reduction engineer has no reason to believe that the contact is not a contact of the polycrystalline silicon layer 24-1 or the selective silicided metal layer 26-1. In addition, when the selective silicided metal layer 26-2 is not used, the contacts are viewed from the normal direction of the main surface 11 of the silicon substrate 10, and the oxide layer 28 and the polycrystalline silicon layer 24-2 cannot be clearly seen. With such a small thickness, the reduction engineer will come to the conclusion that his observation 20 observed a normal and functional complex silicon gate FET transistor. In use, the reduction prevention techniques in Figures 3A, 3B, and / or 3C need only be used scatteredly, but it is better to use them in combination with other reduction engineering techniques, such as the reduction engineering techniques discussed earlier in the subheading "Previous Technology" . The underlying purpose of the related technology and the technology disclosed here is to make it extremely time consuming to figure out how to implement the circuit system (and thus successfully replicate the circuit), causing restoration engineers to be timid and have to put in a lot of effort. So for thousands of components of modern IC, only a small part of it is using pseudo-transistors described here and shown in Figures 3A, 3B and 3C to disguise the circuit. Therefore, unless the reduction engineer can determine the pseudotransistor, the circuit determined by the reduction engineer will be incorrect. In addition, the 'pseudo-transistor' is preferably not used to completely disable the multi-transistor circuit using the pseudo-transistor, but rather to allow the circuit to function in an unexpected or non-intuitive manner. For example, it may be displayed as OR gate by the restoration engineer, and the actual function may be AND gate. Or the input signal displayed as inverted may actually be a non-inverting 10 phase. The possibilities are almost limitless, and it will almost certainly cause frustration engineers to frustrate and give up. It is not an eager and active search for discoveries on how to integrate these integrated circuit components into engineering. In addition, when the reduction engineer etches away the metals 30, 31, the reduction engineer will "see" the 15 layers normally expected, whether or not the contacts are blocked in accordance with the present invention. In this way, if the reduction engineer expects to see Shixi Huametal after the metal is removed, the reduction engineer will still see this situation even if the contact is blocked. If the reduction engineer expects to see polycrystalline silicon after the metal is removed by etching, the reduction engineer will still see this even if the contacts are blocked. Those skilled in the art will understand that other dielectric materials such as Si3N4 can be used instead of silicon dioxide. Those skilled in the art understand that silicided metal layers 26-1 and 26-2 need not be placed in the gate area. In modern semiconductor processes, especially semiconductor processes with a structure size of less than 0.5 micron, a silicided metal layer is typically used to improve conductivity. However, the present invention is directed to the fact that a functional transistor appears to the reduction engineer when the contact is actually deenergized. Since the conductivity is not important and can be avoided in practice, it is unnecessary to place the silicided metal layers 26-1 and 26-2 in the gate area when the contacts are to be destroyed. However, the silicided metal layers 26-1 and 26-2 can be placed in the gate area to simplify the number of masks required, thereby reducing the number of semiconductor processes, and further mislead the reduction engineer by using some shiny residues left during the restoration process. 5 The invention has been described in terms of several preferred embodiments, and modifications will be apparent to those skilled in the art. As such, the invention is not limited to the specific embodiments disclosed, unless specifically required by the scope of the accompanying patent application. [Schematic description] Figure 1 is a plan view of the semiconductor device in Figures IA, 1B, and 1C; 10 Figures IA, 1B, and 1C are the metal contacts in the active area (refer to Figure 1A) and the metal connections in the gate area Point (refer to Figure 1B), a side plan view, and a cross-sectional view through the active area and the gate area (refer to Figure 1C); Figure 2 is a cross-sectional view through the gate area using the conventional double-repeated crystalline silicon treatment; The figure is a plan view of a semiconductor element, which is also shown in Figures 3A, 3B, and 3C. Figure 3A is a side cross-sectional view taken along line 3A-3A of Figure 3. This figure is made by using silicide metal / self Align the drain contact or source contact of the CMOS transistor in the silicide layer, in which a layer of oxide is used to make the related contact inoperable; Figure 3B is a side cross-section along the line 3B-3B of Figure 3 Figure, which is adjacent to the gate region and shows how the silicide metal / self-aligned silicide layer and the oxide layer adjacent to the gate region make the gate contact inoperable; A cross-sectional view showing the layers passing through the source, gate, and zone. 20 200400611 [Representative symbols for main components of the drawing] 10… semiconductor substrate / silicon 24-1, 24-2… polycrystalline silicon layer 11 ... main surface 12… gate area 16, 18… active area 20 .. .Field oxide 21 ... sidewall spacer 22 ... gate oxide layer 26-1, 26-2 ... silicided metal layer 28 .. dielectric layer 29 .. dielectric layer 30 ... metal contact 31 .. metal plug
21twenty one