Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
  • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
  • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
  • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
  • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
  • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
  • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
  • H10P76/4083—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks

Definitions

• the present application relates to a semiconductor arrangement and a method for etching a layer of the semiconductor arrangement by means of a silicon-containing etching mask.
• Etching methods are usually used for structuring semiconductor substrates.
• an etching mask is applied to a layer to be structured and structured using photolithography. Some areas of the layer to be structured are now covered and protected by the etching mask, whereas other areas of the layer to be etched are exposed.
• the layer to be etched is removed using an etchant. The areas of the layer to be etched, which are covered by the etching mask, are thereby protected from the etching substance, so that on these
• Positions do not etch away on the layer to be etched. Since both the layer to be etched and the etching mask are exposed to the etching substance during the etching process, both layers are removed.
• An etching mask with a high selectivity with respect to the layer to be etched is usually selected using the etching agent. This means that the etching removal on the etching mask is significantly less than the etching removal on the layer to be etched. This makes it possible to etch deep structures into the layer to be etched using relatively thin etching masks.
• Typical materials used in silicon semiconductor technology are silicon, silicon oxide and silicon nitride. With a suitable etching substance, each of the three materials is suitable for being used as an etching mask for one or both of the other materials.
• an etching mask made of silicon is suitable for etching silicon oxide or silicon nitride in conjunction with an etching gas containing fluorocarbons.
• a semiconductor arrangement having a semiconductor substrate with a substrate surface on which a layer is arranged which contains silicon oxide or silicon nitride which has a surface with a silicon-containing mask layer which is arranged on the surface of the layer in order to be used for the layer To serve etching mask, wherein the mask layer additionally contains a sulfur or carbon-containing substance, the sulfur being in a sulfur-hydrogen compound or the carbon in a hydrocarbon chain, the substance being in a
• Pressure between 1 and 500 mTorr and a temperature between -20 ° C and 200 ° C forms a solid substance and as an oxidized and / or nitrided molecule forms a gaseous substance, which increases the etch resistance of the mask layer.
• the additional substance serves as an additive in the mask layer, as a result of which the etching rate of the silicon-containing mask layer is reduced. This advantageously ensures that the etching resistance of the silicon-containing mask layer is increased by the additional substance. For example, deeper trenches can be etched into a layer to be etched with a thinner mask layer. This is advantageous because a thin mask layer can be structured with a higher resolution than a thick mask layer by means of photolithography. Folg-
• V 0- HJ 3 ⁇ a H- SD et ⁇ • rt P- P- ⁇ tr ⁇ ⁇ IQ 0 C-. N ⁇ - ⁇ rt SU ⁇
• H- SD N SD ra ⁇ - N ⁇ ⁇ ⁇ CQ • Ü N o ⁇ rt C ⁇ ra ⁇ ⁇ Hi 0 H rt Hl ii 3 N ⁇ PC rt ⁇ C ⁇ ra SU ⁇ - ii ⁇ ü 0 o? C td M HJ
• ⁇ CQ! H ⁇ t tr ISI Hi ⁇ - ⁇ - 3 tr P P Hi ⁇ ⁇ rt rt _o tr H P P rt P C
• Carbon and sulfur are advantageously suitable for reducing the removal rate of silicon to which carbon or sulfur has been added in the case of an etching gas containing fluorocarbons.
• the substance contains aluminum, gallium, indium, thallium or boron in a concentration of more than 10 19 atoms per cm 3 and is electrically activated. Electrically activated means that boron is integrated in the lattice sites of the Si crystal lattice.
• the substances mentioned are p-dopants for the silicon-containing mask layer.
• a p-doped mask layer also has increased etch resistance.
• the layer to be etched contains silicon oxide or silicon nitride.
• Substance is implanted in the silicon-containing mask layer.
• a further embodiment of the invention provides that the substance is incorporated into the silicon-containing mask layer by means of a feed, during the formation of the silicon-containing mask layer.
• the object is achieved by a method for etching a layer of a semiconductor substrate with a silicon-containing etching mask with the steps: forming a layer which contains silicon oxide or silicon nitride on a substrate, the layer having a surface; - Forming a silicon-containing mask layer on the surface of the layer; Structuring the mask layer, a mask structure being formed;
• the etching mask partially protecting the surface from the etching gas.
• the method according to the invention leads carbon and / or sulfur together with an etching gas into an etching system, as a result of which the etching rate of the silicon-containing etching mask is reduced.
• One embodiment of the method according to the invention provides that the hydrocarbon molecules contained in the etching gas, which contain, for example, CH 4 and / or sulfur-hydrogen compounds, which contain, for example, SH 2, are enriched in or on the mask layer during the etching step.
• the enrichment in or on the mask layer has the advantage that the etching resistance of the silicon-containing etching mask is increased and thus its etching rate is reduced.
• a further advantageous method step provides that the carbon and / or sulfur atoms contained in the etching gas are enriched in or on the mask layer during the etching step.
• the enrichment of carbon and / or sulfur atoms also has the advantage that the etching rate of the silicon-containing mask layer is reduced.
• the figures show: 1 shows a substrate with a layer and a mask layer;
• FIG. 2 shows an arrangement according to FIG. 1, the layer being structured with the aid of the mask layer
• FIG 3 shows a representation of the etching rate over the angle of incidence of the etching gas, with and without additional substance.
• the substrate 1 shows a substrate 1 on which a layer 2 is arranged.
• the layer 2 has a surface 7 which faces away from the substrate 1.
• a mask layer 3 is arranged on the surface 7 of the layer 2.
• the mask layer 3 is designed such that it has a mask structure 4 as a trench in the mask layer 3.
• the substrate 1 consists, for example, of a silicon-containing material.
• Layer 2 contains silicon oxide and / or silicon nitride.
• the mask layer 3 contains silicon, and the silicon content can be up to 100%.
• a first variant provides that an additional substance 8 is contained in the silicon-containing mask layer 3.
• the additional substance is, for example, carbon and / or sulfur.
• the additional substance is deposited, for example, together with the mask layer 3 during the formation of the mask layer 3, as a result of which the substance 8 is built into the mask layer 3.
• Another method variant for forming the mask layer 3 first forms the mask layer 3 without the additional substance 8.
• the additional substance 8 is then introduced into the mask layer 3, for example by means of an implantation.
• p-dopants such as aluminum, gallium, indium, thallium and boron are suitable as further materials for the additional substance 8.
• the layer 2 is then etched in accordance with the arrangement shown in FIG. 2.
• FIG. 2 shows the arrangement shown in FIG. 1 at a later point in time.
• an etching was carried out with an etching gas containing fluorocarbons, a trench 5 being formed in layer 2 and a facet 6 being formed on mask layer 3.
• the substance 8 has the effect that the removal rate of the mask layer 2 is reduced and, in particular, has the effect that the removal rate at the forming facet angle is reduced.
• the facet angle between the substrate surface and the facet 6 is measured.
• a further exemplary embodiment according to FIG. 1 first forms the mask layer 3 without the additional substance 8. Subsequently, with reference to FIG. 2, the additional substance 8 is added to the etching gas and, in the course of the etching process, causes the etching selectively to increase since the additional substance 8 is in and / or accumulates on the mask layer 3. The removal rate of the mask layer 3 is thereby reduced. During the etching process, the substance 8 accumulates in the mask layer 3, as a result of which the etching selectivity is further increased.
• the layer 2 has a thickness of 1000 nm and is formed from silicon oxide and / or silicon nitride.
• the mask layer 3 can be formed, for example, from silicon with a thickness of 100 nm and additionally comprises the substance 8. ⁇ t to ⁇ 1 ⁇ > o L ⁇ o L ⁇ o L ⁇ o L ⁇
• Rt P ⁇ ⁇ N Pi SU P LQ rt SU CQ ⁇ - rt ⁇ 03 ⁇ ⁇ - Hj tS ⁇ ⁇ 03 ⁇ Hi P Hi P ⁇ Hi rt Hi rt SU Q ⁇ Hi Pi Sb ⁇ ⁇ - ⁇ SD cn Pi Hj Hl Z ⁇ ⁇ - o SU Hl Hi ⁇ SD ⁇ rt
• P rt ⁇ -3 SU ⁇ : rt o tr Hi K ⁇ CQ 3 03 ⁇ Q. td 3 tr rt ⁇ rt N ⁇ - ⁇ - rt ⁇ ⁇ LQ et. Hj LQ ⁇ ⁇ - ⁇ D ⁇ tr SU tr ⁇ - 03 P P et d ⁇ P tr ⁇ Hj tr ⁇ tr ⁇ - 03 ra ⁇ P- su ⁇ ⁇

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• Drying Of Semiconductors (AREA)

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Citations (4)

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• 2001
  • 2001-01-26 DE DE10103524A patent/DE10103524A1/de not_active Ceased
• 2002
  • 2002-01-17 WO PCT/DE2002/000130 patent/WO2002059951A1/de not_active Ceased
  • 2002-01-17 EP EP02700152A patent/EP1360711B1/de not_active Expired - Lifetime
  • 2002-01-17 KR KR10-2003-7009879A patent/KR100516839B1/ko not_active Expired - Fee Related
  • 2002-01-17 JP JP2002560183A patent/JP2004517505A/ja active Pending
  • 2002-01-17 DE DE50209714T patent/DE50209714D1/de not_active Expired - Fee Related
  • 2002-01-21 TW TW091100879A patent/TW548743B/zh not_active IP Right Cessation
• 2003
  • 2003-06-04 US US10/454,518 patent/US6864188B2/en not_active Expired - Lifetime

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