KR100516839B1 - 반도체 장치 및 실리콘 함유 에칭 마스크를 사용해서반도체 장치의 층을 에칭하는 공정 - Google Patents

반도체 장치 및 실리콘 함유 에칭 마스크를 사용해서반도체 장치의 층을 에칭하는 공정 Download PDF

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Publication number
KR100516839B1
KR100516839B1 KR10-2003-7009879A KR20037009879A KR100516839B1 KR 100516839 B1 KR100516839 B1 KR 100516839B1 KR 20037009879 A KR20037009879 A KR 20037009879A KR 100516839 B1 KR100516839 B1 KR 100516839B1
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KR
South Korea
Prior art keywords
layer
etching
mask layer
mask
silicon
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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KR10-2003-7009879A
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English (en)
Korean (ko)
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KR20030074745A (ko
Inventor
골드바흐마티아스
Original Assignee
인피네온 테크놀로지스 아게
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Publication of KR20030074745A publication Critical patent/KR20030074745A/ko
Application granted granted Critical
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4083—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks

Landscapes

  • Drying Of Semiconductors (AREA)
KR10-2003-7009879A 2001-01-26 2002-01-17 반도체 장치 및 실리콘 함유 에칭 마스크를 사용해서반도체 장치의 층을 에칭하는 공정 Expired - Fee Related KR100516839B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10103524A DE10103524A1 (de) 2001-01-26 2001-01-26 Verfahren und Halbleiteranordnung zur Ätzung einer Schicht eines Halbleitersubstrats mittels einer siliziumhaltigen Ätzmaske
DE10103524.1 2001-01-26
PCT/DE2002/000130 WO2002059951A1 (de) 2001-01-26 2002-01-17 Halbleiteranordnung und verfahren zur ätzung einer schicht der halbleiteranordnung mittels einer siliziumhaltigen ätzmaske

Publications (2)

Publication Number Publication Date
KR20030074745A KR20030074745A (ko) 2003-09-19
KR100516839B1 true KR100516839B1 (ko) 2005-09-26

Family

ID=7671843

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2003-7009879A Expired - Fee Related KR100516839B1 (ko) 2001-01-26 2002-01-17 반도체 장치 및 실리콘 함유 에칭 마스크를 사용해서반도체 장치의 층을 에칭하는 공정

Country Status (7)

Country Link
US (1) US6864188B2 (https=)
EP (1) EP1360711B1 (https=)
JP (1) JP2004517505A (https=)
KR (1) KR100516839B1 (https=)
DE (2) DE10103524A1 (https=)
TW (1) TW548743B (https=)
WO (1) WO2002059951A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7553770B2 (en) 2007-06-06 2009-06-30 Micron Technology, Inc. Reverse masking profile improvements in high aspect ratio etch
KR101972159B1 (ko) 2012-08-24 2019-08-16 에스케이하이닉스 주식회사 실리콘함유하드마스크를 구비한 반도체장치 및 그 제조 방법
KR102051529B1 (ko) 2013-03-25 2020-01-08 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법, 그리고 반도체 장치를 포함하는 마이크로프로세서, 프로세서, 시스템, 데이터 저장 시스템 및 메모리 시스템
CN111584358A (zh) * 2020-04-09 2020-08-25 中国科学院微电子研究所 刻蚀沟槽的方法

Family Cites Families (26)

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GB1147014A (en) * 1967-01-27 1969-04-02 Westinghouse Electric Corp Improvements in diffusion masking
DE2557079C2 (de) * 1975-12-18 1984-05-24 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren zum Herstellen einer Maskierungsschicht
JPS5351970A (en) * 1976-10-21 1978-05-11 Toshiba Corp Manufacture for semiconductor substrate
US4211601A (en) * 1978-07-31 1980-07-08 Bell Telephone Laboratories, Incorporated Device fabrication by plasma etching
US4283249A (en) * 1979-05-02 1981-08-11 International Business Machines Corporation Reactive ion etching
US5362682A (en) * 1980-04-10 1994-11-08 Massachusetts Institute Of Technology Method of producing sheets of crystalline material and devices made therefrom
NL8301262A (nl) * 1983-04-11 1984-11-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij met behulp van ionenimplantatie patronen worden aangebracht in een laag siliciumnitride.
JPS62224687A (ja) * 1986-03-25 1987-10-02 Anelva Corp エツチング方法
US5091047A (en) * 1986-09-11 1992-02-25 National Semiconductor Corp. Plasma etching using a bilayer mask
FR2610140B1 (fr) * 1987-01-26 1990-04-20 Commissariat Energie Atomique Circuit integre cmos et procede de fabrication de ses zones d'isolation electrique
US4782009A (en) * 1987-04-03 1988-11-01 General Electric Company Method of coating and imaging photopatternable silicone polyamic acid
FR2652448B1 (fr) * 1989-09-28 1994-04-29 Commissariat Energie Atomique Procede de fabrication d'un circuit integre mis haute tension.
JP3006048B2 (ja) * 1990-07-27 2000-02-07 ソニー株式会社 ドライエッチング方法
KR960000375B1 (ko) * 1991-01-22 1996-01-05 가부시끼가이샤 도시바 반도체장치의 제조방법
US5217568A (en) * 1992-02-03 1993-06-08 Motorola, Inc. Silicon etching process using polymeric mask, for example, to form V-groove for an optical fiber coupling
JP3111661B2 (ja) * 1992-07-24 2000-11-27 ソニー株式会社 ドライエッチング方法
US5350484A (en) * 1992-09-08 1994-09-27 Intel Corporation Method for the anisotropic etching of metal films in the fabrication of interconnects
US5525535A (en) * 1995-07-26 1996-06-11 United Microelectronics Corporation Method for making doped well and field regions on semiconductor substrates for field effect transistors using liquid phase deposition of oxides
JPH1160735A (ja) * 1996-12-09 1999-03-05 Toshiba Corp ポリシランおよびパターン形成方法
TWI246633B (en) * 1997-12-12 2006-01-01 Applied Materials Inc Method of pattern etching a low k dielectric layen
US6025273A (en) * 1998-04-06 2000-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for etching reliable small contact holes with improved profiles for semiconductor integrated circuits using a carbon doped hard mask
US6387819B1 (en) * 1998-04-29 2002-05-14 Applied Materials, Inc. Method for etching low K dielectric layers
JP2001210726A (ja) * 2000-01-24 2001-08-03 Hitachi Ltd 半導体装置及びその製造方法
US6527968B1 (en) * 2000-03-27 2003-03-04 Applied Materials Inc. Two-stage self-cleaning silicon etch process
KR20030007904A (ko) * 2000-06-06 2003-01-23 이케이씨 테크놀로지, 인코포레이티드 전자 재료 제조 방법
US6583046B1 (en) * 2001-07-13 2003-06-24 Advanced Micro Devices, Inc. Post-treatment of low-k dielectric for prevention of photoresist poisoning

Also Published As

Publication number Publication date
EP1360711A1 (de) 2003-11-12
WO2002059951A1 (de) 2002-08-01
DE50209714D1 (de) 2007-04-26
US20030207588A1 (en) 2003-11-06
JP2004517505A (ja) 2004-06-10
KR20030074745A (ko) 2003-09-19
US6864188B2 (en) 2005-03-08
TW548743B (en) 2003-08-21
DE10103524A1 (de) 2002-08-22
EP1360711B1 (de) 2007-03-14

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