WO2001095075A1 - Circuit integre a semi-conducteur et circuit de distribution du signal d'horloge - Google Patents

Circuit integre a semi-conducteur et circuit de distribution du signal d'horloge Download PDF

Info

Publication number
WO2001095075A1
WO2001095075A1 PCT/JP2000/003578 JP0003578W WO0195075A1 WO 2001095075 A1 WO2001095075 A1 WO 2001095075A1 JP 0003578 W JP0003578 W JP 0003578W WO 0195075 A1 WO0195075 A1 WO 0195075A1
Authority
WO
WIPO (PCT)
Prior art keywords
clock
cmos
buffer
signal
clock buffer
Prior art date
Application number
PCT/JP2000/003578
Other languages
English (en)
Japanese (ja)
Inventor
Tetsuya Maruyama
Original Assignee
Hitachi,Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi,Ltd filed Critical Hitachi,Ltd
Priority to PCT/JP2000/003578 priority Critical patent/WO2001095075A1/fr
Publication of WO2001095075A1 publication Critical patent/WO2001095075A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Definitions

  • the present invention relates to a semiconductor integrated circuit operated in synchronization with a clock signal, and more particularly to a semiconductor integrated circuit, and more particularly to a technology effective when applied to a complementary field effect transistor (hereinafter simply referred to as CMOS) type semiconductor integrated circuit. It is about. Background art
  • dynamic skew is the phase shift of the click signal and distortion of the signal waveform caused by AC noise transmitted on the power supply line of the clock transmission system clock amplifier and crosstalk noise to the clock transmission system. Occurs locally. At this time, most of the logic paths (signal paths of a plurality of sequential circuits in which a combinational circuit is interposed) in the semiconductor integrated circuit are input to the starting flip-flop (sequential circuit) and the ending flip-flop.
  • the transmission system of the mouth signal differs only at a very small part of the end portion of the mouth signal transmission system.
  • the length of the different path at the end of such a clock transmission system is extremely short because of the end of the transmission system, and the difference in signal delay at only that portion is unlikely to cause clock skew. Therefore, the starting flip-flop It is considered that the skew between the clock signals input to the flip-flop and the end-point flip-flop is mainly the dynamic skew component generated instantaneously in the same clock transmission system.
  • the timing interval between the clock input to the start flip-flop and the clock input to the end flip-flop in the next cycle is affected by the dynamic skew. From the timing interval of the clock cycle given upstream of the clock.
  • the present inventors have studied transmission of clock signals complementarily to reduce skew between clock signals.
  • the adoption of a complementary clock signal in a clock transmission system is described in Japanese Patent Application Laid-Open No. 5-233930, Japanese Patent Application Laid-Open No. 91-231196, Japanese Patent Application Laid-Open No. 91-44426. No. 7 and JP-A-8-307460. According to them, it is shown that even if in-phase noise is present in the complementary clock signal, it is canceled by differential amplification.
  • An object of the present invention is to reduce the occurrence of skew due to a dynamic skew component between clock signals input to flip-flops from the start point to the end point of a logical path, and to provide a physical circuit by that.
  • An object of the present invention is to provide a clock distribution circuit capable of suppressing an increase in scale and heat generation, and a semiconductor integrated circuit.
  • a semiconductor integrated circuit includes a logic circuit and a clock supply circuit.
  • the clock supply circuit s input and output complementary clock signals, respectively.
  • a plurality of first clock buffers having two or more stages connected in series, and a second clock buffer that receives a complementary clock signal output from the final stage first clock buffer and outputs a single-phase clock signal
  • a third clock buffer having two or more serially connected stages for transmitting the single-phase clock signal from the second clock buffer.
  • the logic circuit operates by inputting a clock signal formed based on a clock signal output from the third clock buffer at the last stage.
  • the in-phase noise component is canceled when the first noise is received and amplified differentially by the first clock buffer or the second clock buffer.
  • the complementary clock signal transmission line for canceling this common-mode noise component has a series of three stages including two or more stages of the first clock buffer and the second clock buffer, two or more stages before and after, as a clock buffer for transmitting the clock signal complementarily. These are arranged. Therefore, the common-mode noise component can be canceled to a further downstream side of the clock transmission system as compared with a configuration in which the clock signal is transmitted complementarily only between the two clock buffers in the front and rear stages. Therefore, it is possible to reduce the occurrence of skew due to the dynamic skew component between the clock signals input to the flip-flops from the start point to the end point of the logical path.
  • the distortion of the clock waveform and phase due to noise has a large absolute value of the delay time (the wiring length per stage is long and the absolute value of the delay time is large;
  • the relationship between the number of stages of the second clock buffer and the number of stages of the third clock buffer is based on the trade-off between malfunction prevention due to dynamics skew and the increased circuit size and heat generation.
  • One solution can be given to the dooff.
  • the first clock buffer may be a differential clock amplifier having a differential input transistor receiving a complementary signal at a control terminal. Differential reception of differential signals ensures cancellation of common-mode noise components. If priority is placed on low power consumption, a circuit that receives and outputs each of the complementary cook signals over the CM ⁇ S member may be used. In this case, a circuit that differentially receives the complementary clock signal and performs an amplifying operation may be employed for the first clock buffer or the second clock buffer at the last stage.
  • the third clock buffer may be a CMOS transistor. This contributes to low power consumption.
  • the output amplitude of the first clock buffer may be smaller than the output signal amplitudes of the second and third clock buffers.
  • the second clock buffer may be a level conversion circuit that expands an input complementary signal by a plurality of stages of differential amplification.
  • the clock supply circuit includes a plurality of first clock buffers each of which inputs and outputs a complementary clock signal, has a number of three or more stages connected in series, and has an output of each stage connected to a branch path of approximately equal length.
  • a second clock buffer that inputs a complementary clock signal output from the first clock buffer of the stage and outputs a single-phase clock signal, and two or more stages that transmit the single-phase clock signal from the second clock buffer
  • a plurality of third clock buffers each having the number of serially connected stages and having the output of each stage connected to a branch path having substantially the same length.
  • the logic circuit inputs a clock signal formed based on the clock signal output by the third clock buffer at the final stage. Is done.
  • the first clock buffer, the second clock buffer, the third clock buffer, and the branch path may adopt an H-shaped two-branch tree structure.
  • the prevention of malfunction due to the dynamic skew is not based on the assumption that an equal-length wiring or an equal-delay wiring, such as a H-peri-branch structure, is used in the clock transmission system. .
  • the semiconductor integrated circuit may include a PLL circuit that supplies a complementary clock signal to the first-stage first clock buffer.
  • the output amplitude of the first clock buffer may be smaller than the output signal amplitudes of the second and third clock buffers.
  • the first clock buffer may be a differential clock amplifier having a differential input transistor receiving a complementary signal at a control terminal.
  • the second clock buffer may be a level conversion circuit for expanding an input complementary signal by a plurality of stages of differential amplification.
  • the third clock buffer may employ a CM ⁇ S inverter.
  • the present invention can be understood from the viewpoint of a clock distribution circuit.
  • the mouthpiece distribution circuit includes a mouthpiece generation circuit that generates a complementary mouthpiece signal, and three or more serially connected stages that transmit the complementary mouthpiece signal from the mouthpiece generation circuit.
  • a plurality of first clock buffers each having an output of each stage connected to a branch path having substantially the same length, and a single-phase clock signal receiving a complementary clock signal output from the first clock buffer at the last stage.
  • a second clock buffer for outputting a single-phase clock signal from the second clock buffer.
  • the output of each stage is connected to a substantially equal-length branch path. that a plurality of the third clock buffer and, c said first clock buffer containing, second clock buffer, a third clock Kubaffa and branch path has two branches Dzuri structure shaped in H.
  • FIG. 1 is an explanatory diagram mainly showing a clock transmission system of an example of a semiconductor integrated circuit according to the present invention.
  • FIG. 2 is an explanatory diagram exemplifying one serial path from the branch path L3 to the terminal flip-flop in the semiconductor integrated circuit of FIG. 1 in three modes (A) to (C). .
  • FIG. 3 is a logic circuit diagram exemplifying the entire configuration of FIG. 2A with a tree structure.
  • FIG. 4 is a circuit diagram showing a differential clock amplifier which is an example of a first clock buffer.
  • FIG. 5 is a circuit diagram showing a case where the output resistance of the differential clock amplifier is constituted by a MOS resistor.
  • FIG. 6 is a logic circuit diagram of a CM0S type differential clock amplifier in which the configuration of the first clock buffer is simplified.
  • FIG. 7 shows a level conversion circuit which is an example of the second clock buffer.
  • FIG. 8 is a circuit diagram showing a CMOS transistor as an example of a third clock buffer.
  • FIG. 9 is a circuit diagram showing an example of a flip-flop.
  • FIG. 10 is a signal waveform diagram for explaining the canceling action of the in-phase noise component.
  • FIG. 11 is an explanatory diagram of the operation of the transmission system in the semiconductor integrated circuit of FIG.
  • FIG. 12 is an explanatory diagram showing, as a comparative example, a semiconductor integrated circuit in which the entire clock transmission system is constituted by a single-phase clock system.
  • FIG. 1 shows an example of a semiconductor integrated circuit according to the present invention, focusing on a clock transmission system.
  • the semiconductor integrated circuit 1 is formed on a single semiconductor substrate such as, for example, single-crystal silicon by a known CMOS integrated circuit manufacturing technique.
  • a semiconductor integrated circuit has a logic circuit and a clock supply circuit.
  • the logic circuit has a number of signal paths of a plurality of sequential circuits in which a combinational circuit is interposed, and these are connected as desired to realize an intended logic function (for example, a semiconductor integrated circuit is a central circuit).
  • a processing device for example, one signal path is a signal path from an input latch circuit to an output latch circuit via arithmetic logic, a temporary latch, etc.
  • a clock supply circuit is connected to these sequential circuits. Provides a clock signal.
  • the branch supply circuits respectively input and output the complementary block signals, and have three or more stages connected in series, and the output of each stage is a branch path L 1, L 2, L 3, a plurality of first clock buffers 4 connected to L4 and a complementary clock signal output from the first-stage first clock buffer 4. And a second clock buffer 6 for outputting a single-phase clock signal to output a single-phase clock signal, and two or more serially-connected stages for transmitting the single-phase clock signal from the second clock buffer 6.
  • a plurality of third clock buffers 9 connected to branch paths L 5 and L 6 of substantially equal length. The logic circuit receives a clock signal formed based on the clock signal output from the third clock buffer 9 at the last stage.
  • a complementary clock signal is supplied from the PLL circuit 3 to the first clock buffer 4 in the first stage.
  • the first clock buffer 4, the second clock buffer 6, the third clock buffer 9, and the branch paths L1 to L6 have an H-shaped two-branch tree structure. .
  • FIG. 1 only a part of the branch paths L5 and L6 is illustrated, and the circuit configuration at the subsequent stage of the clock buffer 9 at the final stage is omitted.
  • FIG. 2 illustrates one serial path from the branch path L3 to the terminal flip-flop in the semiconductor integrated circuit of FIG.
  • FIG. 2 (A) a CMOS circuit 10 typically shown is connected after the clock buffer 9 at the last stage, and the output of the CM 0 S circuit 10 is connected to the flip-flop 1. Connected to 1 clock input terminal C.
  • the flip-flop 11 makes the data input terminal D through the data output terminal Q by the high level of the clock terminal C, and latches the input data of the data input terminal D by the single level of the clock terminal C.
  • FIG. 3 shows an example of the configuration of FIG. 2 (A) as a whole with a tree structure. In FIG. 3, a path shown by a broken line is a part of a data path typically shown, and flip-flops 11 are arranged before and after the combinational circuit 11A.
  • the clock buffer 12 typically shown is connected after the clock buffer 9 in the last stage, and the clock buffer 12 is The complementary output is coupled to the non-inverting clock input terminal C of flip-flop 13 and the inverting clock terminal Cb.
  • the flip-flop 13 sets the data output terminal Q from the data input terminal D to the through through the data input terminal Q through the high level of the terminal block C and the terminal level of the terminal Cb, The input data of the input terminal D is latched by the high level of the terminal Cb.
  • the example of (C) in FIG. 2 is a logic gate circuit which is coupled to the CMO S / N 14 which is typically shown after the last clock buffer 9 and receives the output of the C / S N / S 14 15 generates non-overlapping two-phase clock signals CKt and CKb.
  • the clock signal CKt is supplied to the clock terminal C of the master latch circuit 16A
  • the clock signal CKb is supplied to the clock terminal C of the slave latch circuit 16A
  • the pair of latch circuits 16A and 16B are connected to the master terminal.
  • FIG. 4 shows a differential clock amplifier which is an example of the first clock buffer 4.
  • the first clock buffer (differential clock amplifier) is an n-channel type current source MOS transistor 17, a pair of n-channel type differential input MOS transistors (current switch MOS transistor) 18, 19, composed of output resistors 20 and 21.
  • the gate electrodes of the differential input MOS transistors 18 and 19 are used as differential input terminals IP and IN.
  • Differential input M ⁇ S Transistors Drain electrodes 18 and 19 are set to differential output terminals ON and OP.
  • VSS is the ground voltage of the circuit and is set to 0 V.
  • VDD is a power supply voltage and takes a predetermined voltage selected from, for example, 1 V to 5 V.
  • VCS is a control voltage that is set to VSS during standby and VDD when standby is released.
  • the differential clock amplifier 4 outputs a complementary signal according to the voltage difference between the input terminals IP and IN.
  • the complementary signal input to IP and I0 has a signal amplitude of It has a relatively small signal amplitude in the range of ⁇ 01) / 2 to ⁇ 00, and is changed near the power supply voltage $ DD.
  • the output resistors 20 and 21 are desirably simple resistance elements such as diffusion resistors in view of speed performance, but if a MOS resistor is used for process simplification, it is exemplified in FIG. in so that the circuit connected in parallel to the n-channel type MO S transistor 22 and the p-channel type MO S transistor 23, each of the output resistor 20, 2 resistance value control may c VRR to be adopted in place of each Voltage.
  • a part or all of the first clock buffer 4 may be replaced with a CMOS differential clock pump shown in FIG.
  • the configuration in FIG. 6 is a configuration in which the input terminals IP and IN are received by the individual CMO Simbus 24, 25, respectively, and the inverted output is output from the output terminals 0 N and OP.
  • the complementary signal is not completely differentially received, so there is no effect of canceling the common-mode noise component itself, and the clock buffer 4 shown in FIG. 4 and the clock buffer 6 shown in FIG. Since the common-mode noise component is canceled, the effect of reducing clock skew is inferior to that of Fig. 4, but the circuit area and power consumption can be significantly reduced.
  • FIG. 7 shows a level conversion circuit which is an example of the second clock buffer 6.
  • the second clock buffer (level conversion circuit) 6 expands the level of the complementary signal input to the terminals IP and IN by a plurality of stages of differential amplification. That is, the level conversion circuit 6 includes n-channel current source MOS transistors 30 to 3, a pair of n-channel differential input MOS transistors 33 and 34, and a pair of p-channel current mirror load MOS transistors. 35, 36, a first differential amplifier AMP1, a pair of n-channel type differential input MOS transistors 37, 38 and a pair of p-channel transistors.
  • a second differential amplifier AMP2 comprising a MOS transistor 39, 40 and a pair of n-channel differential input MOS transistors 41, 42 and a pair of p-channel power mirrors. It comprises a third differential amplifier AMP3 comprising load MOS transistors 43 and 44, and a CMOS output transistor comprising an n-channel MOS transistor 45 and a p-channel MOS transistor 46.
  • Input terminals IP The input polarities of the differential amplifiers AMP 1 and AMP 2 coupled to IN are reversed, and the potential difference of the complementary input clock signal is differentially amplified, and the differentially amplified single-ended output is output. Is input to the third differential amplifier AMP3, is further differentially amplified, and the signal amplitude is sequentially enlarged.
  • the single-ended output of the differential amplifier AMP3 is amplified by the CMOS output combiner, and a CM ⁇ S level clock signal whose output amplitude is from the ground voltage VSS to the power supply voltage VDD is output to the output terminal OUT. Is done.
  • the third clock buffer 9 is composed of a CM ⁇ S inverter as illustrated in FIG.
  • the output amplitude of the differential clock amplifier 4 is larger than the output signal amplitude of the level conversion circuit 6 and the third clock buffer 9. Has also been reduced.
  • FIG. 9 shows an example of the flip-flop 11.
  • a CMOS transistor 50 Between the input terminal D and the output terminal Q, a CMOS transistor 50, a CMOS transfer gate 51 and a CMOS transistor 52 are arranged in series to form a single path.
  • a latch path for feedback connection via the CMOS transistors 53 and 54 and the CMOS transfer gate 55 is formed.
  • the CMOS transfer gates 51 and 55 are connected to a clock signal CKP supplied from a clock terminal C. It is exclusively turned on by the inverted clock signal CKN by the CMOS circuit 56.
  • the operation of the transmission system in the semiconductor integrated circuit 1 described above will be described.
  • the AC noise crosstalk noise on the complementary clock signal forms in-phase noise on the complementary clock signal.
  • the in-phase noise component is canceled.
  • the signal waveforms indicated by 60 and 61 are the non-inverted signal waveform (P-pole signal waveform) and the inverted signal waveform (N-pole signal waveform) of the complementary clock signal in a state where no noise is present. Show. When there is no noise, the cross point of the complementary clock signal waveforms 60 and 61 is the point of 63.
  • the single-phase clock signal waveform corresponding to the complementary clock signal is represented by waveform 61 when no noise is applied.
  • the level indicated by 62 is a logical threshold voltage when a clock buffer such as a CMOS circuit receiving a single-phase clock signal is not receiving power supply noise.
  • this clock buffer receives power supply noise changes to the level of 62 S.
  • a clock buffer such as a CMOS circuit receiving this waveform detects the input change at a point 63S. .
  • the switching point of the signal waveform shifts from 63 to 63S.
  • common-mode noise is added to the complementary waveform, so if the waveform 61 changes to 61S, the waveform 60 also shifts to the high level side and changes to the waveform 60S.
  • the cross point between the complementary signal waveform 61S and the waveform 60S does not substantially deviate from 63.
  • the noise received is mainly in-phase noise. If the noise is in-phase, the switching point remains at 63 and no timing difference occurs.
  • FIG. 11 corresponds to the semiconductor integrated circuit of FIG.
  • Flip-flops: FFa ,: FFb are the start flip-flop and the end flip-flop in a specific data path included in the logic circuit, and the combinational circuit (flip-flop) located in the middle is The illustration is omitted.
  • Flip-flops FFc and FFd are a start-point flip-flop and an end-point flip-flop in a specific data path included in the logic circuit, and the combinational circuit flip-flop arranged in the middle thereof is not shown. is there.
  • the next stage of the clock buffer 4 receives the differential signal and cancels the noise. Even if power supply noise or crosstalk noise is present on one of the paths L4 and L4, which are separate clock transmission systems, for the flip-flops FFa and FFb, the next-stage clock buffer 6 receives the noise differentially. To cancel the noise. Therefore, it is possible to prevent the operation timing of the start flip-flop FFa and the end flip-flop FFb of the same data system from being undesirably shifted due to the dynamic skew.
  • the only link transmission system common to the flip-flops FFc and Fd is the path L1, and the power supply is provided in that portion. Even if noise or crosstalk noise is included in the clock signal, the clock buffer 4 at the next stage receives the differential signal and can cancel the noise. Regarding the paths L2, L3, L4, which are individual clock transmission systems for the flip-flop FFc, and the paths L2, L3, L4, which are individual clock transmission systems for the flip-flop FFd, Even if there is power supply noise or crosstalk noise, it can be differentially received by the next-stage clock buffers 4 and 6 to cancel the noise.
  • the complementary clock signal transmission path for canceling the in-phase noise component is provided with two or more first clock buffers before and after the clock buffer for complementarily transmitting the clock signal.
  • a total of three or more stages are arranged together with the buffer 4 and the second clock buffer 6. Therefore, in-phase noise components can be canceled further downstream of the clock transmission system as compared with a configuration in which the clock signal is transmitted complementarily only between the two stages of the upstream and downstream ports. Therefore, it is possible to reduce the occurrence of skew due to a dynamic skew component between clock signals input to the flip-flops from the start point to the end point of the logical path.
  • At least two serial third-stage clock buffers 9 for transmitting a single-phase clock are left in the clock path from the second clock buffer 6 to the terminal flip-flop, so that the terminals are complementary to the terminal.
  • a configuration that supplies a clock signal it is possible to suppress an increase in the chip occupation area due to the clock transmission system, and it is also possible to reduce local heat generation.
  • the distortion of the clock waveform and phase due to noise causes the wiring length to be longer, the delay time and the rise and fall times to be greater on the upstream side, and the influence on the terminal portion to be greater.
  • the number of mouth buffers becomes much larger on the downstream side where the number of layers of the transmission line branches increases.
  • the effect of the upstream part is large because the wiring length per stage is long, and the waveform becomes dull (the rise and fall times become large). Even if the same voltage fluctuation (due to power supply fluctuation or crosstalk, etc.), the time fluctuation is affected. It is because it becomes large.
  • the relationship between the number of stages of the first and second clock buffers 4 and 6 and the number of stages of the third clock buffer 9 described above is to prevent malfunction due to dynamic skew and increase the circuit scale and heat generation due to this. It offers a solution to the trade-off between quantity and quantity.
  • the first clock buffer 4 is a differential clock amplifier having a differential input transistor that receives a complementary signal at a control terminal, the cancellation of the common-mode noise component is ensured by receiving the differential signal differentially.
  • the output amplitude of the first clock buffer 4 is smaller than the output signal amplitudes of the second and third clock buffers 6 and 9.
  • the clock transmission system is not limited to the H-tree structure, and the wiring route may be random in consideration of equal delay or equal length, or the present invention can be applied without considering equal delay or equal length. No problem.
  • the number of serial stages of the first clock buffer, the second clock buffer, and the third clock buffer is not limited to the configuration shown in FIG. 1 and can be appropriately changed as long as necessary conditions are satisfied. Industrial applicability
  • the present invention relates to a semiconductor integrated circuit that operates in synchronization with a clock signal, such as a logic LSI such as a microcomputer or a data processor, a memory LSI such as a synchronous DRAM, and a system LSI in which a DRAM is embedded together with a CPU. Can be widely applied.
  • a logic LSI such as a microcomputer or a data processor
  • a memory LSI such as a synchronous DRAM
  • system LSI in which a DRAM is embedded together with a CPU.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

L'invention concerne un système de transmission de signal d'horloge, qui contient une première série de plusieurs tampons d'horloge (4) dont deux ou plusieurs sont connectés en série et reçoivent/produisent des signaux d'horloge complémentaires; une deuxième série de tampons d'horloge (6), chaque signal d'horloge complémentaire étant émis par le dernier tampon d'horloge de la première série et produisant un signal d'horloge monophasé; et une troisième série de tampons d'horloge (9), dont deux ou plusieurs sont connectés en série et transmettent le signal d'horloge monophasé. Etant donné que le bruit C.A. acheminé dans le signal d'horloge complémentaire est un bruit en phase, il est supprimé par l'amplification différentielle par un tampon d'horloge complémentaire constitué de trois ou plusieurs tampons, les tampons d'horloge de la première série et les tampons d'horloge de la deuxième série étant arrangés dans les parcours de transmission du signal d'horloge complémentaire. La relation entre le nombre de tampons d'horloge de la première et de la deuxième série et celui de la troisième série règle le compromis entre, d'une part la prévention d'un fonctionnement défectueux dû à un écart dynamique et à l'augmentation de la taille du circuit, et d'autre part la chaleur dégagée résultant de cette prévention.
PCT/JP2000/003578 2000-06-02 2000-06-02 Circuit integre a semi-conducteur et circuit de distribution du signal d'horloge WO2001095075A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2000/003578 WO2001095075A1 (fr) 2000-06-02 2000-06-02 Circuit integre a semi-conducteur et circuit de distribution du signal d'horloge

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2000/003578 WO2001095075A1 (fr) 2000-06-02 2000-06-02 Circuit integre a semi-conducteur et circuit de distribution du signal d'horloge

Publications (1)

Publication Number Publication Date
WO2001095075A1 true WO2001095075A1 (fr) 2001-12-13

Family

ID=11736104

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/003578 WO2001095075A1 (fr) 2000-06-02 2000-06-02 Circuit integre a semi-conducteur et circuit de distribution du signal d'horloge

Country Status (1)

Country Link
WO (1) WO2001095075A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003104826A1 (fr) * 2002-06-10 2003-12-18 株式会社アドバンテスト Appareil de test à semi-conducteur
JP2009043331A (ja) * 2007-08-08 2009-02-26 Rohm Co Ltd シフトレジスタ
US11469758B2 (en) 2018-11-26 2022-10-11 Denso Corporation High frequency switch

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0396009A (ja) * 1989-09-07 1991-04-22 Nec Corp クロック信号分配回路
JPH03177913A (ja) * 1989-12-07 1991-08-01 Hitachi Ltd クロック供給回路
JPH05233092A (ja) * 1992-02-18 1993-09-10 Nec Ic Microcomput Syst Ltd クロック信号分配方法および分配回路
JPH05233093A (ja) * 1992-02-21 1993-09-10 Nec Corp クロック信号供給回路および供給方法
JPH05326866A (ja) * 1992-05-18 1993-12-10 Mitsubishi Electric Corp クロック供給回路
JPH06274242A (ja) * 1993-03-23 1994-09-30 Hitachi Ltd 半導体集積回路装置
JPH0798616A (ja) * 1993-09-24 1995-04-11 Nec Corp クロック信号分配回路
JPH08307460A (ja) * 1995-05-10 1996-11-22 Yamaha Corp デジタル信号伝送路
JPH09231196A (ja) * 1996-02-28 1997-09-05 Sharp Corp クロック分配回路
US5732249A (en) * 1995-07-26 1998-03-24 Mitsubishi Electric Engineering Co., Ltd. Clock distributing circuit

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0396009A (ja) * 1989-09-07 1991-04-22 Nec Corp クロック信号分配回路
JPH03177913A (ja) * 1989-12-07 1991-08-01 Hitachi Ltd クロック供給回路
JPH05233092A (ja) * 1992-02-18 1993-09-10 Nec Ic Microcomput Syst Ltd クロック信号分配方法および分配回路
JPH05233093A (ja) * 1992-02-21 1993-09-10 Nec Corp クロック信号供給回路および供給方法
JPH05326866A (ja) * 1992-05-18 1993-12-10 Mitsubishi Electric Corp クロック供給回路
JPH06274242A (ja) * 1993-03-23 1994-09-30 Hitachi Ltd 半導体集積回路装置
JPH0798616A (ja) * 1993-09-24 1995-04-11 Nec Corp クロック信号分配回路
JPH08307460A (ja) * 1995-05-10 1996-11-22 Yamaha Corp デジタル信号伝送路
US5732249A (en) * 1995-07-26 1998-03-24 Mitsubishi Electric Engineering Co., Ltd. Clock distributing circuit
JPH09231196A (ja) * 1996-02-28 1997-09-05 Sharp Corp クロック分配回路

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003104826A1 (fr) * 2002-06-10 2003-12-18 株式会社アドバンテスト Appareil de test à semi-conducteur
US7126366B2 (en) 2002-06-10 2006-10-24 Advantest Corp. Semiconductor test apparatus
US7332926B2 (en) 2002-06-10 2008-02-19 Advantest Corp. Semiconductor test apparatus
JP2009043331A (ja) * 2007-08-08 2009-02-26 Rohm Co Ltd シフトレジスタ
US11469758B2 (en) 2018-11-26 2022-10-11 Denso Corporation High frequency switch

Similar Documents

Publication Publication Date Title
US7768330B2 (en) Logic circuit
US8166286B2 (en) Data pipeline with large tuning range of clock signals
JP2003078407A (ja) 高速サンプリングレシーバー
JP2001228931A (ja) クロックドライバ回路およびクロック配線方法
JP3987262B2 (ja) レベルコンバータ回路
US6967505B2 (en) Input circuit
JP2004064557A (ja) フリップフロップ回路およびシフトレジスタ
US7251740B2 (en) Apparatus coupling two circuits having different supply voltage sources
US6448818B1 (en) Apparatus, method and system for a ratioed NOR logic arrangement
US6323698B1 (en) Apparatus, method and system for providing LVS enables together with LVS data
WO2001095075A1 (fr) Circuit integre a semi-conducteur et circuit de distribution du signal d'horloge
JP2004078804A (ja) クロック信号伝搬ゲート及びそれを含む半導体集積回路
US6078196A (en) Data enabled logic circuits
US6784694B2 (en) CMOS sequential logic configuration for an edge triggered flip-flop
JPH11340794A (ja) マスタースレーブ型フリップフロップ回路
JP2003046376A (ja) フリップフロップ回路
JP4746976B2 (ja) センスアンプ回路
JP4077123B2 (ja) 差動信号出力回路
JP5139132B2 (ja) 半導体集積回路
JP3683695B2 (ja) ラッチ回路およびｄｆｆ回路
US6853229B2 (en) Circuit for transforming a single ended signal into a differential mode signal
JPH11126473A (ja) 半導体集積回路
JP3209399B2 (ja) ゲートアレイ集積回路
JPH08181574A (ja) フリップフロップ回路
KR100280424B1 (ko) 플립플롭

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR SG US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
ENP Entry into the national phase

Ref country code: JP

Ref document number: 2002 502562

Kind code of ref document: A

Format of ref document f/p: F

122 Ep: pct application non-entry in european phase