WO2001029885A2 - Verfahren zur herstellung einer kondensator-elektrode mit barrierestruktur - Google Patents
Verfahren zur herstellung einer kondensator-elektrode mit barrierestruktur Download PDFInfo
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- WO2001029885A2 WO2001029885A2 PCT/DE2000/003662 DE0003662W WO0129885A2 WO 2001029885 A2 WO2001029885 A2 WO 2001029885A2 DE 0003662 W DE0003662 W DE 0003662W WO 0129885 A2 WO0129885 A2 WO 0129885A2
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- Prior art keywords
- layer
- barrier
- electrode
- capacitor electrode
- deposited
- Prior art date
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- 230000004888 barrier function Effects 0.000 title claims abstract description 108
- 239000003990 capacitor Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 40
- 239000010410 layer Substances 0.000 claims description 133
- 239000007772 electrode material Substances 0.000 claims description 23
- 239000011229 interlayer Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 230000000873 masking effect Effects 0.000 claims description 5
- 238000005498 polishing Methods 0.000 abstract description 4
- 239000000126 substance Substances 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 description 10
- 230000008021 deposition Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 229910052741 iridium Inorganic materials 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000010348 incorporation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- 229910052702 rhenium Inorganic materials 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 206010010144 Completed suicide Diseases 0.000 description 1
- 241000158147 Sator Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- JFWLFXVBLPDVDZ-UHFFFAOYSA-N [Ru]=O.[Sr] Chemical compound [Ru]=O.[Sr] JFWLFXVBLPDVDZ-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000001143 conditioned effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Definitions
- the invention relates to a method for producing a capacitor electrode with an underlying barrier structure in an integrated semiconductor circuit.
- novel capacitor materials usually have to be produced at relatively high process temperatures and using an oxygen-containing process gas. If an oxidizable electrode (for example made of polysilicon or tungsten) were used, this would lead to oxidation of the electrode and a resulting reduction in the capacitance of the capacitor. Novel, inert electrode materials, e.g. Pt, Ir, Ru, can be used.
- One problem with the use of such electrode materials is that the oxygen diffuses through the chemically stable electrode and then builds up a high-resistance barrier oxide layer on the silicon substrate. To prevent this, a barrier is used, which is arranged between the electrode and the substrate.
- the manufacture of the barrier and the lower electrode (bottom electrode) of the condenser arranged above it sators usually takes place through multiple execution of suitable photolithography and etching processes.
- U.S. Patent 5,366,920 describes a process for producing a thin-film capacitor.
- the barrier and the lower electrode are not produced by a photolithography and etching process, but an insulation layer is deposited on the substrate, in which an opening is made.
- the opening is then filled by depositing a barrier layer, an electrode layer, and further layers. In this way, the capacitor is built up layer by layer in the opening of the insulation layer.
- the invention is based on the object of specifying a method for producing a capacitor electrode with a barrier structure arranged underneath which can be carried out simply and reliably.
- An essential aspect of the invention is that a CMP (chemical mechanical polishing) planarization step is used to produce the barrier structure.
- the CMP is an easily executable process step.
- the CMP process is used to generate a planarized surface of the barrier interlayer and the barrier structure embedded therein.
- the planarized surface is then used as a base for the capacitor electrode to be built up subsequently.
- An electrode interlayer is preferably placed over the planarized bar to form the capacitor electrode.
- Barrier structure-inlay layer is deposited and an electrode structuring hole exposing the barrier structure in the electrode-inlay layer is produced by a lithographic masking and etching step. Then a layer of electrode material filling the electrode structuring hole is deposited in and around the electrode structuring hole, and finally the capacitor electrode is formed out of the electrode material layer by CMP.
- CMP planarization steps can therefore be used both for producing the “buried” barrier structure and for producing the (lower) capacitor electrode.
- a layer deposition step and a lithographic mask and etching step are used to form the capacitor electrode in a manner known per se.
- a barrier structuring hole is created in a barrier incorporation layer, a barrier layer is deposited in and around the barrier structuring hole and a barrier structure is formed out of the barrier layer by means of CMP planarization.
- the CMP planarization step is used directly for the (lateral) structuring of the barrier layer.
- the barrier layer can be deposited in such a way that the barrier structuring hole is completely filled.
- the barrier structure incorporation layer with an embedded barrier structure is then given a flat surface, which in the manner already described can serve as a base for the subsequent construction of the capacitor electrode.
- the barrier layer is deposited in such a way that the bottom and wall of the hole are lined while maintaining a depression.
- a layer of electrode material is deposited over the barrier layer.
- the capacitor electrode is simultaneously formed from the overlying electrode material layer.
- FIG. 1 shows the structure of a DRAM memory cell with switching transistor and high- ⁇ or ferroelectric stack capacitor in a schematic manner
- 2A-D are schematic sectional views for explaining the production of a buried barrier structure according to a first exemplary embodiment of the invention
- 3A-B are schematic sectional views for explaining a first possibility of producing a capacitor electrode over the barrier structure
- 4A-D are schematic sectional views for explaining a second possibility of producing a capacitor electrode over the barrier structure
- 5A-E are schematic sectional views for explaining the production of a buried barrier structure according to a second exemplary embodiment of the invention.
- 6A-E are schematic sectional illustrations for explaining the production of a buried barrier structure with a capacitor electrode arranged above it, according to a third exemplary embodiment of the FIG.
- n + -doped drain region 2 is separated from an n + -doped source region 3 via an intermediate channel 4 made of substrate material.
- a thin gate oxide layer 5 lies above the channel 4.
- a gate electrode 6 is attached to the gate oxide layer 5.
- a cover oxide layer 7 is deposited, which comprises a contact hole 8.
- the contact hole 8 is filled with an electrical connection structure 9 (so-called “plug”) consisting of polysilicon.
- a capacitor 10 is implemented above the cover oxide layer 7.
- the capacitor has a lower electrode 11 (so-called “bottom electrode”), an upper electrode 12 and, in between, a high- ⁇ dielectric / ferroelectric 13.
- the high ⁇ dielectric / ferroelectric 13 can be made, for example, from Pb (Zr, Ti) 0 3 [PZT], SrBi 2 Ta 2 0 9 [SBT], SrTi0 3 [ST] and / or (Ba, Sr) Ti0 3 [ BST] or other new perovskite materials. It is usually deposited using a MOD (metal organic deposition), a MOCVD (metal organic chemical vapor decomposition) process or a sputtering process.
- MOD metal organic deposition
- MOCVD metal organic chemical vapor decomposition
- the high- ⁇ dielectric / ferroelectric 13 After the high- ⁇ dielectric / ferroelectric 13 has been deposited, it must be annealed ("conditioned") in an oxygen-containing atmosphere at high temperatures. In order to avoid an undesired reaction of the high ⁇ dielectric / ferroelectric 13 with the electrodes 11, 12, these are made of Pt (or another sufficiently temperature-stable and inert material). In addition, a continuous barrier structure 14 with contact layers (not shown in FIG. 1) arranged below the barrier structure 14 is provided to protect the connection structure 9 below the lower Pt electrode 11.
- FIGS. 2A-D A first exemplary embodiment according to the invention for producing a barrier structure is illustrated in FIGS. 2A-D.
- the same or comparable parts as in the previous figure are identified by the same reference numerals.
- the three layers 15.1 ', 15.2' and 14 ' are structured together by ion etching.
- a barrier structure 14.1 and an Ir contact layer structure 15.2 and a Ti contact layer structure 15.1 are formed.
- the structure width can be in the sub- ⁇ m range.
- a barrier interlayer 16 is deposited in a next step.
- This can be, for example, a TEOS oxide layer.
- a CVD (chemical vapor deposition) process can be used for the deposition.
- the thickness of the barrier embedding layer 16 depends on the thickness of the barrier structure 14.1 to be buried and can be between 200 and 1500 nm
- the barrier interlayer 16 is now polished back by means of CMP.
- the polishing process can be stopped on the surface of the Ir0 2 barrier structure 14.1.
- a surface of the barrier interlayer 16 and the barrier structure 14.1 of excellent planarity is produced.
- FIGS. 3A-B A first possibility for realizing the lower capacitor electrode 11 is shown in FIGS. 3A-B.
- PVD physical vapor deposition
- Electrode layer 11 ' is applied to the planarized surface of the barrier embedding layer 16 and the barrier structure 14.1 stored therein.
- the Pt electrode layer 11 'can have a thickness of 50 nm to 400 nm.
- the lower capacitor electrode 11 is formed from the Pt electrode layer 11 ′ by ion etching (see FIG. 3B).
- the Pt electrode layer 11 ' can be a thin (5 to 50 nm) Ir0 2 layer (not shown) can be deposited as an adhesive layer.
- an electrode insertion layer 17 ′ is produced on the planarized surface of the barrier insertion layer 16 (with an inserted barrier structure 14.1).
- the electrode interlayer 17 ' may also be a TEOS layer. Your layer thickness corresponds to the desired one
- the electrode insertion layer 17 ' is structured by a lithography and etching step.
- the top of the barrier structure 14.1 is exposed at the bottom of the electrode structuring hole 18 produced in the process.
- the entire surface of the Pt electrode layer is deposited using a PVD, CVD or platinization process.
- the electrode structuring hole 18 is completely filled with electrode material (Pt).
- the Pt electrode layer is polished back using CMP.
- the arrangement shown in FIG. 4C with a fully structured capacitor electrode 11 results.
- the structured electrode interlayer 17 ′ is removed by wet chemical means.
- the lower capacitor electrode 11 produced in the manner described remains.
- FIGS. 5A-E A second exemplary embodiment according to the invention is shown in FIGS. 5A-E.
- the starting point is again a planarized cover oxide layer 7 with a polysilicon connection structure 9.
- the polysilicon connection structure 9 is first etched back selectively. This creates a recess 19, the depth of which is approximately 50 to 100 nm.
- a thin first contact layer for example made of Ti, thickness 5 to 50 nm
- a second thicker contact layer for example made of Ir, thickness about 50 to 250 nm
- the deposition of the contact layers is controlled so that the recess 19 is only partially filled after the deposition of the first contact layer and is completely filled up by the deposition of the second contact layer.
- the two contact layers are then polished back using CMP.
- the cover oxide layer 7 serves as the stop layer.
- a planar surface is formed over the entire surface, a pot-like first contact layer structure 15.1a made of Ti above the reduced connection structure 9 and a second contact layer structure 15.2a made of e.g. I realized.
- a barrier interlayer is then produced and structured in accordance with the illustration shown in FIG. 5C, see reference numeral 16a.
- the structuring takes place through photolithographic and etching processes.
- the bottom of the barrier structuring hole 20 created here is at least partially formed by the contact layer structures 15.1a and 15.2a.
- a whole-area layer 14a 'made of barrier material (for example IrO 2 ) is deposited, see FIG. 5D.
- the barrier layer 14a 1 is then polished back by means of CMP, it being possible for the barrier layer 16a to be used as the stop layer.
- 5E shows the planarized barrier embedding layer 16a with the barrier structure 14.1a mounted therein.
- the deposition and structuring of the lower Pt capacitor electrode 11 can again be carried out either in accordance with FIGS. 3A-B or in the manner shown in FIGS. 4A-D.
- FIGS. 6A-E A third exemplary embodiment for producing a lower capacitor electrode with an underlying barrier structure is explained with reference to FIGS. 6A-E.
- the starting point is the structure of FIG. 6A already explained with reference to FIG. 5A.
- the next process step (deposition of the contact layers and CMP planarization) are also identical to the process steps already described in connection with FIG. 5B.
- the structure shown in FIG. 6B results.
- a barrier-embedding layer 16b is applied to the planarized structure shown in FIG. 6B (still analogous to the second exemplary embodiment).
- the barrier interlayer 16b can in turn be a TEOS oxide layer.
- the barrier interlayer 16b is now structured by photolithography and etching.
- the structure width of the structuring hole 20b created in this way corresponds to the desired lateral dimension of the lower capacitor electrode, i.e. can be larger than the structure width of the structuring hole 20a.
- a barrier layer 14b ' is first deposited over the entire surface of the structure shown in FIG. 6C.
- the barrier layer 14b ' can in turn consist of Ir0 2 and coats the floor and the Sidewalls of the Bamere structure hole 20b.
- a thin layer 11b 'of electrode material (for example Pt) is then deposited on the barrier layer 14b'.
- Their layer thickness can be approximately 50 nm. Due to the small thickness of the electrode material layer 11b ', the barrier structuring hole 20b is not completely filled.
- both layers i.e. the electrode material layer 11b 'and the barrier layer 14b' are polished back by means of CMP.
- the barrier interlayer 16b can in turn be used as the stop layer.
- the CMP process can be carried out either as a one-step process or as a two-step process. In the case of a one-stage process control, the same polishing agent ("slurry") is used for the polishing of the two layers 11b 'and 14b'.
- the structure resulting from the planarization step is shown in FIG. 6E.
- the barrier structure 14.1b formed from the barrier layer 14b 'as well as the lower capacitor electrode 11b formed from the electrode material layer 11b' have the shape of a pot.
- the area of the capacitor electrode 11b can approximately correspond to the area of the capacitor electrode 11m in the first two exemplary embodiments and is therefore sufficiently large.
- the ferroelectric / dielectric layer for producing the capacitor dielectric / ferroelectric 13 is deposited and finally the upper capacitor electrode 12 is manufactured by a further layer generation and structuring process.
- An advantage of the process flow described in the third exemplary embodiment is that, overall, only a single lithograph / etching step is required. For this reason, the process is extremely inexpensive and time-saving.
- other materials such as Ru, Pd, Re, Os, Rh, Pt, W, Ta, Hf, La, Mo, Nb and alloys thereof can be used for the upper contact layer structure 15.2, 15.2a in addition to Ir.
- Ti, Cr, V, Co, Ni or their suicides can also be used for the lower contact layer structure 15.1, 15.1a.
- the barrier layer 14 ', 14a 1 , 14b' can also consist of the conductive oxides of the materials mentioned for the upper contact layer structure.
- Ir, Ru, Re and alloys of these materials, their oxides and ternary oxides of the strontium-ruthenium oxide (SrRu0 3 ) type can also be used for the electrode material layer 11 'in addition to Pt.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00983035A EP1222684A2 (de) | 1999-10-20 | 2000-10-16 | Verfahren zur herstellung einer kondensator-elektrode mit barrierestruktur |
JP2001531134A JP3964206B2 (ja) | 1999-10-20 | 2000-10-16 | バリア構造を有するコンデンサ電極の製造方法 |
US10/127,618 US6686265B2 (en) | 1999-10-20 | 2002-04-22 | Method of producing a capacitor electrode with a barrier structure |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19950540.3 | 1999-10-20 | ||
DE19950540A DE19950540B4 (de) | 1999-10-20 | 1999-10-20 | Verfahren zur Herstellung einer Kondensator-Elektrode mit Barrierestruktur |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/127,618 Continuation US6686265B2 (en) | 1999-10-20 | 2002-04-22 | Method of producing a capacitor electrode with a barrier structure |
Publications (2)
Publication Number | Publication Date |
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WO2001029885A2 true WO2001029885A2 (de) | 2001-04-26 |
WO2001029885A3 WO2001029885A3 (de) | 2001-06-14 |
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ID=7926289
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Application Number | Title | Priority Date | Filing Date |
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PCT/DE2000/003662 WO2001029885A2 (de) | 1999-10-20 | 2000-10-16 | Verfahren zur herstellung einer kondensator-elektrode mit barrierestruktur |
Country Status (7)
Country | Link |
---|---|
US (1) | US6686265B2 (de) |
EP (1) | EP1222684A2 (de) |
JP (1) | JP3964206B2 (de) |
KR (1) | KR100471730B1 (de) |
DE (1) | DE19950540B4 (de) |
TW (1) | TW490809B (de) |
WO (1) | WO2001029885A2 (de) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100418589B1 (ko) * | 2001-11-12 | 2004-02-14 | 주식회사 하이닉스반도체 | 강유전체 메모리 소자의 콘캐이브형 캐패시터 형성방법 |
US7221015B2 (en) | 2002-03-18 | 2007-05-22 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
US7270884B2 (en) * | 2003-04-07 | 2007-09-18 | Infineon Technologies Ag | Adhesion layer for Pt on SiO2 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001284548A (ja) * | 2000-03-31 | 2001-10-12 | Fujitsu Ltd | 半導体記憶装置及びその製造方法 |
KR20030023143A (ko) * | 2001-09-12 | 2003-03-19 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
US7001780B2 (en) * | 2003-08-06 | 2006-02-21 | Infineon Technologies Ag | Method of fabrication of an FeRAM capacitor and an FeRAM capacitor formed by the method |
US20050070030A1 (en) * | 2003-09-26 | 2005-03-31 | Stefan Gernhardt | Device and method for forming a contact to a top electrode in ferroelectric capacitor devices |
JP5608317B2 (ja) * | 2008-03-07 | 2014-10-15 | ピーエスフォー ルクスコ エスエイアールエル | キャパシタ用電極及びその製造方法、半導体装置 |
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Also Published As
Publication number | Publication date |
---|---|
US20020151162A1 (en) | 2002-10-17 |
DE19950540A1 (de) | 2001-05-03 |
JP3964206B2 (ja) | 2007-08-22 |
DE19950540B4 (de) | 2005-07-21 |
EP1222684A2 (de) | 2002-07-17 |
KR100471730B1 (ko) | 2005-03-10 |
US6686265B2 (en) | 2004-02-03 |
KR20020047253A (ko) | 2002-06-21 |
WO2001029885A3 (de) | 2001-06-14 |
TW490809B (en) | 2002-06-11 |
JP2003512721A (ja) | 2003-04-02 |
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