Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
  • H10D10/01—Manufacture or treatment
  • H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02367—Substrates
  • H01L21/0237—Materials
  • H01L21/02373—Group 14 semiconducting materials
  • H01L21/02381—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02439—Materials
  • H01L21/02441—Group 14 semiconducting materials
  • H01L21/0245—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02521—Materials
  • H01L21/02524—Group 14 semiconducting materials
  • H01L21/02532—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02612—Formation types
  • H01L21/02617—Deposition types
  • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
  • H10D10/80—Heterojunction BJTs
  • H10D10/821—Vertical heterojunction BJTs
  • H10D10/891—Vertical heterojunction BJTs comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
  • H01L21/2205—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping

Definitions

• the invention relates to a layer structure for bipolar transistors and a method for their production and a method for integrated circuits produced on this basis.
• Si x Ge y C ⁇ - xy heterostructures with the parameters x, y in the range 0 ⁇ x, y ⁇ 1, lie, among other things, in their extreme speed, their low base resistances and improved noise behavior .
• the technology for manufacturing integrated circuits using Si x GeyC ⁇ -x -y / Si HBT's is compatible with the widely established mass technology for integrated circuits based on silicon.
• the advantages listed make fast transistors based on Si x Ge y C ⁇ -xy layer structures a preferred variant for highly integrated circuits with use in modern telecommunications.
• the base of the transistor structure is made from Si x Ge y C ⁇ -x . y , Si x Ge ⁇ -x layers with thicknesses of sometimes less than 20 nm.
• the perfection of the grown epitaxial layers and the interfaces that arise during the layer deposition is a prerequisite for a high yield of good transistors and circuits and for the correct functioning of the corresponding circuits.
• the problem of poly-Si emitter layers on silicon for the production of bipolar transistors has recently been increasingly investigated. In order to achieve sufficient current amplification in the manufacture of the vertical structures, oxygen-contaminated interfaces with increased emitter resistances were accepted [JS Hamel, DJ Roulston, CR Selvakumar. IEEE Electron Device Letters, 13 (6), 332 (1992)].
• the Si layer forming the emitter and emitter connection is designed according to the prior art both for silicon, Si homostructures and in Si / Si / Si x Ge y C ⁇ -xy / Si hetero structures as a polycrystalline Si layer, as described in many publications [for example in JD Cressler, IEEE Electron Device Lett, 17, 13 (1996), D. Knoll et al., IEDM Techn. Dig., 703 (1998)]
• the invention is based on the object of proposing a layer structure for bipolar transistors with the aid of which the electrical properties and the homogeneity of bipolar transistors are improved.
• the base current behavior is to be improved and the noise is to be reduced, and a method for producing bipolar transistors with such a layer Structure are shown, with the help of which it is possible to manufacture integrated circuits with such bipolar transistors with good yield and reproducibility.
• the vertical structure of the transistors contains a partially monocrystalline emitter layer, which turns into a polycrystalline and / or amorphous layer above an epitaxial, single-crystal growth layer and the partially single-crystalline emitter layer locally in the vertical structure of the transistor thin oxide and / or nitride layers.
• the partially monocrystalline emitter layer is deposited on a Si x Ge y C ⁇ -xy cover layer, a Si buffer layer and a silicon substrate with the parameters x, y in the range 0 ⁇ x, y ⁇ 1.
• the interface between the partially monocrystalline emitter layer and the substructure is characterized by a low oxygen contamination with an oxygen dose of less than 1 x 10 15 cm ⁇ 2 .
• At least part of the electrically active zone of the partially monocrystalline emitter layer is formed by a Si x Ge y CC -x-> cover layer with the parameters x, y in the range 0 ⁇ x, y ⁇ 1.
• the method according to the invention for producing the layer structure for Si-based bipolar transistors is based on the fact that
• a doping gas is supplied during the cooling to the layer growth temperature and that
• the partially monocrystalline emitter layer is advantageously applied in a multi-disk reactor by means of chemical vapor deposition at low pressure.
• the partially monocrystalline emitter layer is preferably formed by a doped Si x Ge ,, C ⁇ -xy layer with the parameters x, y in the range 0 ⁇ x, y ⁇ 1.
• the samples are subjected to an intensive nitrogen purge of at least 15 minutes in a cold CVD reactor without pre-tempering the CVD system in hydrogen-containing gases.
• the layer structure is subjected to further technological sub-steps, such as, for example, oxidations, implantations, etching, partial sub-steps.
• the monocrystalline growth of the partially monocrystalline Si emitter layer is maintained until the end of the layer deposition, so that there is no changeover to polycrystalline / amorphous growth.
• the doping element for the partially monocrystalline emitter layer is As and / or P.
• At least one emitter dopant is introduced during the CVD deposition process. The emitter dopant is advantageously introduced during the cooling process and before the silane addition to grow the partially monocrystalline emitter layer.
• a homogeneously doped partially single-crystal emitter layer or alternatively doped and undoped regions of the partially single-crystal emitter layer to increase the growth rate are deposited.
• the partially monocrystalline emitter layer is applied to Si substrate wafers.
• the partially crystalline emitter layer is coated on commercial Si substrate wafers or on commercial "silicon-on-insulator” (SOI) wafers and Si wafers with homoepitaxial layers and Si base structures and Si formed in accordance with the prior art - Collector structures applied.
• SOI silicon-on-insulator
• the partially-single-crystal emitter is in layer of the heterostructure Si - emitter / Si / Si y C ⁇ -y / Si substrate for use.
• the partially crystalline emitter layer comes in three-component material systems of the type Si - emitter / Si / Si x Ge y C ⁇ -xy , Si x Ge y O ⁇ - ⁇ -y , with the parameters x, y in the range 0 ⁇ x , y ⁇ 1, are used on Si substrates.
• a silicon wafer is provided with a layer stack for a heterobipolar transistor which is produced according to the prior art.
• the layer stack consists of a doped Si buffer layer 2 directly on the Si substrate 1 for forming the collector, an Si x Ge y C ⁇ -x- layer 3 with the parameters x, y in the range 0 ⁇ x, y ⁇ 1, to form the base, an epitaxial Si cover layer 4 and a polycrystalline silicon layer to form the emitter 5.
• the critical interface 6 between the Si emitter layer 5 and the epitaxial Si cover layer 4 is contaminated with oxide residues and / or strong oxygen contamination in a layer production according to the prior art.
• the polycrystalline emitter layer can also be formed by a Si x Ge- ⁇ layer. Outside of the section shown, the layer deposition as a polycrystalline layer can also take place via nitride or oxide layers produced according to the prior art or over other layer structures.
• 1b schematically shows the same layer stack produced according to the solution according to the invention, in which the interface 6 is only contaminated to a small extent by acid.
• Concentrations of substance of preferably less than 1 x 10 5 cm ⁇ is characterized and in which after initially epitaxial, single-crystalline growth of the Si emitter layer 5 in later growth stages, crystallographic defects arise which only form a significant distance with the formation of a further interface 7 in polycrystalline growth the Si emitter layer 5 end.
• Fig.lc shows the borderline case of a completely single-crystal emitter layer 5, as can be produced, for example, in growth in ultra-high vacuum (UHV) systems for molecular beam epitaxy (MBE) or at high temperatures and / or in extremely clean normal pressure and low pressure CVD systems.
• UHV ultra-high vacuum
• MBE molecular beam epitaxy
• 2b shows a transmission electron micrograph of a cross section through the partially monocrystalline emitter layer 5 with the two interfaces 6 and 7 the success of the method for producing transistors with a partially monocrystalline emitter layer 5.
• a commercial, industry-compatible LP-CVD system with a large wafer capacity, for example of more than 50 wafers per process, originally specified for deposition of polycrystalline silicon, can be used for the production of the vertical transistor structure according to the invention.
• the preceding technological steps in transistor production as well as the lateral structure of the transistor correspond to the state of the art.
• the method according to the invention is used for the production of the vertical layer sequence in the transistor structure, in particular the production of the partially monocrystalline emitter layer 5.
• the wafer is cleaned on the Basis of solvents containing hydrofluoride. The storage time of the samples after the etching is limited to less than one hour without special surface passivation.
• the solution according to the invention can also be used in CVD systems without a wafer lock, which avoids the ventilation of the overall system.
• the plant is subjected, according to the invention, to an intensive nitrogen purge of at least 15 minutes in a cold reactor.
• the invention can be used to cool the growth temperature in the range from 450 ° C. to 700 ° C., preferably 550 ° C., the doping gas is switched on for the in-situ doping of the layer, preferably with arsenic or phosphorus.
• the oxygen contamination of the boundary surface 6 between the emitter layer 5 and the silicon substrate 1 and the Si cap layer 4 is achieved according to a built-oxygen dose of less than 5 x 10 cm ", preferably less than
• the advantages of the method according to the invention can be seen.
• the almost perfect interface 6 enables homogeneous diffusion and a low contact resistance.
• the low surface roughness of the emitter contact which is significantly lower than in the case of polycrystalline emitter layers with large grains produced in accordance with the prior art, can also be seen in FIG. 2 (b).
• the layer deposition can initially be substantially shortened with the same layer thickness after initially growing single-crystal. This leads to a shortening of the entire technological process.
• the deposition of the in-situ doped emitter layers 5 can save subsequent implantations for emitter doping.
• Another advantage of the invention is that the lack of the contaminated interface homogenizes the diffusion of the dopant, which is also reflected in an improvement in the electrical parameters.
• the solution according to the invention opens up the possibility of starting the growth process with a selective, epitaxial deposition, this layer initially depositing only in the open windows which are not covered with oxide. The difference in height between the Si surface and the oxide surface is reduced. It is only when the polycrystalline silicon is turned over in the open windows that non-selective layer growth begins on the entire wafer.
• the solution according to the invention also enables the creation of a corresponding layer structure on "silicon on insulator” (SOI) wafers.
• SOI silicon on insulator
• the transistor according to the invention with the partially monocrystalline emitter layer 5 and the method for its production enable use in modern Si x Ge y C ⁇ -xy technologies, with the parameters x, y in the range 0 ⁇ x, y ⁇ 1, which is perspective for the Manufacture of modern highly integrated circuits for mobile communication are provided.

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Chemical & Material Sciences (AREA)
• Materials Engineering (AREA)
• Bipolar Transistors (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (1)

Family

ID=7919533

Family Applications (1)

Country Status (4)

Cited By (1)

Families Citing this family (3)

Citations (2)

Family Cites Families (11)

• 1999
  • 1999-08-26 DE DE19940278A patent/DE19940278A1/de not_active Withdrawn
• 2000
  • 2000-07-28 WO PCT/DE2000/002491 patent/WO2001017002A1/de not_active Ceased
  • 2000-07-28 EP EP00958187A patent/EP1212786B1/de not_active Expired - Lifetime
  • 2000-07-28 JP JP2001520454A patent/JP2003528443A/ja active Pending

Patent Citations (2)

Non-Patent Citations (6)

Also Published As

Similar Documents

Legal Events