WO2001006461A1 - Procede et dispositif de dessin - Google Patents

Procede et dispositif de dessin Download PDF

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Publication number
WO2001006461A1
WO2001006461A1 PCT/JP1999/003813 JP9903813W WO0106461A1 WO 2001006461 A1 WO2001006461 A1 WO 2001006461A1 JP 9903813 W JP9903813 W JP 9903813W WO 0106461 A1 WO0106461 A1 WO 0106461A1
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WO
WIPO (PCT)
Prior art keywords
block
processing
data
blocks
command
Prior art date
Application number
PCT/JP1999/003813
Other languages
English (en)
Japanese (ja)
Inventor
Junko Nakase
Takashi Nakamoto
Hiromi Watanabe
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1999/003813 priority Critical patent/WO2001006461A1/fr
Priority to AU46523/99A priority patent/AU4652399A/en
Publication of WO2001006461A1 publication Critical patent/WO2001006461A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/147—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using display panels

Definitions

  • the present invention relates to a drawing processing method and a drawing processing apparatus, and more particularly, to a drawing processing method and a drawing apparatus for processing a graphics image such as a line segment and a polygon (polygon) with digital data.
  • the present invention relates to a drawing processing method and an image processing apparatus that divide and execute processing for each block.
  • FIG. 2 In the above-described apparatus, in order to reduce the memory cost, as shown in FIG. 2, an external memory 4 is shared by the drawing processing apparatus 1 for drawing a graphics image and the other processing circuits 5 and 6. It is possible. However, the processing circuit 5 to the processing circuit 6 shown in FIG. 2 are circuits having certain independent processing functions, such as the above-mentioned MPEG decoding processing. In the apparatus shown in FIG.
  • the drawing processing unit 1 and the processing circuits 5 and 6 in order for the drawing processing unit 1 and the processing circuits 5 and 6 to efficiently share the shared memory 4, the drawing processing unit 1 and the processing circuits 5 and 6 must be accessed from the shared memory 4. It is desirable to perform the access in units of data rather than random access. If the rendering processing device 1 performs processing in units of a set of data, the configuration may be such that the rendering process is performed in blocks of m pixels X n pixels (m and n are integers of 1 or more). Conceivable. An example of a drawing processing circuit that processes a plurality of polygons in one screen in units of blocks is described in the device disclosed in Japanese Patent Publication No. 10-32-0753. There is.
  • This drawing processing circuit After accumulating polygon data for each surface and obtaining all polygons for each block in advance, the processing for each block is executed. That is, it is necessary to temporarily hold data (coordinate values, luminance values, etc.) for all polygons in one screen. In addition, it is necessary to create a list of polygons for each block based on the data of all polygons in one screen, and retain that information. For this reason, there is a problem that the amount of memory for retaining data becomes large.
  • an object of the present invention is to realize a drawing processing method and a drawing processing capable of reducing a memory capacity required for holding data on polygons. It is another object of the present invention to provide a rendering apparatus which can share a memory with another processing circuit having an independent function and requires a small amount of memory. Disclosure of the invention
  • a screen is divided into a plurality of blocks of m pixels X n pixels (m and n are integers equal to or greater than 1), and a graphics title image is displayed on the screen according to a drawing command.
  • a drawing processing apparatus for processing drawing by digital data in block units for each drawing command sequentially input, a block including a pixel (hereinafter referred to as a drawing area) drawn by the drawing command is obtained.
  • the drawing process of the drawing command is executed for each block obtained.
  • the drawing command refers to a data string that specifies drawing of a graphic image such as a line segment or a polygon, and the data string specifies at least a position on the screen to be drawn. Contains drawing position information.
  • the drawing processing apparatus of the present invention divides the screen into a plurality of blocks of m pixels ⁇ n pixels (m and n are integers of 1 or more), and draws the polygon image on the screen according to a polygon drawing command.
  • This is configured to include the following means, based on a drawing processing apparatus that performs the processing in units of blocks.
  • Processing block determining means for obtaining M blocks (M is an integer of 0 or more) (hereinafter referred to as processing blocks);
  • a block processing unit that sequentially inputs block parameters specifying the M processing blocks and data from the command buffer unit from the processing block determination unit, and processes an image in a processing block area specified by the block parameters.
  • the data of the processing block specified by the processing block determination means is read from the externally connected memory means and stored in the plotter coffer memory means, and for the processing block specified by the processing block determination means, An operation necessary for drawing is executed based on the drawing command, and the pixel data obtained as a result is stored in the block buffer memory means.
  • the block buffer memory means transfers the pixel data to the memory.
  • drawing processing is executed in the order of drawing commands given by a CPU (Central Processing Unit) and the like, and drawing commands for one screen are accumulated in order to execute the drawing processing in block units. There is no need to c. It is not necessary to obtain and hold drawing commands related to each block in advance. Therefore, according to the present invention, it is possible to realize a drawing processing device which can execute processing in units of blocks and has a small amount of memory for storing drawing commands. This is especially effective when using an external common memory with at least one screen capacity.
  • FIG. 1 is a processing flowchart of an embodiment of a drawing processing method according to the present invention.
  • FIG. 2 is a diagram showing a general configuration of a drawing processing device and peripheral circuits.
  • FIG. 3 is a diagram showing a configuration of a first embodiment of a drawing processing apparatus according to the present invention.
  • FIG. 4 is a diagram showing a relationship between a drawing area and a processing block.
  • FIG. 5 is a diagram showing a relationship between a drawing surface of a line segment and a processing block.
  • FIG. 6 is a diagram for explaining a line segment drawing procedure.
  • FIG. 7 is a diagram illustrating a drawing example using a plurality of drawing commands.
  • FIG. 8 is a time chart for explaining processing of a plurality of drawing commands in one embodiment of the present invention.
  • FIG. 9 shows the configuration of a second embodiment of the drawing processing apparatus according to the present invention.
  • FIG. 10 is a time chart for explaining the processing of the drawing processing apparatus in FIG.
  • FIG. 11 is a diagram showing the configuration of a third embodiment of the drawing processing apparatus according to the present invention.
  • the first 2 figures Figure s first 3 is a time chart for explaining the processing of the drawing processing apparatus of FIG. 1 1 is Ru FIG der showing the proc list used in the first embodiment of the present invention.
  • FIG. 1 shows a processing flow of a first embodiment of a drawing processing method according to the present invention.
  • a polygon drawing command is input from the CPU (Central Processing Unit) (s1).
  • the drawing command is a data string that specifies at least the type of drawing figure (line segment, rectangle, etc.) and the coordinates of the start point, end point, or vertex (hereinafter referred to as drawing position information).
  • drawing position information the coordinates of the start point, end point, or vertex
  • a drawing process for each block is executed (s3).
  • the processing for a certain block is completed, if there is a next block, the processing for the next block is executed.
  • the next drawing command The same processing is performed.
  • FIG. 3 shows a configuration of an embodiment of a drawing processing apparatus and peripheral circuits for performing the drawing method of the present invention.
  • the drawing processing device 100 is connected to the CPU 2 via the CPU data bus 150 and to the external shared memory 41 via the data bus 151.
  • the drawing processing unit 3100 processes from a command buffer 160 for buffering drawing commands sent from the CPU 2 via the CPU data bus 150 and a drawing command given from the command buffer 160.
  • a block is determined, and a block parameter for designating a processing block is given to the block processing unit 120.
  • the processing block determination unit 110 and the block specified by the processing block determination unit 110 are determined based on the drawing command.
  • a block processing unit 120 that executes the operations required for drawing and writes it to the block buffer memory 130, and the external memory 41 via the data bus 15 1 and data in block units! It consists of a block buffer memory 130 that performs ⁇ and power.
  • a drawing command is input from the CPU 2 to the command buffer 160 via the CPU data bus 150.
  • the drawing command is buffered and sent to the processing block determination unit 110 and the block processing unit 120.
  • the processing block determination unit 110 executes processing as follows. As shown in Fig. 4, taking the case where drawing command a is a drawing command for drawing a quadrilateral polygon as an example, the relationship between the drawing area of drawing command a and the processing block is shown. It is composed of m pixels and n pixels in the vertical direction. Symbols B0 to B11 are symbols for identifying block 0 to block 11, respectively.
  • the processing block determination unit 110 operates so as to sequentially output block parameters specifying these processing blocks to the block processing unit 120.
  • Block coordinates (bx, by) may be defined as block unit coordinates, and the block coordinates of the processing block may be used as block parameters.
  • the above block parameters can be obtained from the drawing position information of the drawing area given by the drawing command, that is, the coordinates of the four vertices of polygon 1.
  • the processing block determination unit 110 keeps the block parameters of the processing blocks as a list (block list) at the time of processing as shown in FIG. 13, for example, and holds and sequentially reads the block list.
  • the block parameter may be given to the block processing unit 120, or the block parameter of the next processing block may be calculated by calculation each time and the block parameter may be given to the block processing unit.
  • the determination unit 110 may be any unit that can sequentially output the parameters of the processing blocks, and does not necessarily need to determine the positions and numbers of all the processing blocks to be processed by each drawing command prior to the drawing process.
  • the processing block is determined each time by sequentially determining whether or not the block is a processing block. It may be.
  • the block processing unit 120 executes a block drawing process specified by the block parameter based on the block parameter given from the processing block determination unit 110 and the drawing command given from the command buffer 160.
  • the block drawing process includes the following three steps. That is, (1) the data of the block specified by the block parameter is read from the external memory 41 into the block buffer memory 130, and (2) the data necessary for drawing is stored in the block processing unit 120. Execute and write the obtained pixel data to the block buffer memory 130. (3) Write back the block data from the block buffer memory 130 to the memory 41.
  • the drawing processing procedure of the block will be described using the case as an example. In Fig. 5, as in Fig.
  • a screen (frame) is divided into 12 by a block of m pixels in the horizontal direction and n pixels in the vertical direction, and blocks B4, B5, and B6 are provided.
  • the processing blocks are blocks B4, B5, and B6.
  • blocks B4, B5, and B6 are sequentially processed in the order of blocks.
  • the parameters are supplied to the block processing unit 120.
  • the block processing unit 120 executes block drawing processing in the order of blocks B4, B5, and B6 as shown in FIG. First, a block parameter of the block B4 is given, and a block drawing process is performed on the block B4.
  • the data of the pixel included in the block B4 in the line segment PQ shown in FIG. 6 (a) is written to the memory 41.
  • the block drawing process is similarly performed for blocks B5 and B6, and the block PQ of the line segment PQ shown in FIGS. 6 (b) and (c) is respectively obtained.
  • the data of the pixels included in B5 and B6 are written to the external memory 41c
  • the block processing unit 12 includes drawing commands and processing blocks from the command buffer 160.
  • the block parameter of the processing block is given from the determination unit 110.
  • the drawing command contains the coordinate values of pixels p and Q. These blockno ,.
  • the block processing unit 120 obtains the coordinates of the starting point of the drawing in each processing block, and performs the drawing process from the starting point to the end point of the line segment.
  • block B4 in FIG. 6 (a) since the start point P of the line segment is in block B4, ⁇ becomes a platform point, and processing is performed up to the rightmost block boundary of ⁇ 4.
  • the line segment PQ and the block are obtained from the coordinate value data of points P and Q, and the X coordinate, Y coordinate and force of the processing block boundary obtained from the block parameters. From the two intersections with the boundary, the intersection closer to the start point P is used as the start point, and the drawing process is executed up to the block boundary on the right end of B5. Similarly, the intersection of the boundary between the line segment PQ and the boundary of the block B6 is determined for ⁇ of the block B6 in FIG.
  • FIG. 7 shows a drawing example using a plurality of drawing commands.
  • drawing command a (B0, B1, B2, B3)
  • drawing command b (B5, B6, B9, B10, B11 )
  • Drawing command c (B2, B3, B6, B7).
  • FIG. 8 shows a time chart of ⁇ for continuously processing the above three commands a, b, and c.
  • the command a is input to the processing block determination unit 110 and the block processing unit 120 via the command buffer 160.
  • the processing block determination unit 110 calculates the processing blocks B 0, B 1, B 2, and B 3 based on the coordinate values of the start point and the end point of the line segment included in the drawing command 1, and then calculates the blocks B 0, B 1, and B 2 , B 3 are sequentially given to the block processing unit 120.
  • the block processing unit 120 Upon receiving the block parameters from the processing block confirmation 110, the block processing unit 120 sequentially performs block drawing processing on the blocks specified by the block parameters. In this way
  • the lock processing unit 120 sequentially executes the drawing processing of the blocks B0, B1, B2, and B3. When the drawing processing of the block B3 ends, the processing by the drawing command a ends.
  • the command buffer 16 fetches the drawing command b from the CPU data bus 15.0 and gives it to the processing block determination unit 110 and the block processing unit 120.
  • block drawing processing is performed on the processing blocks B5, B6, B9, B10, and B11 in the same manner as in the drawing command a. Are sequentially executed.
  • the same processing is performed for the drawing command c as for the drawing command a and the drawing command Kb.
  • FIG. 9 is a diagram showing the configuration of a second embodiment of the drawing processing apparatus according to the present invention.
  • the block buffer memory 130 which was one surface in the drawing processing apparatus 100 of the first embodiment, is replaced with the block buffer memories 130-1 and 130-0. It has a two-sided configuration.
  • the selection means 140 and 41 for switching between the two blocks of the block buffer memories 13 0-1 and 13 0-2 are provided by the block processing section 12 1 and the block buffer memory 13 0-1, respectively. It is provided between 1 3 0-2 and between the data bus 15 1 and the block buffer memory 13 0-1 and 13 0-2. Since other components are substantially the same as those in FIG. 3, the same functional units are assigned the same reference numerals as those in FIG. 3 and their explanation is omitted.
  • FIG. 10 shows a time chart of the drawing processing when executed by the drawing processing apparatus 101 of FIG.
  • the block processing unit 12 1 executes block processing using the block buffer memory 13-1, while the block buffer memory 13
  • the data of the block B 1 to be processed next is read from the memory 41 for 1 3 0-2.
  • the block processor 1 21 finishes writing the block B 0 to the block buffer memory 1 3 0 1
  • the block buffer memory 1 3 0 By switching to 2, the calculation and writing of the pixel data of block B1 is started immediately.
  • the processing result of the block B0 stored in the block buffer memory 1330-1 is written to the memory during the calculation and writing of the pixel data of the block B1.
  • the block processing unit 1221 calculates and writes pixel data to the block buffer memories 130-1 and 130-2
  • the other block is processed.
  • Data between Lock Knocker memory and external memory 41! Becomes possible, the drawing processing apparatus of the first embodiment (see FIGS. 3 and 8) starts the block drawing processing of the next processing block after all the block drawing processing of one processing block is completed.
  • the processing time can be shortened and the performance can be improved as compared with the case of the first embodiment.
  • FIG. 11 shows the configuration of a third embodiment of the drawing processing apparatus according to the present invention.
  • two block processing units 1 2 1 1 and 1 2 1 2 are provided, and a block buffer is provided in each of the two block processing units 1 2 1-1 and 1 2 1-2.
  • the block drawing processing is executed in parallel for two processing blocks.
  • FIG. 12 shows a time chart of the processing in the second and third embodiments.
  • FIGS. 12 (a) and (b) show the cases of the drawing processing apparatuses of the second and third embodiments, respectively.
  • blocks R and W indicate a data read period from the memory and a data write period to the memory, respectively.
  • the shaded blocks indicate the data writing period from the block processing unit.
  • block drawing processing can be executed in parallel for two blocks. That is, in the second embodiment, the arithmetic operation ⁇ writing of the pixel data is performed only on the block stored in one of the block buffer memory 130-1 and the block buffer memory 130-2. Because it is executable, one block buffer memory waits while pixel data is calculated and written on the other. In the third embodiment, the waiting time can be eliminated, and the performance can be further improved as compared with the second embodiment. In particular, it is effective when the time required for drawing processing in one block is longer than the time required for data transfer between the block buffer memory and the (shared) memory.
  • the drawing command of the drawing processing device is given from the CPU.
  • the means for giving the drawing command does not necessarily need to be the CPU.
  • a vertex coordinate calculation of a polygon (geometry operation) May be a dedicated circuit for performing the above.
  • drawing processing is executed in the order of drawing commands given by the CPU and the like, and the drawing processing is executed in units of blocks, so that it is not necessary to accumulate two drawing commands for one screen. Therefore, it is possible to realize a ray drawing processing device which can execute processing in block units and has a small memory amount.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Generation (AREA)

Abstract

Cette invention concerne un dispositif de dessin qui consiste à diviser un écran en blocs de m x n pixels (n et n sont des entiers de 1 ou plus) et de tracer une image graphique sur l'écran selon les instructions de dessin en unités de bloc au moyen de données numériques, ce qui permet de partager une mémoire extérieure avec d'autres circuits de traitement. Ce dispositif comprend une mémoire tampon de blocs (130) dotée d'une capacité de données correspondant à au moins un bloc et une unité de traitement de blocs (120) capable de lire des données sur les blocs à partir des données pour un écran, données stockées dans une mémoire externe (41) pour les blocs, avec la zone dans laquelle une image est tracée conformément à l'ensemble des instructions de dessin ;de stocker des données de pixel tirées d'opérations arithmétiques nécessaires au dessin de l'image selon les instructions de dessins tirées de la mémoire tampon de blocs (130) et de re-transférer les données de la mémoire tampon de blocs (130) à la mémoire externe (41).
PCT/JP1999/003813 1999-07-15 1999-07-15 Procede et dispositif de dessin WO2001006461A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP1999/003813 WO2001006461A1 (fr) 1999-07-15 1999-07-15 Procede et dispositif de dessin
AU46523/99A AU4652399A (en) 1999-07-15 1999-07-15 Drawing method and drawing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1999/003813 WO2001006461A1 (fr) 1999-07-15 1999-07-15 Procede et dispositif de dessin

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003263650A (ja) * 2002-03-12 2003-09-19 Sony Corp 画像処理装置およびその方法
JP2007287031A (ja) * 2006-04-19 2007-11-01 Seiko Epson Corp 画像処理装置及び画像処理方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01296388A (ja) * 1988-05-25 1989-11-29 Matsushita Electric Ind Co Ltd 画像生成装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01296388A (ja) * 1988-05-25 1989-11-29 Matsushita Electric Ind Co Ltd 画像生成装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003263650A (ja) * 2002-03-12 2003-09-19 Sony Corp 画像処理装置およびその方法
US7372466B2 (en) 2002-03-12 2008-05-13 Sony Corporation Image processing apparatus and method of same
JP2007287031A (ja) * 2006-04-19 2007-11-01 Seiko Epson Corp 画像処理装置及び画像処理方法

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