WO2000055904A1 - Dram-zellenanordnung und verfahren zu deren herstellung - Google Patents
Dram-zellenanordnung und verfahren zu deren herstellung Download PDFInfo
- Publication number
- WO2000055904A1 WO2000055904A1 PCT/DE2000/000756 DE0000756W WO0055904A1 WO 2000055904 A1 WO2000055904 A1 WO 2000055904A1 DE 0000756 W DE0000756 W DE 0000756W WO 0055904 A1 WO0055904 A1 WO 0055904A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- trench
- substrate
- word lines
- insulating
- dram
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000606049A JP3786836B2 (ja) | 1999-03-12 | 2000-03-10 | Dramセル装置およびその製造方法 |
KR10-2001-7011606A KR100403442B1 (ko) | 1999-03-12 | 2000-03-10 | Dram-셀 장치 및 제조 방법 |
EP00916811A EP1161770A1 (de) | 1999-03-12 | 2000-03-10 | Dram-zellenanordnung und verfahren zu deren herstellung |
US09/951,243 US6504200B2 (en) | 1999-03-12 | 2001-09-12 | DRAM cell configuration and fabrication method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19911148.0 | 1999-03-12 | ||
DE19911148A DE19911148C1 (de) | 1999-03-12 | 1999-03-12 | DRAM-Zellenanordnung und Verfahren zu deren Herstellung |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/951,243 Continuation US6504200B2 (en) | 1999-03-12 | 2001-09-12 | DRAM cell configuration and fabrication method |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000055904A1 true WO2000055904A1 (de) | 2000-09-21 |
Family
ID=7900802
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2000/000756 WO2000055904A1 (de) | 1999-03-12 | 2000-03-10 | Dram-zellenanordnung und verfahren zu deren herstellung |
Country Status (8)
Country | Link |
---|---|
US (1) | US6504200B2 (de) |
EP (1) | EP1161770A1 (de) |
JP (1) | JP3786836B2 (de) |
KR (1) | KR100403442B1 (de) |
CN (1) | CN1150612C (de) |
DE (1) | DE19911148C1 (de) |
TW (1) | TW461086B (de) |
WO (1) | WO2000055904A1 (de) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6627940B1 (en) | 1999-03-30 | 2003-09-30 | Infineon Technologies Ag | Memory cell arrangement |
US6646299B2 (en) | 1999-10-19 | 2003-11-11 | Infineon Technologies Ag | Integrated circuit configuration having at least two capacitors and method for manufacturing an integrated circuit configuration |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10028424C2 (de) * | 2000-06-06 | 2002-09-19 | Infineon Technologies Ag | Herstellungsverfahren für DRAM-Speicherzellen |
KR100652370B1 (ko) | 2000-06-15 | 2006-11-30 | 삼성전자주식회사 | 플로팅 바디효과를 제거한 반도체 메모리소자 및 그제조방법 |
KR100473476B1 (ko) * | 2002-07-04 | 2005-03-10 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
TWI225691B (en) * | 2003-03-14 | 2004-12-21 | Nanya Technology Corp | A vertical NROM cell and method for fabrication the same |
DE10326330A1 (de) * | 2003-06-11 | 2005-01-05 | Infineon Technologies Ag | Verfahren und Hilfstransistorstruktur zur Herstellung einer Halbleiterspeichereinrichtung |
KR100660880B1 (ko) * | 2005-10-12 | 2006-12-26 | 삼성전자주식회사 | 복수의 스토리지 노드 전극들을 구비하는 반도체 메모리소자의 제조 방법 |
US7859026B2 (en) * | 2006-03-16 | 2010-12-28 | Spansion Llc | Vertical semiconductor device |
US20080315326A1 (en) * | 2007-06-21 | 2008-12-25 | Werner Graf | Method for forming an integrated circuit having an active semiconductor device and integrated circuit |
US7952138B2 (en) * | 2007-07-05 | 2011-05-31 | Qimonda Ag | Memory circuit with field effect transistor and method for manufacturing a memory circuit with field effect transistor |
JP2009182105A (ja) * | 2008-01-30 | 2009-08-13 | Elpida Memory Inc | 半導体装置及びその製造方法 |
KR100979240B1 (ko) * | 2008-04-10 | 2010-08-31 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조방법 |
US8786014B2 (en) * | 2011-01-18 | 2014-07-22 | Powerchip Technology Corporation | Vertical channel transistor array and manufacturing method thereof |
KR101168338B1 (ko) * | 2011-02-28 | 2012-07-31 | 에스케이하이닉스 주식회사 | 반도체 메모리 소자 및 그 제조방법 |
FR3023647B1 (fr) | 2014-07-11 | 2017-12-29 | Stmicroelectronics Rousset | Transistor vertical pour memoire resistive |
CN113497129B (zh) * | 2020-04-07 | 2023-12-01 | 长鑫存储技术有限公司 | 半导体结构及其制作方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02159058A (ja) * | 1988-12-13 | 1990-06-19 | Fujitsu Ltd | 半導体メモリセル |
US5497017A (en) * | 1995-01-26 | 1996-03-05 | Micron Technology, Inc. | Dynamic random access memory array having a cross-point layout, tungsten digit lines buried in the substrate, and vertical access transistors |
US5736761A (en) * | 1995-05-24 | 1998-04-07 | Siemens Aktiengesellschaft | DRAM cell arrangement and method for its manufacture |
US5828094A (en) * | 1994-03-17 | 1998-10-27 | Samsung Electronics Co., Ltd. | Memory cell structure having a vertically arranged transistors and capacitors |
EP0899790A2 (de) * | 1997-08-27 | 1999-03-03 | Siemens Aktiengesellschaft | DRAM-Zellanordnung und Verfahren zu deren Herstellung |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5208657A (en) * | 1984-08-31 | 1993-05-04 | Texas Instruments Incorporated | DRAM Cell with trench capacitor and vertical channel in substrate |
US4824793A (en) * | 1984-09-27 | 1989-04-25 | Texas Instruments Incorporated | Method of making DRAM cell with trench capacitor |
US5225697A (en) * | 1984-09-27 | 1993-07-06 | Texas Instruments, Incorporated | dRAM cell and method |
KR940006679B1 (ko) * | 1991-09-26 | 1994-07-25 | 현대전자산업 주식회사 | 수직형 트랜지스터를 갖는 dram셀 및 그 제조방법 |
US5208172A (en) * | 1992-03-02 | 1993-05-04 | Motorola, Inc. | Method for forming a raised vertical transistor |
DE59608588D1 (de) * | 1995-09-26 | 2002-02-21 | Infineon Technologies Ag | Selbstverstärkende DRAM-Speicherzellenanordnung |
US5937296A (en) * | 1996-12-20 | 1999-08-10 | Siemens Aktiengesellschaft | Memory cell that includes a vertical transistor and a trench capacitor |
US5892707A (en) * | 1997-04-25 | 1999-04-06 | Micron Technology, Inc. | Memory array having a digit line buried in an isolation region and method for forming same |
DE59814170D1 (de) * | 1997-12-17 | 2008-04-03 | Qimonda Ag | Speicherzellenanordnung und Verfahren zu deren Herstellung |
EP0945901A1 (de) * | 1998-03-23 | 1999-09-29 | Siemens Aktiengesellschaft | DRAM-Zellenanordnung mit vertikalen Transistoren und Verfahren zu deren Herstellung |
-
1999
- 1999-03-12 DE DE19911148A patent/DE19911148C1/de not_active Expired - Lifetime
-
2000
- 2000-03-01 TW TW089103596A patent/TW461086B/zh not_active IP Right Cessation
- 2000-03-10 CN CNB008049491A patent/CN1150612C/zh not_active Expired - Fee Related
- 2000-03-10 EP EP00916811A patent/EP1161770A1/de not_active Withdrawn
- 2000-03-10 WO PCT/DE2000/000756 patent/WO2000055904A1/de active IP Right Grant
- 2000-03-10 KR KR10-2001-7011606A patent/KR100403442B1/ko not_active IP Right Cessation
- 2000-03-10 JP JP2000606049A patent/JP3786836B2/ja not_active Expired - Fee Related
-
2001
- 2001-09-12 US US09/951,243 patent/US6504200B2/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02159058A (ja) * | 1988-12-13 | 1990-06-19 | Fujitsu Ltd | 半導体メモリセル |
US5828094A (en) * | 1994-03-17 | 1998-10-27 | Samsung Electronics Co., Ltd. | Memory cell structure having a vertically arranged transistors and capacitors |
US5497017A (en) * | 1995-01-26 | 1996-03-05 | Micron Technology, Inc. | Dynamic random access memory array having a cross-point layout, tungsten digit lines buried in the substrate, and vertical access transistors |
US5736761A (en) * | 1995-05-24 | 1998-04-07 | Siemens Aktiengesellschaft | DRAM cell arrangement and method for its manufacture |
EP0899790A2 (de) * | 1997-08-27 | 1999-03-03 | Siemens Aktiengesellschaft | DRAM-Zellanordnung und Verfahren zu deren Herstellung |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 014, no. 414 (E - 0975) 7 September 1990 (1990-09-07) * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6627940B1 (en) | 1999-03-30 | 2003-09-30 | Infineon Technologies Ag | Memory cell arrangement |
US6646299B2 (en) | 1999-10-19 | 2003-11-11 | Infineon Technologies Ag | Integrated circuit configuration having at least two capacitors and method for manufacturing an integrated circuit configuration |
Also Published As
Publication number | Publication date |
---|---|
TW461086B (en) | 2001-10-21 |
KR100403442B1 (ko) | 2003-10-30 |
US20020079527A1 (en) | 2002-06-27 |
JP2002539642A (ja) | 2002-11-19 |
DE19911148C1 (de) | 2000-05-18 |
JP3786836B2 (ja) | 2006-06-14 |
KR20010104379A (ko) | 2001-11-24 |
US6504200B2 (en) | 2003-01-07 |
EP1161770A1 (de) | 2001-12-12 |
CN1150612C (zh) | 2004-05-19 |
CN1343371A (zh) | 2002-04-03 |
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