WO2000007242A1 - Leiterbahnrahmen, platine mit leiterbahnrahmen und verfahren zur herstellung eines leiterbahnrahmens - Google Patents
Leiterbahnrahmen, platine mit leiterbahnrahmen und verfahren zur herstellung eines leiterbahnrahmens Download PDFInfo
- Publication number
- WO2000007242A1 WO2000007242A1 PCT/DE1999/002072 DE9902072W WO0007242A1 WO 2000007242 A1 WO2000007242 A1 WO 2000007242A1 DE 9902072 W DE9902072 W DE 9902072W WO 0007242 A1 WO0007242 A1 WO 0007242A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- frame
- integrated electronic
- electronic circuit
- signal line
- conductor track
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the invention relates to a conductor track frame, a circuit board with at least one conductor track frame and a method for producing a conductor track frame.
- fast memory modules high performance DRAMs
- fast memory modules have particularly high requirements for the dissipation of thermal power loss, the guarantee of electrical function and high numbers of connections (pins, IOs).
- parasitic inductances, capacitances and resistances must be minimized.
- the object of the invention is to integrate integrated electronic circuits, in particular with memory cell arrangements, into a conductor structure with the least possible design effort.
- this object is achieved by a conductor * track frame with at least one integrated electronic circuit, wherein the integrated electronic circuit in the region of a main surface of the conductor frame is, with at least one signal line, wherein between the integrated electronic circuit and the signal line at least in sections at least an electrically insulating plate and an electrically conductive, grounded plate.
- the signal lines connect functional elements of the integrated electronic circuit to one or more suitable connections.
- Parasitic electrical parameters such as inductance, capacitance and resistance of the geometrical structure are minimized by the structure of the conductor track frame according to the invention. Very good electrical and signaling reliability is achieved even with integrated electronic circuits with high switching speeds, in particular with fast memory chips (high performance DRAMs) with particularly high requirements for ensuring the electrical function.
- a particularly good use of space can be achieved if the signal line runs at least in sections within the conductor track frame.
- a further improvement in space utilization is achieved in that at least one integrated electronic circuit is located on each of the two main surfaces of the conductor track frame.
- the electrical reliability is further increased in that the signal line runs parallel to the integrated electronic circuit, at least in sections.
- the conductor track frame In order to avoid thermal stress on the integrated electronic circuit, it is expedient for the conductor track frame to be provided with at least one heat distributor.
- the conductor track frame is used as a cooling vane for the integrated electronic circuits.
- the heat distributor is in thermal contact with a heat conductor which at least partially penetrates the conductor track frame.
- the invention further provides for a circuit board which is equipped with integrated electronic circuits to be designed in such a way that it contains at least one interconnect frame according to the invention.
- a particularly good use of space can be achieved in that it has a main circuit board and that the conductor track frame is arranged essentially perpendicular to the main circuit board.
- the main circuit board contains a multiplicity of conductor track frames and that the conductor track frames are arranged essentially parallel and / or coplanar to one another.
- the invention further relates to a method for producing a conductor track frame provided with at least one integrated electronic circuit, the conductor track frame being provided with at least one signal line and the integrated electronic circuit being applied such that there is between the integrated electronic circuit and the signal line at least in sections at least one electrically insulating plate and an electrically conductive, grounded plate.
- the so-called crosstalk can be avoided by the signal lines being electrically shielded by two adjacent earth lines.
- FIG. 1 shows a cross section through a conductor track frame perpendicular to the plane in which the integrated electronic circuits are located
- FIG. 2 shows a cross section through the conductor track frame shown in FIG. 1,
- FIG. 3 shows a cross section through the conductor track frame shown in FIGS. 1 and 2 through the sectional plane III-III,
- Fig. 4 shows a cross section through an expedient arrangement of conductor tracks in a further conductor track frame according to the invention.
- the integrated electronic circuits 4, 5 have thermal vias 6, only one of which is shown enlarged in the figure as an example.
- the thermal vias 6 are contact holes that are connected to are filled with a thermally conductive material. They are produced in the same way as electrically conductive contact points 8, but are not electrically connected, but only serve to conduct heat.
- the integrated electronic circuits are connected via the electrically conductive contact points 8 to signal lines 9, which end in a connecting element 7 of the conductor track frame 1.
- connection element 7 In its edge region, the conductor track frame 1 opens into the connection element 7, which can be inserted into a circuit board arrangement or into another suitable slot.
- connection of the signal lines 9 from the integrated electronic circuits 4, 5 to the connection element 7 takes place via the electrically conductive contact points 8, which are embedded in the insulation layers 2, 2 ⁇ , 3, 3 ⁇ .
- interposer I Such an arrangement of insulation layers 2, 2 ⁇ , 3, 3 and signal lines 9 embedded in them is referred to as interposer I.
- a connection via insulation layers 2, 2 ⁇ , 3, 3 ⁇ is particularly useful if the integrated electronic circuits 4, 5 are in the form of configured chips (existing packages).
- a connection via a further, preferably branched, conductor strip frame, which is preferably attached to a further insulating plate, is particularly suitable for non-configured electronic circuits.
- the signal lines 9 are laid, for example, in accordance with the embodiment shown in FIG. 2.
- the signal lines 9 each extend from a signal connection S in the area of the connection element 7 to a contact point 8.
- the signal connections S are each located between two basic potential connections G. All signal lines 9 preferably have the same length and are connected by suitable wiring (interposer routing). connected several times to the integrated electronic circuits 4, 5, so that a wide bus system is formed.
- Heat distributors 12, 13 penetrate the entire area of the conductor track frame 1.
- FIG. 3 shows a cross section through the conductor track frame shown in FIGS. 1 and 2 through the section plane III-III in the area of the signal connections S.
- the signal connections S which open into the signal lines 9 at a higher level, not shown, are through two basic potential connections G and electrically shielded by the two electrically conductive, grounded base plates 14, 14.
- the signal lines 9 are ⁇ by the base plates 14, 14 and two adjacent ground lines which are arranged in extension of the basic potential terminals G, electrically shields off.
- the ground lines, which are arranged in the extension of the basic potential connections G preferably have the same lengths as the signal lines, so that the electrical shielding of the signal lines 9 is further improved.
- FIG. 4 shows a cross section through an alternative, equally expedient, arrangement of conductor tracks in a further conductor track frame according to the invention.
- signal lines 16, 18, 22, 24 starting from signal connections S are each connected by two adjacent earth lines 15, 17, 19, starting from a basic potential connection G. 23 electrically shielded.
- the signal lines 16, 18, 22,, 24 open into contact points 26, 28, 32, 34.
- the earth lines 15, 17, 19, 23 can laterally form a vertical line formed from the contact points 26, 28, 32, 34 in a common - Unite the line, preferably the earth line 15.
- the four contact points 26, 28, 32, 34 form a contact matrix with corresponding further contact points, a contact matrix with 4 x 4 contact points being shown in the present case.
- Thermal vias 40, 41, 42 enable good heat dissipation.
- the arrangement of the conductor tracks shown is particularly advantageous because it combines good electrical shielding of the signal lines 16, 18, 22, 24 with high heat dissipation.
- other arrangements of the signal lines, the ground lines, the contact points or the thermal vias are also used to design other embodiments of the interconnect frames according to the invention.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99945911A EP1104584A1 (de) | 1998-07-28 | 1999-07-05 | Leiterbahnrahmen, platine mit leiterbahnrahmen und verfahren zur herstellung eines leiterbahnrahmens |
US09/771,912 US6798045B2 (en) | 1998-07-28 | 2001-01-29 | Lead frame, circuit board with lead frame, and method for producing the lead frame |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19833930.5 | 1998-07-28 | ||
DE19833930 | 1998-07-28 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/771,912 Continuation US6798045B2 (en) | 1998-07-28 | 2001-01-29 | Lead frame, circuit board with lead frame, and method for producing the lead frame |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000007242A1 true WO2000007242A1 (de) | 2000-02-10 |
Family
ID=7875571
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1999/002072 WO2000007242A1 (de) | 1998-07-28 | 1999-07-05 | Leiterbahnrahmen, platine mit leiterbahnrahmen und verfahren zur herstellung eines leiterbahnrahmens |
Country Status (3)
Country | Link |
---|---|
US (1) | US6798045B2 (de) |
EP (1) | EP1104584A1 (de) |
WO (1) | WO2000007242A1 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105047642B (zh) * | 2015-08-12 | 2024-01-19 | 深圳市槟城电子股份有限公司 | 一种端口防护电路集成封装件 |
CN105047640B (zh) * | 2015-08-12 | 2023-06-06 | 深圳市槟城电子股份有限公司 | 一种端口防护电路集成封装件及其制造方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1984001470A1 (en) * | 1982-10-05 | 1984-04-12 | Mayo Foundation | Leadless chip carrier for logic components |
US5220491A (en) * | 1990-04-09 | 1993-06-15 | Hitachi, Ltd. | High packing density module board and electronic device having such module board |
US5288949A (en) * | 1992-02-03 | 1994-02-22 | Ncr Corporation | Connection system for integrated circuits which reduces cross-talk |
US5523622A (en) * | 1992-11-24 | 1996-06-04 | Hitachi, Ltd. | Semiconductor integrated device having parallel signal lines |
US5686764A (en) * | 1996-03-20 | 1997-11-11 | Lsi Logic Corporation | Flip chip package with reduced number of package layers |
WO1997050123A1 (en) * | 1996-06-24 | 1997-12-31 | Intel Corporation | A power-ground plane for a c4 flip-chip substrate |
EP0849793A2 (de) * | 1996-12-18 | 1998-06-24 | Texas Instruments Incorporated | Verbesserungen für oder in Beziehung auf integrierte Schaltungspackungen |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6486545A (en) | 1987-09-28 | 1989-03-31 | Mitsubishi Electric Corp | Lead frame |
US5260601A (en) | 1988-03-14 | 1993-11-09 | Texas Instruments Incorporated | Edge-mounted, surface-mount package for semiconductor integrated circuit devices |
US5025306A (en) | 1988-08-09 | 1991-06-18 | Texas Instruments Incorporated | Assembly of semiconductor chips |
DE3838486A1 (de) | 1988-11-12 | 1990-05-17 | Standard Elektrik Lorenz Ag | Schaltungstraeger fuer hochfrequenzleitungen |
US4965654A (en) | 1989-10-30 | 1990-10-23 | International Business Machines Corporation | Semiconductor package with ground plane |
US5045914A (en) | 1989-12-26 | 1991-09-03 | Motorola, Inc. | Plastic pad array electronic AC device |
JP2501266B2 (ja) * | 1991-11-15 | 1996-05-29 | 株式会社東芝 | 半導体モジュ―ル |
JPH0677392A (ja) | 1992-06-05 | 1994-03-18 | Fujitsu Ltd | 半導体装置とその製造方法 |
US5731633A (en) * | 1992-09-16 | 1998-03-24 | Gary W. Hamilton | Thin multichip module |
US5283717A (en) * | 1992-12-04 | 1994-02-01 | Sgs-Thomson Microelectronics, Inc. | Circuit assembly having interposer lead frame |
US5363550A (en) * | 1992-12-23 | 1994-11-15 | International Business Machines Corporation | Method of Fabricating a micro-coaxial wiring structure |
JP3253765B2 (ja) * | 1993-06-25 | 2002-02-04 | 富士通株式会社 | 半導体装置 |
KR100253028B1 (ko) | 1994-11-10 | 2000-04-15 | 로데릭 더블류 루이스 | 반도체장치용다층리드프레임 |
JP3400877B2 (ja) * | 1994-12-14 | 2003-04-28 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JPH09213868A (ja) | 1996-01-30 | 1997-08-15 | Nec Corp | マイクロ波半導体集積回路用リ−ドフレ−ム |
JPH10144965A (ja) * | 1996-11-11 | 1998-05-29 | Hamamatsu Photonics Kk | 光半導体装置及びその製造方法 |
US6137164A (en) * | 1998-03-16 | 2000-10-24 | Texas Instruments Incorporated | Thin stacked integrated circuit device |
-
1999
- 1999-07-05 WO PCT/DE1999/002072 patent/WO2000007242A1/de active Application Filing
- 1999-07-05 EP EP99945911A patent/EP1104584A1/de not_active Withdrawn
-
2001
- 2001-01-29 US US09/771,912 patent/US6798045B2/en not_active Expired - Lifetime
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1984001470A1 (en) * | 1982-10-05 | 1984-04-12 | Mayo Foundation | Leadless chip carrier for logic components |
US5220491A (en) * | 1990-04-09 | 1993-06-15 | Hitachi, Ltd. | High packing density module board and electronic device having such module board |
US5288949A (en) * | 1992-02-03 | 1994-02-22 | Ncr Corporation | Connection system for integrated circuits which reduces cross-talk |
US5523622A (en) * | 1992-11-24 | 1996-06-04 | Hitachi, Ltd. | Semiconductor integrated device having parallel signal lines |
US5686764A (en) * | 1996-03-20 | 1997-11-11 | Lsi Logic Corporation | Flip chip package with reduced number of package layers |
WO1997050123A1 (en) * | 1996-06-24 | 1997-12-31 | Intel Corporation | A power-ground plane for a c4 flip-chip substrate |
EP0849793A2 (de) * | 1996-12-18 | 1998-06-24 | Texas Instruments Incorporated | Verbesserungen für oder in Beziehung auf integrierte Schaltungspackungen |
Also Published As
Publication number | Publication date |
---|---|
US6798045B2 (en) | 2004-09-28 |
US20010019172A1 (en) | 2001-09-06 |
EP1104584A1 (de) | 2001-06-06 |
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