Classifications

• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B29/10—Inorganic compounds or compositions
  • C30B29/14—Phosphates
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C16/4401—Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C16/4401—Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber
  • C23C16/4408—Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber by purging residual gases from the reaction chamber or gas lines
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
  • C30B25/02—Epitaxial-layer growth
  • C30B25/08—Reaction chambers; Selection of materials therefor
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S414/00—Material or article handling
  • Y10S414/135—Associated with semiconductor wafer handling
  • Y10S414/139—Associated with semiconductor wafer handling including wafer charging or discharging means for vacuum chamber

Definitions

• the invention relates to the process of forming films of material on semiconductor wafers through the use of carrier gases within a reactor chamber.
• the present invention relates to the epitaxial deposition of specific materials onto a silicon wafer and to a system and method for reducing or eliminating particulate matter and the resulting particle-related defects on the finished wafer.
• the wafers are loaded in one or multiple load locks and transported through a wafer handling chamber to a reactor, where the actual material is deposited onto the semiconductor wafers by means of gases or vapors.
• the gas in the load lock, wafer handling chamber and reactor must be as particle-free as possible in order to reduce the number of defects on the semiconductor wafer surface.
• Epitaxial depositions in general and silicon epitaxial deposition in particular are integral parts of VLSI processing, especially for the advanced bipolar, NMOS and CMOS technologies, since many of the components of the individual transistors and devices are formed in an epitaxial layer.
• the parent substrate is substantially defect-free (the introduction of substantially defect-free silicon wafer starting material in the mid 1970 's offered this possibility)
• the growth of defect-free epitaxial layers requires the elimination of particles on the surface of the parent substrate wafer.
• the elimination or substantial decrease in unwanted particles and the associated achievement of very low particle-related defect densities are accomplished by extensive runs and wafer inspection resulting in very low wafer yields.
• particles may enter the semiconductor manufacturing equipment by other means, such as when semiconductor wafers are put into a load lock, during equipment maintenance or through some other indirect source. Particles generated during the process are removed by the laminar flow of the purge gas. The particles may be transported to the inner surfaces of the equipment and adhere thereon. If particles are present in the gas, or suddenly released from the inner surfaces of the equipment, the particles may be transported to the surface of the semiconductor wafer and cause defects. Undesirable particles including the particles that are to be deposited on the semiconductor wafer during the manufacturing process can be attracted to, deposited and retained on the inner surfaces of the semiconductor manufacturing equipment.
• Capillary force is reduced by the reduction of moisture in the equipment.
• the moisture is reduced by use of construction materials with low moisture permeability and the use of a particle and moisture free gas flow through the equipment.
• a dry particle-free gas purge such as dry nitrogen evaporates moisture and purges particles that are only being retained by the capillary force on the inner surfaces of the equipment.
• U.S. Patent Number 5,373,806 to Logar is an example of an attempt to solve the problem of retained particles.
• Logar electrostatic charges are reduced by heating the substrate to a specific temperature lower than the processing temperature prior to production deposition by the use of a radiant source of energy. This is an extra step that must be taken in the manufacturing process, increasing production time and cost.
• particles are removed from the inner surface of the wafer handling chamber and the load locks by purging the wafer handling chamber with a particle-free gas.
• the semiconductor wafers are transported through the wafer handling chamber and load locks.
• a laminar flow of gas is provided so that particles can be picked up and carried with the purge gas through an exhaust outlet located within the wafer handling chamber and load locks.
• the gas flow becomes turbulent, causing particles to be stirred up and transported to the surface of any semiconductor wafer that happen to be in the wafer handling chamber.
• Another problem with the existing system occurs when a gate valve that isolates the wafer handling chamber from the load lock or processing chamber is opened. If there is a pressure difference between the two chamber, the gas flow in one chamber is diverted to the second chamber, which results in turbulence within the both chambers. Because the single stage back pressure regulators do not completely open, particles, vapors and gases back stream from the exhaust outlet into both chambers.
• a method and apparatus for reducing particles in an epitaxial reactor used in processing of semiconductor wafers includes an enclosure for processing the semiconductor wafers.
• a purge gas delivery system removes undesirable particles from the enclosure. Included in the system is a pilot operated back pressure regulator for regulating the exhaust of the purge gas from the enclosure.
• the system also includes an ionizing source for conditioning the purge gas that is integrally connected to the purge gas delivery system.
• the pilot operated back pressure regulator includes a dome regulator for adjusting purge gas flow, a valve for actuating the dome regulator, and a pressure regulator for delivering the pilot gas to the dome regulator.
• the enclosure has a wafer handling chamber and a processing chamber.
• a robotic arm located within the wafer handling chamber has a Bernoulli wand end affecter that lifts and transporting the semiconductor wafers between the wafer handling chamber and processing chamber.
• the wafer handling chamber is connected by an isolating gate valve to the processing chamber.
• the isolating gate valve is opened and closed according to a procedure that reduces the disturbances when there is a pressure difference between the wafer handling chamber and the processing chamber.
• Figure 1 is a diagram of the semiconductor manufacturing equipment, showing gas purge lines that are associated with the load locks and the wafer handling chamber according to the teachings of the present invention
• Figure 2 is a perspective view of the semiconductor manufacturing equipment illustrating the load locks, the wafer handling chamber and an epitaxial reactor;
• Figure 3 is a schematic of an isolation valve assembly in the preferred embodiment of the present invention.
• Figure 4 is a schematic diagram illustrating the dome loaded regulator circuit in a preferred embodiment of the present invention.
• FIG. 5 is a schematic diagram of the pilot operated back pressure regulator in the preferred embodiment of the present invention
• Figure 6 is a cross sectional side view of the pilot operated back pressure regulator in the preferred embodiment of the present invention.
• DETAILED DESCRIPTION OF EMBODIMENTS Referring to figures 1 and 2 wherein figure 1 includes a diagram of a piece of semiconductor manufacturing equipment (an epitaxial reactor 10) , illustrating a gas purge system 12 that is associated with a wafer transport chamber that includes load locks 14 and 15, and a wafer handling chamber 16.
• the epitaxial reactor 10 is partitioned into the wafer handling chamber 16, load locks 14 and 15, and a process chamber 20 that is isolated from the load locks 14 and 15 and the wafer handling chamber 16 by isolation gate valve 18.
• the load locks 14 and 15 and wafer handling chamber 16 Prior to processing any semiconductor wafers, the load locks 14 and 15 and wafer handling chamber 16 are purged by purge gas from the gas source 22 that includes a control system. This purge gas flows from the source 22 through the pipes 24 and 26 into the load locks 14 and 15 and wafer handling chamber 16.
• cassettes of semiconductor wafers are placed in the load locks 14 and 15 through load lock portals 32 and 34.
• the load lock portals 32 and 34 are closed to isolate the wafers from the surrounding atmosphere.
• the load locks are purged by the purge gas from the gas source 22.
• the purge gas such as dry nitrogen flows through the pipes 24 into the load locks 14 and 15.
• the purge gas purges out oxygen, moisture and undesirable particles that enters the load locks 14 and 15 when the load lock portals 32 and 34 are opened to receive the wafer cassettes.
• the load locks 14 and 15 are opened to the wafer handling chamber by the lowering of the cassette by an elevator 8 which breaks the air tight seal typically located at edge 6, and the wafers are transported sequentially from the cassettes to the process chamber 20 by a transfer arm 29 that has a Bernoulli wan 36 end affecter. While the wafers are transported through the wafer handling chamber 16, the wafer handling chamber 16 is purged by a gas from the gas source 22.
• the purge gas from the gas source is made slightly conductive by passing it through ionizer 21a which is connected to load lock 14, ionizer 21b which is connected to load lock 15, ionizer 21c which is connected to the wafer handling chamber 16 and ionizer 21d which is connected to the Bernoulli wand 36 by a flexible tube 30 that is connected to the robotic arm 29.
• the gas is the same as the purge gas.
• the ionizers 21a, 21b, 21c, and 21d reduces or removes electrostatic forces from inside the epitaxial reactor 10.
• the slightly conductive purge gas can discharge any particles from the wafers or inner surfaces of the chamber subject to the purge .
• the ionizers may be devices such as Model 2201 ss (alpha particle ionizer manufactured by NRD, Inc. of Grand Island, New York or preferably an electronic ionizer, such as the model 4210 manufactured by Ion Systems of Berkeley, California.
• the purge gas flows, under pressure, through the ionizers 21a, 21b, 22c, and 21d.
• the flow rate of the nitrogen purge gas is measured at 15 standard liters per minute (slm) , as a Low Flow rate and at 50 slm per minute as a High Flow rate.
• the flow rate is dependent on the volume of chambers and is selected to be as high as possible without creating turbulence.
• a flow rate of 15 slm is common because a higher rate of flow causes turbulence and may stir up and drive particles into suspension with the purge gas.
• a High Flow rate is only used during maintenance mode when there are no wafers in the epitaxial reactor 10, because it stirs up particles and facilitates the cleaning of the equipment.
• the purge gas is slightly conductive, any static in the equipment is reduced or eliminated so that the particles are not attracted to surfaces by electrostatic force, such as the semiconductor wafers (not shown) .
• the ionizers 21a, 21 b, 21c and 21d are located as close to the load locks 14 and 15 and the wafer handling chamber 16 as possible. Additionally, there should be no bends in the piping that connects the ionizers 21a 21 b, 21c and 21d to the load locks 14 and 15 and the wafer handling chamber 16.
• the transfer arm 29 is used to move the wafers from the load lock 14 or 15 into the process chamber 20 for wafer processing.
• the transfer arm 29, including a low ingestion Bernoulli wand 36, is within the wafer handling chamber 16.
• the Bernoulli wand 36 picks up the semiconductor wafers one at a time from the cassettes (not shown) in one of the load locks 14 and 15.
• Each wafer is then transported through an open isolation gate valve 18 to a susceptor 38 within the process chamber 20.
• the Bernoulli wand 36 is used to reduce particle accumulation within the epitaxial reactor 10 by avoiding contact with the top and bottom surfaces of the wafers.
• the Bernoulli wand 36 utilizes a novel non-spiking gas system and uses nitrogen gas, through wand gas supply line 28. However, when the Bernoulli wand 36 picks up a wafer and releases it onto the susceptor 38 in the process chamber 20, the resulting impulse of gas released into the wafer handling chamber 16 causes a pressure spike and a resulting turbulence of gas in the wafer handling chamber 16. Any turbulence causes particles that are present within the wafer handling chamber 16 to be disturbed and lifted into suspension in the purging gas. The particles thus can be transported to a wafer surface, however the presence of a damper 44 that dampers the pressure spikes generated from the operation of the Bernoulli wand 36 and prevents the generating of a pressure spike and the resulting turbulence.
• the gas flow is turned off to drop a wafer at its destination, the remaining gas is vented into the wafer handling chamber 16.
• This sudden burst of gas flow causes a sudden pressure rise.
• the damper 44 and orifice 46 is utilized to reduce the pressure spike in the wafer handling chamber 16.
• the dome regulator 90 is shut off and, simultaneously, valve 95 is opened to release the remaining gas flow into the damper 44 and flow resisting orifice 46.
• the size of the damper 44 and the size of the orifice 46 are properly sized, the gas flow increase is gradually released into the wafer handling chamber 16 to compensate for the sudden burst.
• the orifice 46 is sized to provide a tuning mechanism for regulating pressure bursts into the wafer handling chamber 16.
• the damper 44 and orifice 46 is used in conjunction with the back pressure regulator 40 that is located in the exhaust line 42 that is connected to the wafer handling chamber 16.
• the back pressure regulator 40 maintains a constant pressure in the wafer handling chamber 16 and the load locks 14 and 15.
• the valve 41 is opened so that the gas load locks 14 and 15 can be vented.
• the isolation gate valve includes a valve assembly 80 that is constructed to allow the isolation gate valve 18 to open only a minute amount to allow the pressure to equalize between the wafer handling chamber 16 and the process chamber 20.
• Figure 3 is a schematic of the isolation gate valve assembly 80.
• the isolation gate valve assembly 80 includes an actuator 82 which is mechanically connected with the isolation gate valve 18, enabling the isolation gate valve 18 to open. Additionally, the isolation gate valve 18 is mechanically connected with a second actuator 84, that actuates the initial opening of the isolation gate valve 18 in a controlled way, allowing the equalization of pressure between the wafer handling chamber 16 and the process chamber 20. The actuator 84 also may control the final closing of the isolation gate valve in a controlled manner.
• This isolation gate valve assembly 80 provides a multi- speed isolation gate valve, which can reduce or eliminate gas flow bursts which occur in the initial stage of prior art isolation gate valves.
• the isolation gate valve 18 is opened and the Bernoulli wand 36 retrieves the processed wafer and loads the wafer into a cassette within one of the load locks (14 or 15) . After all of the wafers have been processed, the cassette located within the load lock is removed through one of the portals (32 or 34) .
• a dome loaded regulator circuit 90 is utilized to feed gas into the semiconductor manufacturing equipment.
• Figure 4 is a schematic diagram illustrating the dome loaded regulator circuit 90 and includes a dome loaded regulator 92, a valve 94, a pressure regulator 96 and a needle valve 98.
• the gas flow into the equipment is increased incrementally by the dome loaded regulator 92 which is pneumatically actuated by the valve 94, which controls a restricted gas flow.
• the gas flow originates from the pressure regulator 96.
• the needle valve 98 controls the amount of restriction of the gas flow.
• the needle valve 98 may be a plurality of needle valves and check valves, to regulate different ramp- up and ramp-down flow rates of the purge gas.
• FIG. 5 is a schematic diagram of the pilot operated back pressure regulator 40 in the preferred embodiment of the present invention.
• the pilot operated back pressure regulator 40 includes a pneumatically actuated throttle valve 50 which is actuated by a pressure relay system 52.
• the pressure relay system 52 is normally a 22:1 ratio pressure relay that adjusts the opening of the pneumatically actuated throttle valve 50 from the sensed pressure across the throttle valve 50 and conduits 101 and 102.
• the pilot operated back pressure regulator 40 also includes a variable load springs 54 and a throttle valve actuator 56. Additionally, the pilot operated back pressure regulator 40 includes a throttle valve input 58.
• FIG. 6 is a cross sectional side view of the pilot operated back pressure regulator 40 in the preferred embodiment of the present invention.
• the pilot operated back pressure regulator 40 uses the pneumatically actuated throttle valve 50 to regulated the pressure.
• the pilot operated back pressure regulator 40 includes the pressure relay system 52, which is a 22:1 pressure relay in the preferred embodiment, and the pneumatically actuated throttle valve 50.
• the pressure relay system 52 includes a large piston 58 which drives a small pressure reducing regulator 60.
• a high pressure pilot supply 80 PSI in the preferred embodiment
• the variable load spring 54 opens the small pressure regulator 60 .
• the opening of the small pressure regulator 60 allows a dynamic flow from a chamber 64 to enter a chamber 68 via a passage 66.
• the dynamic flow then flows through a bleed passage 70 to a passage 72.
• the dynamic flow is exhausted through an output 74 of the pilot operated back pressure regulator 40.
• This dynamic flow creates a bias pressure on the throttle valve actuator 56 at a level just below the pressure required to drive the throttle valve 50 open.
• the size of the bleed passage 70, chamber 68, and a chamber 57 determines the response time and pressure differential necessary to drive the throttle valve 50 open. The smaller the bleed passage 70 and chamber 57, the faster the response of the pilot operated back pressure regulator 40.
• a small increase in pressure at an input 76 for the pilot operated back pressure regulator 40 is transmitted, via a channel 78, to the top of the large piston 58 through the passage 66 driving the small regulator 60 to a higher pressure that is multiplied by the ratio of the pressure relay.
• This increases the pressure at the top of throttle valve actuator 56 and drives the throttle valve 50 open, relieving the pressure at the input 76 of the pilot operated back pressure regulator 40 and thereby regulating the pressure at the throttle valve input 58.

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• Chemical & Material Sciences (AREA)
• Engineering & Computer Science (AREA)
• Materials Engineering (AREA)
• Metallurgy (AREA)
• Organic Chemistry (AREA)
• General Chemical & Material Sciences (AREA)
• Chemical Kinetics & Catalysis (AREA)
• Mechanical Engineering (AREA)
• Crystallography & Structural Chemistry (AREA)
• Inorganic Chemistry (AREA)
• Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
• Chemical Vapour Deposition (AREA)

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Citations (6)

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• 1998
  • 1998-07-10 US US09/113,934 patent/US6161311A/en not_active Expired - Lifetime
• 1999
  • 1999-06-30 EP EP99932209A patent/EP1097251B1/en not_active Expired - Lifetime
  • 1999-06-30 WO PCT/US1999/015070 patent/WO2000003056A1/en not_active Ceased
  • 1999-06-30 KR KR1020017000387A patent/KR20010071820A/ko not_active Abandoned
  • 1999-06-30 DE DE69940064T patent/DE69940064D1/de not_active Expired - Fee Related
  • 1999-06-30 JP JP2000559270A patent/JP2002520832A/ja active Pending
  • 1999-06-30 EP EP08006163A patent/EP1956112A3/en not_active Withdrawn
  • 1999-07-08 TW TW088111373A patent/TW445304B/zh not_active IP Right Cessation
• 2000
  • 2000-12-01 US US09/727,736 patent/US6550158B2/en not_active Expired - Lifetime

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