WO1999049491A1 - Source d'electrons a emission de champ - Google Patents

Source d'electrons a emission de champ Download PDF

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Publication number
WO1999049491A1
WO1999049491A1 PCT/JP1999/001423 JP9901423W WO9949491A1 WO 1999049491 A1 WO1999049491 A1 WO 1999049491A1 JP 9901423 W JP9901423 W JP 9901423W WO 9949491 A1 WO9949491 A1 WO 9949491A1
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WO
WIPO (PCT)
Prior art keywords
field emission
electron source
field
effect transistor
cathode
Prior art date
Application number
PCT/JP1999/001423
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English (en)
Japanese (ja)
Inventor
Keisuke Koga
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to EP99909285A priority Critical patent/EP1071109A4/fr
Priority to US09/622,734 priority patent/US6818915B1/en
Priority to KR1020007010567A priority patent/KR20010034645A/ko
Publication of WO1999049491A1 publication Critical patent/WO1999049491A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02—Main electrodes
    • H01J1/30—Cold cathodes, e.g. field-emissive cathode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02—Main electrodes
    • H01J1/30—Cold cathodes, e.g. field-emissive cathode
    • H01J1/304—Field-emissive cathodes
    • H01J1/3042—Field-emissive cathodes microengineered, e.g. Spindt-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00—Electrodes common to discharge tubes
    • H01J2201/30—Cold cathodes
    • H01J2201/319—Circuit elements associated with the emitters by direct integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2329/00—Electron emission display panels, e.g. field emission display panels

Definitions

  • the present invention relates to a cold cathode electron source that is expected to be applied to electron beam pumped lasers, flat display devices, ultrahigh-speed micro vacuum devices, etc., and in particular, can realize integration and low voltage.
  • Field of the Invention The present invention relates to a field emission electron source for various semiconductor applications and a method for manufacturing the same. Background art
  • micro-cold cathode structure is expected to have a flat electron emission characteristic and a high current density, and is therefore expected to be particularly useful as an electron source for next-generation flat displays.
  • the operating temperature is wider than that of liquid crystal display systems such as TFT-LCD, it is desired to put it into practical use as an in-vehicle environment-resistant display.
  • This first conventional example uses the principle that the amount of emitter electron current emitted from a field emission cathode device is made constant using the ⁇ current characteristics of a field effect transistor (FET).
  • FET field effect transistor
  • (a) is a cross-sectional view of a part of a silicon substrate on which one field emission cathode device and an FET are configured
  • (b) is a circuit showing an electric equivalent circuit of a portion including the field emission cathode device. It is a block diagram.
  • 810 is a field effect transistor (FET)
  • 801 is a p-type silicon substrate
  • 802 is the first source of FET8I0 :! Mold layer
  • 803 is a conical emitter of the field emission cathode device
  • 804 ' is an insulating layer (Si 2 layer) portion of 804 that functions as a gate insulating layer of the field emission cathode device
  • 805 is a gate layer of the field emission cathode device.
  • Reference numeral 806 denotes a second ⁇ -type layer serving as a drain of the FET 810
  • reference numeral 807 denotes a source electrode of the FET 810
  • reference numeral 808 denotes a gate electrode of the FET 8L0
  • reference numeral 809 denotes an anode of the field emission cathode device
  • reference numeral 81 1 denotes a source.
  • Reference numeral 812 denotes a gate voltage source (voltage value Vg)
  • 813 denotes an anode voltage source (voltage value Va)
  • 814 denotes a gate-source control voltage source (voltage value Vgs).
  • the field emission cathode device consists of a triode with an anode (A) 809, a gate (G) 805, and an emitter (E) 803.
  • the drain-source path of the FET 810 and the source resistance 811 are connected in series between the two.
  • the anode (A) 809 is connected to an anode voltage source 813 for generating an anode voltage Va
  • the gate (G) 805 is connected to a gate voltage source 8 for generating a fixed gate voltage Vg.
  • the gate 808 is connected to a gate-source control voltage source 814 that generates a variable gate-source control voltage Vgs.
  • a predetermined anode voltage Va is applied to the anode 809, a predetermined gate voltage Vg is applied to the gate 805, and a required value is applied to the gate 808 of the FET 810.
  • the gate-source voltage V gs is applied, the emitter electron current is emitted from the emitter 803 without heating the emitter 803.
  • the emitter current of the field emission cathode device is Variable gate-source control applied to the gate 808 of the FET 810 connected to the emitter 803 instead of being controlled by the fixed gate voltage V g applied to the gate 805 It is controlled by the voltage V gs. That is, the FET 810 operates in the constant current region by appropriately setting the gate-source control voltage V gs applied to the gate 808.
  • the amount of electron flow radiation emitted from the emitter in the electric field is determined by the characteristics of the FET that is connected in series with this emitter and has the function of supplying emitted electrons. Therefore, by optimally designing the FET, the operating conditions of the FET and the field emission electron flow can be designed in advance. In particular, by performing field emission in the FET saturation operation region, it is free from the instability factors of the emitter itself, and as a result, an extremely stable and precisely controlled field emission electron flow can be obtained.
  • FIG. 9 shows, as a second conventional example, a configuration example of an FED of such a system disclosed in Japanese Patent Application Laid-Open No. H10-74473.
  • a second gate electrode (focusing electrode) is formed for each emitter, and a negative potential is applied to this gate electrode relative to the first gate electrode (pull-out gate electrode). By giving, it converges the electrons emitted from the emitter.
  • reference numeral 91 denotes an insulating layer
  • an insulating layer 93 is further provided on the gate electrode (lead electrode) 92
  • a second gate electrode (circular opening) is provided thereon.
  • (Converging electrode) 94 is provided.
  • a second gate electrode (focusing electrode) 94 is provided so as to surround each emitter 95. This second By setting the potential of the gate electrode (focusing electrode) 94 to a lower potential than that of the first gate electrode (extraction gate electrode) 92, the electrons emitted from the emitter are subjected to the lens effect of the focusing effect, and The trajectory of the beam is converged.
  • the field emission type cathode device of the first conventional example can control the field emission electron flow rate stably for a short period of time, but cannot secure stability for a long period of time depending on operating conditions.
  • the field emission display of the second conventional example has the function of converging the electron beam, but has the disadvantage that the amount of electrons emitted from the emitter is reduced. Disclosure of the invention
  • the present invention has been made to solve the above-mentioned problems, and its objects are to achieve the following (1) to obtain a field emission type electron source structure which realizes a reliable operation required for a next-generation display; 2) To obtain a field emission electron source structure that achieves high-density and stable operation for higher definition, and (3) A field emission electron source that has a beam focusing function that enables higher definition Obtaining the structure.
  • An apparatus provided according to an aspect of the present invention includes: a lead electrode formed on a p-type silicon substrate via an insulating film and having an opening at a position corresponding to a cathode formation region; A field emission electron source including: a cathode formed on the substrate at a position corresponding to the opening of the extraction electrode; and a p-type silicon substrate corresponding to the field emission electron source. And an n-channel field effect transistor portion formed in the field effect transistor, wherein the field emission electron source portion is formed in a drain region of the field effect transistor portion, and is applied to a gate electrode of the field effect transistor portion.
  • a field emission type electron source device in which a field emission current from the field emission electron source section is controlled by a control voltage, wherein the drain region includes at least two types of diodes having different impurity concentrations, and At least one of the two types has a low impurity concentration.
  • a The effect transistor is formed at the end of the drain region in contact with the channel region of the transistor region.
  • the drain region may include at least two types of n-type impurity elements having different thermal diffusion rates in a silicon substrate as the impurity elements.
  • the drain region contains, as impurity elements, a phosphorus element having a high thermal diffusion rate in a silicon substrate and an arsenic element having a low thermal diffusion rate in a silicon substrate.
  • a device provided with an extraction electrode formed on a P-type silicon substrate via an insulating film and having an opening at a position corresponding to a cathode formation region; a field emission electron source including: a cathode formed on a p-type silicon substrate at a position corresponding to the opening of the extraction electrode; and a P-type corresponding to the field emission electron source.
  • An n-channel field-effect transistor formed on a silicon substrate, wherein the field-emission electron source is formed in a drain region of the field-effect transistor, and is applied to a gate electrode of the field-effect transistor.
  • a field emission current from the field emission electron source section, wherein the gate electrode of the field effect transistor section has at least two types of different voltages. Gate width And a portion of the gate electrode is arranged to cover an end of the drain region.
  • a device provided with a lead electrode formed on a p-type silicon substrate via a first insulating film and having an opening at a position corresponding to a cathode formation region;
  • a field emission electron source including: a cathode formed on the p-type silicon substrate at a position corresponding to the opening of the extraction electrode; and a p-type corresponding to the field emission electron source.
  • An electron source device wherein a gate insulating film formed between the gate electrode of the field effect transistor and the P-type silicon substrate is provided between the extraction electrode and the P-type silicon substrate. And a structure in which the gate insulating film is buried with the first insulating film.
  • the gate insulating film may be composed of a silicon thermal oxide film formed in a sharpening thermal oxidation process for sharpening the tip of the cathode portion of the field emission electron source.
  • a device provided with an extraction electrode formed on a p-type silicon substrate via an insulating film and having an opening at a position corresponding to a cathode formation region;
  • a field emission electron source including: a cathode portion formed on the type silicon substrate at a position corresponding to the opening of the extraction electrode; and a p-type silicon substrate corresponding to the field emission electron source portion.
  • an n-channel field-effect transistor formed thereon.
  • the field-emission electron source is formed in a drain region of the field-effect transistor, and is applied to a gate electrode of the field-effect transistor.
  • a field emission type electron source device in which a field emission current from the field emission electron source unit is controlled by a control voltage, wherein the field emission type electron source device is made of the same material as the gate electrode of the field effect transistor unit. Further comprising a shield electrode disposed so as to cover the region not covered Te cowpea to the gate electrode within the channel region of the field effect transistor unit.
  • the shield electrode is maintained at the same potential as the p-type silicon substrate, and has a function of blocking the influence of an external electric field not caused by the gate electrode on the channel region.
  • a device provided with an extraction electrode formed on a p-type silicon substrate via an insulating film and having an opening at a position corresponding to a cathode formation region;
  • a field emission electron source including: a cathode formed on the p-type silicon substrate at a position corresponding to the opening of the extraction electrode; and a p-type corresponding to the field emission electron source.
  • N-channel field-effect transistor formed on silicon substrate And a field-emission electron source section formed in a drain region of the field-effect transistor section, wherein the field-emission electron source section is formed by a control voltage applied to a gate electrode of the field-effect transistor section.
  • a field emission type electron source device in which a field emission current from a portion is controlled, wherein the drain region of the field effect transistor portion is surrounded by the source region inside the source region of the field effect transistor portion. And the gate electrode of the field effect transistor portion has a planarly symmetric arrangement with respect to the cathode portion of the field emission electron source portion.
  • the drain region is made of a p-type conductive layer.
  • an outer peripheral portion in contact with the channel region of the target field effect transistor portion and an inner peripheral portion of the source region may have a circular shape formed concentrically.
  • At least a part of the gate electrode formed between the source region and the drain region may have an arc-shaped symmetric shape.
  • V g For example, between the j-th voltage e X applied to the extraction electrode of the field emission electron source unit and the second voltage V g applied to the gate electrode of the field-effect transistor unit, V g There is a relationship V e X.
  • the drain end where the high electric field strength is concentrated is formed of a well with a low impurity concentration.
  • extreme electric field concentration can be reduced, and the reliability of the device operation is improved. be able to.
  • two or more ⁇ -type wells utilizing the difference in thermal diffusion rate can be used. , Can be easily formed.
  • ⁇ - ⁇ ell having a low impurity concentration and ⁇ + ⁇ ell having a high impurity concentration can be easily formed. .
  • a channel gate electrode is provided in a field emission type electron source device.
  • the drain current flowing from the source to the drain is diffused in the drain end region, and as a result, the current density can be reduced.
  • a field effect transistor which requires a thick insulating film for an extraction electrode requiring high voltage application and a thin insulating film for low voltage driving. Functionally separated from the insulating film. Further, by adopting a structure in which the gate insulating film is buried with the insulating film, a multilayer wiring can be formed, and a wiring for driving the matrix can be easily formed. If the gate insulating film is composed of a silicon thermal oxide film formed in the step of sharpening thermal oxidation of the cathode of the field emission electron source, the use of a precisely controlled high-quality thermal oxide film enables High reliability is obtained and FET control can be performed with high accuracy.
  • the influence of the external electric field can be suppressed by covering the channel region of the field effect transistor with the shield electrode.
  • the wiring process can be simplified by being formed of the same material as the gate electrode.
  • the shield electrode is held at the same potential as the p-type silicon substrate and a function that blocks the influence of the electric field from an external electric field other than the gate electrode is added, the shield electrode will be held at the same potential as the p-type silicon substrate potential Therefore, the shield function from the external electric field can be more reliably exhibited.
  • an electrode arrangement such as a gate electrode symmetrically in a plane centering on the drain, thereby facilitating the electron focusing operation.
  • the step of introducing impurities into the drain region by ion implantation is simplified, the manufacturing cost can be reduced, and at the same time, the occurrence of cathode shape variations due to ion implantation into the cathode can be suppressed.
  • the outer periphery of the drain and the inner periphery of the source which are in contact with the channel region of the field effect transistor, have circular shapes formed concentrically, so that carriers can be injected from the source region to the drain region. Are uniformed, and good transistor characteristics are obtained.
  • At least a part of the gate electrode for controlling the channel region formed between the source region and the drain region has a symmetrical arc shape, so that the electrode shape for convergence is centered on the drain. Therefore, the convergence operation can be performed more uniformly.
  • FIG. 1 (a) and 1 (b) are a cross-sectional view and a plan view, respectively, schematically showing the configuration of a field emission type electron source device according to the first embodiment of the present invention
  • FIG. 2A and 2B show a cross-sectional structure taken along line I- ⁇ .
  • FIGS. 2A and 2B are a cross-sectional view and a plan view, respectively, schematically showing the configuration of a field emission type electron source device according to the second embodiment of the present invention.
  • 2A and 2B show a cross-sectional structure taken along line I-I.
  • FIG. 3 is a cross-sectional view schematically illustrating a configuration of a field emission electron source device according to a third embodiment of the present invention.
  • FIG. 4 (a) and 4 (b) are a cross-sectional view and a plan view, respectively, schematically showing the configuration of a field emission type electron source device according to a fourth embodiment of the present invention, and FIG. 2A and 2B show a cross-sectional structure taken along line I-I.
  • FIGS. 5 (a) and (b) show the electric field emission in the fifth embodiment of the present invention, respectively.
  • 5A and 5B are a cross-sectional view and a plan view, respectively, schematically illustrating the configuration of the exiting electron source device.
  • FIG. 5A shows a cross-sectional structure taken along line I-I of FIG.
  • 6 (a) and 6 (b) are a cross-sectional view and a plan view, respectively, schematically showing the configuration of a field emission type electron source device according to the sixth embodiment of the present invention.
  • 2A and 2B show a cross-sectional structure taken along line I-I.
  • FIGS. 7A and 7B are a cross-sectional view and a plan view schematically showing the configuration of a field emission type electron source device according to a seventh embodiment of the present invention, respectively. 2A and 2B show a cross-sectional structure taken along line I-I.
  • FIG. 8A is a cross-sectional view schematically showing the configuration of a conventional field emission electron source device
  • FIG. 8B is an equivalent circuit diagram of the configuration of FIG.
  • Fig. 9 is a cross-sectional view schematically showing the configuration of a conventional field emission electron source device.
  • This drain potential mainly depends on the channel resistance, which is a design parameter of the FET, and the dynamic It depends on the product of the operating conditions and the field emission electron flow rate.
  • the field emission electron flow is set according to the required brightness of the FED panel, but is usually set to about 1 A per pixel.
  • the drain potential rises to several volts or more when a micron-level element size is assumed using a normal FET with a power supply voltage of about 3.5 V.
  • the drain potential becomes higher.
  • the inventors of the present application have confirmed that the increase in the drain potential as described above causes some problems in the operation of the field emission electron source device. One of them is the hot electron phenomenon.
  • the FET When the FET is operated for a long time under the condition that the potential between the source and the drain exceeds the band gap energy of silicon, which is 1.1 leV, the electrons accelerated by the electric field between the source and the drain make the gate insulating film near the drain. The phenomenon of being injected into the interface occurs. The injected electrons stay in the vicinity of the gate insulating film to cause an action to cancel the gate voltage, or form an interface state at the gate insulating film interface to generate a leak current through the gate insulating film. Causes various FET performance degradation. Furthermore, the present inventors have found that an impact ionization phenomenon is a factor that causes a change in FET characteristics.
  • the problem of an increase in the field emission electron flow due to the external electric field also hinders stable emission current control, and is a major obstacle to commercialization.
  • the electric potential applied to the second gate electrode 94 strikes the electric field intensity at the tip of the emitter generated by the first gate electrode 92.
  • the electric field intensity is weakened and the amount of electron emission decreases, and in this conventional configuration, there is a trade-off relationship between the convergence effect and the amount of electron emission. > It was confirmed that there was an essential problem that sufficient convergence could not be achieved while maintaining the amount of emission.
  • 1A and 1B are a cross-sectional view and a plan view, respectively, of the field emission type electron source device according to the present embodiment.
  • FIG. 1A is a cross-sectional view taken along the line I-I of (b). 1 shows a cross-sectional structure.
  • 1 is a p-type silicon substrate
  • 2 is a first ⁇ -type semiconductor conductive portion serving as a source region of an element operating as a field effect transistor (FET)
  • 3 is an impurity serving as a drain region of the FET.
  • High-concentration second n-type semiconductor conductive part 4 is third n-type semiconductor conductive part with low impurity concentration to be the drain region of FET, and 5 operates as a field-emission electron source in the form of a tower with a circular cross section
  • a cathode 6 is an insulating layer made of a silicon oxide film functioning as a field emission electron source and a gate insulating film of an FET
  • 7 is an extraction electrode for operating as a field emission electron source
  • 8 is a FET channel region.
  • a gate electrode 9 for control, and 9 is a source electrode for F ⁇ . As shown in FIGS.
  • a part of one main surface of a p-type silicon substrate I
  • the first n-type semiconductor conductive part 2 and the second ⁇ -type semiconductor conductive part 3 serving as a drain are formed at a certain distance from each other.
  • a third ⁇ -type semiconductor conductive portion 4 having a low impurity concentration is selectively formed.
  • the ⁇ -type impurity element for forming the second ⁇ -type semiconductor conductive part 3 phosphorus having a high thermal diffusion rate in the silicon substrate is used to form the third ⁇ -type semiconductor conductive part 4.
  • arsenic which has a low thermal diffusion rate in a silicon substrate
  • This is based on the principle that the impurity profile changes due to the difference in thermal diffusion rate in the heat treatment process after the ion implantation of two or more different elements is optimally implanted using the same mask. is there. In other words, elements with high thermal diffusion rates (such as phosphorus) redistribute deeper and more widely than elements with low thermal diffusion rates (such as arsenic) than the impurity profile at the beginning of implantation.
  • an evening cathode 5 having a circular cross section is formed on the surface of the second ⁇ -type semiconductor conductive portion 3 serving as a drain.
  • the tip of the tower-shaped cathode 5 made of silicon has a tip microstructure on the order of nanometers formed by a sharpening process utilizing thermal oxidation.
  • a conductive lead electrode 7 is formed near the cathode 5 via an insulating film 6 made of a silicon oxide film having a circular opening.
  • the channel region of the FET located between the first ⁇ -type semiconductor conductive portion 2 serving as the source and the second ⁇ -type semiconductor conductive portion 3 and the third ⁇ -type semiconductor conductive portion 4 serving as the drain has an insulating film.
  • a gate electrode 8 for FET is formed on 6. Further, a source electrode 9 is formed on the ⁇ -type semiconductor conductive portion 2 of the source via a contact window.
  • the p-type silicon substrate 1 and the first n-type semiconductor conductive portion 2 serving as a source region are grounded, and a positive voltage Vex is applied to the extraction electrode 7. Furthermore, when a predetermined voltage Vg is applied to the gate electrode 8 of the FET, the channel region below the gate electrode 8 becomes open, and the conditions for injecting electron carriers from the source to the drain are established. Under this condition, a positive voltage Vex is applied to the extraction electrode 7. In a field-emission electron source having a submicron-order gate opening diameter and a nanometer-order cathode tip, electrons begin to be field-emitted from the tip of the cathode 5 when a voltage of usually several tens of volts is applied.
  • the emitted electrons travel while being accelerated toward an anode plate arranged opposite to the p-type silicon substrate 1 not shown in FIGS. 1 (a) and 1 (b).
  • the amount of the electron current emitted from the cathode 5 is not controlled by the fixed gate voltage VeX applied to the extraction electrode 7 but to the gate electrode 8 of the FET connected to the cathode 5. It is controlled by the applied variable gate-source control voltage Vg. That is, the FET operates in the constant current region by appropriately selecting the gate-source control voltage Vg applied to the gate electrode 8.
  • the amount of electron flow radiation emitted from the cathode 5 in the electric field is determined by the characteristics of the FET connected in series to the emitter and having a function of supplying emitted electrons. Therefore, by optimally designing the FET, it becomes possible to design the operating conditions of the FET and the field emission electron flow in advance. In particular, by performing field emission in the saturation operation region of the FET, an extremely stable and precisely controlled field emission electron flow can be obtained without being affected by the instability factors of the emitter itself.
  • the feature of the drain structure of the present embodiment is that a plurality of drain-well structures (so-called twin-well structures) having two or more impurity concentrations are employed.
  • the field-emitted electron flow is basically supplied from the source of the FET, but the channel region between the source and drain has a high resistance.
  • the drain potential rises according to the amount of current.
  • the drain potential of a FET formed by a submicron process and operating at a power supply voltage of about 3.5 volts can reach several volts or more, assuming a channel current of about 1 microampere.
  • the electrons injected from the source are accelerated and injected into the drain by the electric field in the channel generated by the drain potential.
  • the channel electric field is not generated uniformly in the channel region, but concentrates near the drain on the silicon substrate surface.
  • electrons traveling in the channel become high energy electrons (hot electrons), particularly under the influence of the high electric field strength near the drain.
  • the hot electrons have higher energy as the electric field intensity near the drain increases, and can cause various problems, such as an increase in the threshold voltage for controlling the ONZO FF of the FET and a decrease in the drain current. There is.
  • the drain has a high impurity concentration, so that the pn junction at the drain end is close to an ablative junction.
  • the pn junction at the drain end is reduced.
  • the electric field concentration at the drain end can be reduced.
  • the shape of the cathode 5 is the same as the shape of the cathode 5 has been described.
  • a similar effect can be obtained with a conventional conical cathode shape.
  • the material of the cathode 5 an example in which a p-type silicon substrate is formed by processing is used. Similar effects can be obtained by using a material (a high melting point metal material such as molybdenum or tungsten) or a carbon-based material (such as diamond, graphite, or diamond-like carbon). (Second embodiment)
  • 2A and 2B are a cross-sectional view and a plan view, respectively, of the field emission type electron source device according to the present embodiment.
  • FIG. 2A shows a cross-sectional structure taken along line I-I of FIG.
  • 1 is a p-type silicon substrate
  • 2 is a first n-type semiconductor conductive portion serving as a source region of an element operating as a field effect transistor (FET)
  • 3 is a drain region of the FET.
  • the second n-type semiconductor conductive part with high impurity concentration, 4 is the third n-type semiconductor conductive part with low impurity concentration that will be the drain region of the FET, and 5 operates as a tower-shaped field emission electron source with a circular cross section 6 is an insulating layer composed of a silicon oxide film functioning as a gate insulating film of a field emission type electron source and FET, 7 is an extraction electrode for operating as a field emission type electron source, and 8 T ⁇ FET A T-shaped gate electrode for controlling the channel region, and 9 is a source electrode for the F-channel.
  • a part of one main surface of the p-type silicon substrate 1 includes an n-type A semiconductor conductive portion 2 and an n-type semiconductor conductive portion 3 serving as a drain are formed, and an n-type semiconductor conductive portion 4 having a low impurity concentration is selectively located at a position surrounding the periphery of the n-type semiconductor conductive portion 3. Is formed.
  • a tower-shaped cathode 5 having a circular cross section is formed on the surface of the ⁇ -type semiconductor conductive portion 3 serving as a drain.
  • a tip microstructure on the order of nanometers is formed by a sharpening process using thermal oxidation. Have been.
  • a conductive lead electrode 7 is formed near the cathode 5 via an insulating film 6 made of a silicon oxide film having a circular opening.
  • the FET channel region located between the source n-type semiconductor conductive part 2 and the drain n-type semiconductor conductive part 3 and the n-type semiconductor conductive part 4 has an FET gate region on the insulating film 6. Eight single electrodes are formed.
  • the gate electrode 8 has two or more types of plural gate widths (a so-called ⁇ -shaped gate structure). Part of the gate electrode 8 is arranged so as to cover the surface of the ⁇ -type semiconductor conductive portion 4 having a low impurity concentration and located in the channel region of the FET and located at the drain end. Further, a source electrode 9 is formed on the ⁇ -type semiconductor conductive portion 2 of the source via a contact window.
  • the ⁇ ⁇ ⁇ ⁇ -type silicon substrate 1 and the ⁇ -type semiconductor conductive part 2 of the source are grounded, and a positive voltage V e X is applied to the extraction electrode 7. Furthermore, when a predetermined voltage Vg is applied to the eight gate electrodes of the FET, the channel region below the gate electrode 8T is opened, and the conditions for injecting electron carriers from the source to the drain are established. Under this condition, when a positive voltage Vex is applied to the extraction electrode 7, a field emission electron source having a submicron-order gate opening diameter and a nanometer-order cathode tip usually has several tens of volts. Electrons begin to be field-emitted from the tip of the cathode 5 by the voltage application. The emitted electrons travel while being accelerated toward the anode plate facing the p-type silicon substrate 1 not shown in FIG.
  • the amount of electron current emitted from the cathode 7 is not controlled by the fixed gate voltage V e applied to the extraction electrode 7, but rather by the gate electrode of the FET connected to the cathode 5.
  • the amount of electron flow emitted from the cathode 5 in the field emission is determined by the characteristics of the FET connected in series to the emitter and having a function of supplying the emitted electrons. Therefore, by optimally designing the FET, it becomes possible to design the operating conditions of the FET and the field emission electron flow in advance. In particular, by performing field emission in the saturation operation region of the FET, an extremely stable and precisely controlled field emission electron flow can be obtained as a result, without being affected by the instability factors of the emitter itself. .
  • the function of the gate electrode 8T having two or more different gate widths and arranged so as to cover the drain end region will be described in detail.
  • the field-emitted electron stream is basically supplied from a source of FET. Since the channel region between the source and drain has a high resistance, the drain potential increases in accordance with the amount of electron current emission, that is, the amount of channel current. Experiments have confirmed that, for a FET formed by a submicron process and operating at a power supply voltage of about 3.5 volts, the drain potential reaches several volts or more, assuming a channel current of about 1 microampere. I have. The electrons injected from the source are accelerated by the electric field in the channel generated by the drain potential and injected into the drain.
  • the channel electric field is not generated uniformly in the channel region, but concentrates near the drain on the silicon substrate surface.
  • electrons traveling in the channel become high energy electrons (hot electrons), particularly under the influence of the high electric field strength near the drain.
  • the hot electrons have higher energy as the electric field strength near the drain increases, which can cause various problems such as an increase in the threshold voltage for ON / OFF control of the FET and a decrease in the drain current.
  • the gate electrode 8T (so-called T-shaped gate structure) described in the present embodiment so as to cover the drain end, the above-mentioned hot electron phenomenon can be suppressed.
  • the gate electrode structure having a plurality of widths (so-called T-shaped gate structure) described in the present embodiment is also effective in terms of design flexibility.
  • the amount of drain current flowing through the FET channel depends on the width (W) and length (L) parameters (W / L) of the gate electrode. Since the width of the drain is inevitably determined by the degree of integration and arrangement of the entire device, it is often difficult to freely design the width (W) of the gate electrode. However, by adopting the T-shaped gate structure described in this embodiment, after arranging a part of the gate so as to cover the drain end region, the remaining gate part has an element of width (W) and (L). Since the dimensions can be freely set, the degree of freedom in device design is improved.
  • the shape of the cathode 5 is a tower shape has been described, but the same effect can be obtained with a conventional conical cathode shape.
  • a conventional metal material a refractory metal material such as molybdenum or tungsten
  • a carbon-based material a diamond, a graph, or the like
  • FIG. 3 is a cross-sectional view of the field emission type electron source device according to the present embodiment.
  • 31 is a p-type silicon substrate
  • 32 is a first n-type semiconductor conductive portion serving as a source region of an element operating as a field effect transistor (FET)
  • 33 is a drain of the FET.
  • 34 represents a third n-type semiconductor conductive portion having a low impurity concentration serving as a drain region of FET.
  • 35 represents a tower-shaped portion having a circular cross section.
  • a cathode that operates as a field emission electron source 36 is a lower insulating layer made of a silicon oxide film that functions as a gate insulating film of a FET, and 37 is a silicon oxide film that functions as a lead electrode for a field emission electron source.
  • An upper insulating layer, 38 is an extraction electrode for operating as a field emission type electron source, 39 is a gate electrode for controlling the channel region of the FET, and 40 is a source electrode for the gate electrode.
  • an n-type semiconductor conductive portion 32 serving as a FET source is provided on a part of one main surface of the p-type silicon substrate 31.
  • An n-type semiconductor conductive portion 33 serving as a drain is formed, and an ri-type semiconductor conductive portion 34 having a low impurity concentration is selectively formed at a position surrounding the periphery of the n-type semiconductor conductive portion 33. I have.
  • an evening cathode 35 having a circular cross section is formed on the surface of the n-type semiconductor conductive portion 33 serving as a drain.
  • a tip microstructure on the order of nanometers is formed by a sharpening process utilizing thermal oxidation.
  • a conductive extraction electrode 3 is formed via a lower insulating film 36 and an upper insulating film 37 made of a silicon oxide film having a circular opening. 8 are formed.
  • the channel region of the FET located between the source n-type semiconductor conductive part 32 and the drain n-type semiconductor conductive part 33 and the n-type semiconductor conductive part 34 is formed on the lower insulating film 36.
  • an FET gate electrode 39 having a configuration embedded in the upper insulating film 37 is formed.
  • a thermal oxide film formed by a sharpening process of the cathode 35 is used as the lower insulating film 36.
  • a source electrode 40 is formed on the source n-type semiconductor conductive portion 32 through a contact window.
  • the p-type silicon substrate 31 and the first n-type semiconductor conductive portion 32 are grounded, and a positive voltage V e X is applied to the bow
  • a positive voltage V e X is applied to the extraction electrode 38.
  • a field emission electron source in which a gate opening diameter on the order of submicrons and a cathode tip on the order of nanometers are formed, electrons start to be emitted from the tip of the cathode 35 by applying a voltage of usually several tens of volts. The emitted electrons travel while being accelerated toward the anode plate, which is not shown in FIG. 3, and is opposed to the p-type silicon substrate 31.
  • the amount of the electron current emitted from the cathode 35 is not controlled by the fixed gate voltage Vex applied to the extraction electrode 38, but rather by the gain of the FET connected to the cathode 35. It is controlled by the variable gate-source control voltage V g applied to the gate electrode 39. In other words, the FET operates in the constant current region by appropriately selecting the gate-source control voltage Vg applied to the gate electrode 39.
  • the amount of electron flow radiation emitted from the cathode 35 in the electric field is determined by the characteristics of the FET connected in series with the emitter and having a function of supplying the emitted electrons. It is determined.
  • the lower insulating film 36 of the present embodiment mainly functions as a gate insulating film for FET.
  • the threshold voltage at which F ET is changed to ⁇ N Z ⁇ F F depends strongly on the thickness of the gate insulating film.
  • a thin film with the highest possible quality is required.
  • the extraction electrode 38 for the field emission electron source a laminated film of the lower insulating film 36 and the upper insulating film 37 is used.
  • a thick insulating film is required in consideration of the withstand voltage.
  • ONZO control of a field emission electron source is performed by applying a voltage to the extraction electrode 38, a thicker insulating film is advantageous in terms of operating speed and power consumption. .
  • the gate insulating film for the FET and the insulating film for the field emission electron source can be independently designed, and the high performance of the device can be achieved. Easy to make.
  • the gate electrode 39 has a structure buried by the upper insulating film 37,
  • a multilayer wiring structure generally used in SI can be easily obtained.
  • the use of multi-layer wiring makes it possible to easily realize a matrix drive wiring structure in the x and y directions, which is impossible with single-layer wiring.
  • the shape of the cathode 35 is a tower shape has been described.
  • a similar effect can be obtained with a conventional conical cathode shape.
  • the material of the cathode 35 an example in which a p-type silicon substrate is formed by processing is used. Similar effects can be obtained by using a material (a refractory metal material such as molybdenum or tungsten) or a carbon-based material (such as diamond, graphite, or diamond-like carbon). (Fourth embodiment)
  • FIGS. 4 (a) and 4 (b) are a cross-sectional view and a plan view, respectively, of the field emission type electron source device according to the present embodiment
  • FIG. 4 (a) is a view taken along the line I-I of (b). 1 shows a cross-sectional structure.
  • 41 is a p-type silicon substrate
  • 42 is a second n-type semiconductor conductive portion serving as a source region of an element that operates as a field effect transistor (FET)
  • 43 is a drain region of the FET.
  • the second n-type semiconductor conductive portion having a high impurity concentration is 44 and the third n-type semiconductor conductive portion 44 having a low impurity concentration is a drain region of the FET.
  • 45 is a tower-shaped field emission electron source having a circular cross section.
  • the operating cathode, 46 is a lower insulating layer made of a silicon oxide film functioning as a gate insulating film of a FET, 47 is an upper insulating layer made of a silicon oxide film functioning as a lead electrode for a field emission electron source, and 48 is An extraction electrode for operating as a field emission electron source, 49 is a gate electrode for controlling the FET channel region, 50 is a shield electrode from an external electric field in the FET channel region, and 51 is a source for FET. With electrodes That. As shown in FIGS. 4 (a) and 4 (b), in the field emission type electron source device according to the present embodiment, a part of one main surface of the p-type silicon substrate 41 has an n-type as a source of the FET.
  • a semiconductor conductive portion 42 and an ⁇ -type semiconductor conductive portion 43 serving as a drain are formed, and a ⁇ -type semiconductor conductive portion 44 having a low impurity concentration is selectively formed around the ⁇ -type semiconductor conductive portion 43.
  • a ⁇ -type semiconductor conductive portion 44 having a low impurity concentration is selectively formed around the ⁇ -type semiconductor conductive portion 43.
  • an evening cathode 45 having a circular cross section is formed on the surface of the ⁇ -type semiconductor conductive portion 43 serving as a drain.
  • the tip of the tower-shaped cathode 45 made of silicon is a sharpening process using thermal oxidation.
  • the nanometer-order microstructure on the order of nanometers is formed by the metal.
  • a conductive lead electrode 48 is formed near the cathode 45 via a lower insulating film 46 and an upper insulating film 47 made of a silicon oxide film having a circular opening.
  • the channel region of the FET located between the source n-type semiconductor conductive part 42 and the drain n-type semiconductor conductive part 43 and the n-type semiconductor conductive part 44 is formed on the lower insulating film 46.
  • a gate electrode 49 for the F gate having a configuration embedded in the upper insulating film 47 is formed.
  • a shield electrode 50 made of the same material as the gate electrode 49 is disposed so as to cover a region where the gate electrode 49 for the FET is not formed in the channel region of F ⁇ . .
  • As the lower insulating film 46 a thermal oxide film formed by a sharpening process of the cathode 45 is used.
  • a source electrode 51 is formed on the ⁇ -type semiconductor conductive portion 42 of the source through a contact window.
  • the ⁇ -type silicon substrate 41, the ⁇ -type semiconductor conductive portion 42 of the source, and the shield electrode 50 are grounded, and a positive voltage V eX is applied to the extraction electrode 48. Furthermore, when a predetermined voltage Vg is applied to the gate electrode 49 of the FET, the channel region below the gate electrode 49 becomes open, and the conditions for injecting electron carriers from the source to the drain are established. Under this condition, a positive voltage V e X is applied to the extraction electrode 48. In a field emission electron source with a gate opening diameter on the order of sub-microns and a cathode tip on the order of nanometers, electrons begin to be field-emitted from the tip of the cathode 45 by applying a voltage of several tens of volts. .
  • the emitted electrons travel while being accelerated toward an anode plate (not shown) facing the p-type silicon substrate 41.
  • the amount of electron current emitted from the cathode 45 is not controlled by the fixed gate voltage VcX applied to the extraction electrode 48, but rather by the gate electrode of the FET connected to the cathode 45. It is controlled by the variable gate-source control voltage V applied to 49. That is, the FET has a gate source applied to its gate electrode 49.
  • the amount of the electron current emitted from the cathode 45 in the electric field is determined by the characteristics of the FET connected in series with the emitter and having a function of supplying the emitted electrons. . Therefore, by optimally designing the FET, the operating conditions of the FET and the field emission electron flow can be designed in advance. In particular, by performing field emission in the saturation operation region of the FET, an extremely stable and precisely controlled field emission electron flow can be obtained as a result without being affected by the instability factors of the emitter itself.
  • the electrons field-emitted from the cathode 45 collide with residual gas molecules in the vacuum atmosphere to ionize them. This ionization strongly depends on the degree of vacuum to be operated, the type and concentration of residual molecules, the external electric field strength for accelerating electrons, or the density of the field-emitted electrons (emission current).
  • the positively charged ions (cations) receive an electric field in the direction opposite to the electrons, are guided toward the substrate, and are irradiated on the silicon substrate 41.
  • the element structure described in the present embodiment has the outermost surface covered with the upper insulating film 47. When the cations continue to be irradiated to the upper insulating film 47 at a certain density or higher, a positive charge is gradually charged on the upper insulating film 47, and a positive charge voltage is generated.
  • the seal connected to the substrate and the conductive potential is used.
  • the gate electrode 50 By covering the channel region with the gate electrode 50, even if a charge voltage is generated, the effect of the electric field on the channel region can be prevented by the shield effect, so that a change in FET characteristics can be prevented.
  • the shape of the cathode 45 is a tower shape has been described, but the same effect can be obtained with a conventional conical cathode shape.
  • the material of the cathode 45 an example in which a p-type silicon substrate is formed by processing is used.
  • a conventional metal material a high melting point metal material such as molybdenum and tungsten
  • a carbon-based material diamond, graph The same effect can be obtained by using iron or diamond-like force.
  • FIGS. 5 (a) and 5 (b) are a cross-sectional view and a plan view, respectively, of the field emission type electron source device according to the present embodiment
  • FIG. 5 (a) is a sectional view taken along line II of FIG. 1 shows a cross-sectional structure.
  • reference numeral 51 denotes a p-type silicon substrate; 52, a second n-type semiconductor conductive portion serving as a source region of an element operating as a field effect transistor (FET); 53, a drain region of the FET; A second n-type semiconductor conductive part having a high impurity concentration, 54 is a cathode operating as a field-emission electron source having a circular cross section, and 55 is a silicon oxide functioning mainly as a gate insulating film of a FET.
  • the first insulating layer 56 made of a film mainly functions as an insulating film for an extraction electrode of a field emission electron source.
  • a second insulating layer made of a silicon oxide film, 57 is a gate electrode for controlling a channel region for FET, 58 is a source electrode for FET, and 59 is a lead electrode for cathode.
  • a part of one of the main surfaces of the p-type silicon substrate 51 is used as a source of the FET.
  • a second n-type semiconductor conductive part 53 serving as a drain is formed, and the second n-type semiconductor conductive part 53 is formed of a first ⁇ -type semiconductor conductive part 52.
  • At least a part of the surface of the channel region of the FET located between the first n-type semiconductor conductive portion 52 serving as a source and the second n-type semiconductor conductive portion 53 serving as a drain includes A gate electrode 57 having a structure embedded between the first insulating layer 55 and the second insulating layer 56 is formed. Further, a source electrode 58 is formed on the first n-type semiconductor conductive portion 52 via a contact window.
  • a negative cathode 54 On the surface of the second n-type semiconductor conductive portion 53 serving as a drain, a negative cathode 54 having a circular cross section is formed. At the tip of an evening cathode 54 made of silicon, a tip microstructure on the order of nanometers is formed by a sharpening process utilizing thermal oxidation. Further, around the cathode 54, an extraction electrode 59 having a certain aperture and for applying an electric field for electron emission is formed on the second insulating layer 56.
  • the P-type silicon substrate 51 and the first n-type semiconductor conductive portion 52 serving as a source region are grounded, and a positive voltage V eX is applied to the extraction electrode 59. Furthermore, when a predetermined voltage Vg is applied to the gate electrode 57 of the FET, the channel region below the gate electrode 57 becomes open, and the conditions for injecting electron carriers from the source to the drain are established. Under this condition, a positive voltage Vex is applied to the extraction electrode 59. This In this case, the conditions for applying V ex and V g are set so as to satisfy the relationship of V g ⁇ V e X.
  • electrons start to be field-emitted from the tip of the cathode 54 by applying a voltage of several tens of volts.
  • the emitted electrons travel while being accelerated toward an anode plate (not shown) facing the p-type silicon substrate 51.
  • the amount of electron current emitted from the cathode 54 is not controlled by the fixed gate voltage V e X applied to the extraction electrode 59, but rather by the gate electrode of the FET connected to the cathode 54. It is controlled by the variable gate-source control voltage Vg applied to 57.
  • the FET operates in the constant current region by appropriately selecting the gate-source control voltage V.g applied to the gate electrode 57.
  • the amount of electron flow radiation emitted from the cathode 54 in the electric field is determined by the characteristics of the FET having the function of supplying the emitted electrons connected in series with the emitter. . Therefore, by optimally designing the FET, the operating conditions of the FET and the field emission electron flow can be designed in advance. In particular, by performing field emission in the saturation operation region of the FET, an extremely stable and precisely controlled field emission electron flow can be obtained as a result without being affected by the instability factors of the emitter itself.
  • the feature of the drain structure of this embodiment is that it has an island structure whose outer peripheral portion is surrounded by a source region and a channel region. Further, the gate electrode for controlling the operation of the FET is symmetrically arranged around the cathode of the field emission electron source. By adopting this arrangement, carriers can be evenly injected from the source region to the drain region.
  • the drain of the normal structure injects carriers from a part of the boundary adjacent to the channel region.
  • the injected carriers diffuse in the drain and emit field emission charges. It will reach the cathode of the source part. Therefore, it is expected that the carrier concentration varies depending on the position of the drain. On the other hand, in the configuration of the present embodiment described above, such a problem does not occur.
  • the cathode is arranged symmetrically with respect to the drain where the cathode is formed. Since the carrier is injected uniformly and symmetrically through the gate electrode, variations in electron emission within the drain are also suppressed.
  • the extraction electrode of the present invention is effective not only for controlling the amount of emitted electrons, but also for controlling the beam trajectory of emitted electrons.
  • the gate electrode 57 that brings a convergence effect is formed as a wiring buried between the first: I insulating layer 55 and the second insulating layer 56, and is located below the lead electrode 59. Is formed. Due to this relative arrangement, even when a voltage lower than Vex is applied to Vg, the gate electrode 57 does not affect the cathode 54.
  • the configuration of the present invention can have a sufficient convergence function while maintaining the amount of electron emission.
  • the shape of the cathode 54 is a tower shape has been described, but a similar effect can be obtained with a conventional conical cathode shape.
  • a conventional metal material a refractory metal material such as molybdenum and tungsten
  • a carbon-based material diamond, graphite
  • diamond-like carbon a conventional metal material (a refractory metal material such as molybdenum and tungsten) or a carbon-based material (diamond, graphite) , Or diamond-like carbon) can obtain the same effect.
  • FIGS. 6 (a) and 6 (b) are a cross-sectional view and a plan view, respectively, of the field emission type electron source device according to the present embodiment.
  • FIG. 6 (a) is a cross-sectional view taken along line I-I of (b). 1 shows a cross-sectional structure.
  • 61 is a p-type silicon substrate
  • 62 is an n-type semiconductor conductive portion serving as a source region of an element operating as a field effect transistor (FET)
  • 63 is a tower shape having a circular cross section.
  • the cathode operates as a field emission type electron source
  • 64 is the first insulating layer mainly composed of a silicon oxide film that functions as the gate insulating film of the FET
  • 65 is the insulation for the extraction electrode of the field emission type electron source.
  • 66 is a gate electrode for controlling the channel region for the FE
  • 67 is a source electrode for FET
  • 68 is a source electrode for cathode.
  • a part of one main surface of the p-type silicon substrate 61 has a first source serving as an FET source.
  • An electron source section is formed, and the field emission electron source section is arranged inside so as to be surrounded by the n-type semiconductor conductive section 62.
  • the gate electrode 66 for controlling the voltage is formed as a wiring embedded between the first insulating layer 64 and the second insulating layer 65 in a symmetrical arrangement with respect to the cathode 63. I have. Further, a source electrode 67 is formed on the source n-type semiconductor conductive portion 62 via a contact window.
  • a tower-shaped cathode 63 having a circular cross section is formed on the surface of the silicon substrate 61 serving as a drain region inside the n-type semiconductor conductive portion 62 serving as a source.
  • the tip of the tower-shaped cathode 63 made of silicon has a tip microstructure on the order of nanometers formed by a sharpening process using thermal oxidation.
  • a lead electrode 68 having a constant opening diameter and for applying an electric field for electron emission is formed on the second insulating layer 65.
  • the p-type silicon substrate 61 and the ri-type semiconductor conductive portion 62 serving as a source region are grounded, and a positive voltage V eX is applied to the extraction electrode 68. Further, when a predetermined voltage Vg is applied to the gate electrode 66 of the FET, the channel region below the gate electrode 66 becomes open, and the conditions for injecting electron carriers from the source to the drain are adjusted. Under this condition, a positive voltage V e X is applied to the extraction electrode 68.
  • the application conditions of V e X and V g at this time are set so as to satisfy the relationship of V g ⁇ V e X.
  • a depletion layer is formed in the surface layer of the p-type silicon substrate under the extraction electrode.
  • an n-type inversion layer is formed on the surface of this depletion layer, and functions as a conductive layer for electron carriers.
  • electrons injected from the channel region are emitted through the formed n-type inversion layer. Will be guided in the direction of As a result, even if an n-type semiconductor conductive portion is not formed in the drain, substantially the same transistor operation can be performed by applying a constant voltage to V eX.
  • electrons In a field emission electron source having a fixed gate opening diameter on the order of submicrons and a cathode tip on the order of nanometers, electrons begin to be field-emitted from the tip of the cathode 63 by applying a voltage of several tens of volts. . The emitted electrons proceed while being accelerated toward an anode plate (not shown) facing the p-type silicon substrate 61.
  • the amount of electron current emitted from the cathode 63 is not controlled by the fixed gate voltage V e X applied to the extraction electrode 68, but rather by the gate electrode of the FET connected to the cathode 63. It is controlled by the variable gate-source control voltage Vg applied to 6. That is, the FET operates in the constant current region by appropriately selecting the gate-source control voltage Vg applied to the gate electrode 66. As described above, the amount of electron flow radiation emitted from the cathode 63 in the electric field is determined by the characteristics of the FET which has a function of supplying the emitted electrons connected in series with the emitter.
  • the feature of the field emission electron source of the present embodiment is that it has an island structure whose outer peripheral portion is surrounded by a source region and a channel region.
  • the gate electrode for controlling the operation of the FET is symmetrically arranged around the cathode of the field emission electron source.
  • the amount of electrons emitted from the cathode varies depending on the position of the cathode.However, in the present invention, the amount of electrons emitted is symmetrical with respect to the n-type inversion layer region where the cathode is formed. Since carriers are uniformly and symmetrically injected through the gate electrodes arranged, variations in electron emission in the n-type inversion layer region are suppressed.
  • the extraction electrode of the present invention is effective not only for controlling the amount of emitted electrons but also for controlling the beam trajectory of emitted electrons.
  • the emission was achieved. Electrons exhibit a convergence effect under the influence of the Vg electric field in a vacuum. This is because a potential of V g set lower than V e X generates an electric field which has a converging effect on electrons emitted from the cathode toward the opposite anode. Since the converged electric field from the gate electrode symmetrically arranged with respect to the cathode is generated symmetrically with respect to the electron trajectory, it has an excellent lens operation which has not been achieved in the prior art.
  • the gate electrode 66 that brings the convergence effect is formed as a wiring buried between the first insulating layer 64 and the second insulating layer 65, and is located at a position lower than the extraction electrode 68. Is formed. Due to this relative arrangement, relative to V ex Even when a very low voltage is applied to V g, the effect of the gate electrode 66 does not reach the cathode 63. In the conventional structure, the electron emission amount is reduced together with the convergence function. However, in the configuration of the present invention, it is possible to have a sufficient convergence function while maintaining the electron emission amount.
  • the shape of the cathode 63 is an evening shape has been described.
  • a similar effect can be obtained with a conventional conical cathode shape.
  • As the material of the cathode 63 an example in which a p-type silicon substrate is formed by processing is used, but a conventional metal material (a refractory metal material such as molybdenum and tungsten) or a carbon-based material (a diamond, The same effect can be obtained by using an ait or diamond-like carbon.
  • 7A and 7B are a cross-sectional view and a plan view, respectively, of the field emission type electron source device according to the present embodiment.
  • FIG. 7A is a cross-sectional view taken along the line I-I in FIG. 1 shows a cross-sectional structure.
  • 71 is a p-type silicon substrate
  • 72 is a first n-type semiconductor conductive portion serving as a source region of an element operating as a field effect transistor (FET)
  • 73 is a drain of the FET.
  • 74 is a cathode operating as a field-emission electron source in a tower shape having a circular cross section
  • 75 is silicon mainly functioning as a gate insulating film of a FET.
  • the first consisting of oxide film It is an insulating layer.
  • Reference numeral 76 denotes a second insulating layer mainly composed of a silicon oxide film serving as an insulating film for a lead electrode of a field emission electron source, 77 denotes a gate electrode for controlling a channel region for FET, and 78 denotes a gate electrode.
  • a source electrode for FET and 79 is an extraction electrode for cathode.
  • a part of one main surface of the p-type silicon substrate 71 is provided with a second source serving as an FET source.
  • the first n-type semiconductor conductive portion 73 and the second n-type semiconductor conductive portion 73 serving as a drain are formed, and the second n-type semiconductor conductive portion 73 is formed of the first n-type semiconductor conductive portion 72.
  • the inner peripheral shape of the first n-type semiconductor conductive portion 72 serving as a source and the outer peripheral shape of the second n-type semiconductor conductive portion 73 serving as a drain have circular shapes formed concentrically.
  • the channel region of the FET is located between the source region and the drain region and has a ring shape.
  • a ring-shaped gate electrode 77 buried between the first insulating layer 75 and the second insulating layer 76 is formed so as to cover the ring-shaped channel.
  • a source electrode 78 is formed on the source n-type semiconductor conductive portion 72 via a contact window.
  • an evening cathode 74 having a circular cross section is formed on the surface of the second n-type semiconductor conductive portion 73 serving as a drain.
  • an evening cathode 74 having a circular cross section is formed at the tip of the silicon-shaped cathode 74 made of silicon.
  • a nanometer-order tip microstructure is formed by a sharpening process using thermal oxidation.
  • a certain opening is provided around the cathode 74 and is formed on the extraction electrode 79 for applying an electric field for electron emission to the second insulating layer 76.
  • the p-type silicon substrate 71 is connected to the first n-type semiconductor conductive portion 72 serving as a source region. Then, a positive voltage V cx is applied to the extraction electrode 79. Furthermore, when a predetermined voltage Vg is applied to the gate electrode 77 of the FET, the channel region below the gate electrode 77 is opened, and the conditions for injecting electron carriers from the source to the drain are established. Under this condition, a positive voltage Vex is applied to the extraction electrode 79. The application conditions of Vex and Vg at this time are set so as to satisfy the relationship of Vg ⁇ Vex.
  • electrons In a field emission electron source in which a gate opening diameter on the order of submicrons and a cathode tip on the order of nanometers are formed, electrons begin to be field-emitted from the tip of the cathode 74 by applying a voltage of usually several tens of volts. The emitted electrons proceed while being accelerated toward the anode plate, which is arranged opposite to the p-type silicon substrate 7 ′ (not shown).
  • the amount of electron current emitted from the cathode 74 is not controlled by the fixed gate voltage V eX applied to the extraction electrode 79, but is applied to the gate electrode 77 of the FET connected to the cathode 74. Is controlled by the variable gate-source control voltage Vg. In other words, the FET operates in the constant current region by appropriately selecting the gate-source control voltage Vg applied to the gate electrode 77. As described above, the amount of the electron current emitted from the cathode 74 in the electric field is determined by the characteristics of the FET having a function of supplying the emitted electrons connected in series with the emitter.
  • the FET By optimally designing the FET, it becomes possible to design the operating conditions of the .FET and the field emission electron flow in advance. In particular, by performing field emission in the saturation operation region of the FET, an extremely stable and precisely controlled field emission electron flow can be obtained as a result without being affected by the instability factors of the emitter itself. .
  • a feature of the drain structure of the present embodiment is that the drain structure has an island structure surrounded by a source region and a channel region. Gate electrodes for controlling the operation of the FET are arranged symmetrically in a ring around the cathode of the field emission electron source. I have. By employing this arrangement, it is possible to uniformly inject the carrier from the source region to the drain region.
  • the drain of the normal structure injects carriers from a part of the boundary adjacent to the channel region.
  • the injected carriers diffuse in the drain and reach the cathode of the field emission electron source. Therefore, it is expected that the carrier concentration varies depending on the position of the drain.
  • the configuration in which one cathode is formed in the drain has been described. However, when used as a pixel for FED, it is usually 1. Multi-emissive in which several hundred cathodes are formed in the drain per pixel. Use the configuration. If the carrier density in the drain is different, it is expected that the amount of electrons emitted from the cathode will vary depending on the position of the cathode, but in the present invention, the cathode is arranged symmetrically with respect to the drain on which the cathode is formed. Since carriers are injected uniformly and symmetrically through the gate electrode, variations in electron emission within the drain are also suppressed.
  • the extraction electrode of the present invention is effective not only for controlling the amount of emitted electrons, but also for controlling the beam trajectory of emitted electrons.
  • the emission is achieved.
  • the electrons are affected by the Vg electric field in a vacuum and exhibit a convergence effect. This is because a potential of V g set lower than V e X generates an electric field which has a converging effect on electrons emitted from the cathode toward the opposite anode. Since the converging electric field from the gate electrode arranged symmetrically with respect to the cathode in a ring shape is generated completely symmetrically with respect to the electron trajectory, it has a better lens action than ever before.
  • the gate electrode 77 that brings the convergence action is formed as a wiring embedded between the second insulating layer 75 and the second insulating layer 76, and the lower layer of the extraction electrode 79 is hidden. Is formed. Due to this relative arrangement, even when a voltage lower than Vex is applied to Vg, the effect of the gate electrode 77 is not affected by the cathode. Less than 7 4 In the conventional structure, the electron emission amount is reduced together with the convergence function. However, in the configuration of the present invention, it is possible to have a sufficient convergence function while maintaining the electron emission amount.
  • the present embodiment it is possible to suppress variations in electron emission in the drain and complete beam focusing effect by symmetrically arranged ring-shaped gate electrodes. A high-density emission operation with a small spread can be guaranteed. Therefore, the obtained configuration can be expected as a good field emission electron source suitable for high definition display.
  • the shape of the cathode 74 is a tower shape.
  • the same effect can be obtained with a conventional conical cathode shape.
  • a conventional metal material a refractory metal material such as molybdenum or tungsten
  • a carbon-based material a diamond, a graphite
  • the drain end of the FET is formed of the low impurity concentration well, so that the electric field concentration near the drain during the FET operation is greatly reduced. be able to.
  • the performance degradation of the FET caused by the hot-elect opening and the like can be prevented, and the reliability of the device operation can be significantly improved.
  • an impurity element a phosphorus source with a high thermal diffusion rate used in semiconductor processes
  • elemental arsenic which has a slow thermal diffusion rate, has the advantage that an impurity profile with excellent controllability can be formed.
  • the drain current density can be reduced, and as a result, there is an advantage that the performance of the FET is prevented from deteriorating due to hot electrons.
  • the transistor gate insulating film for FET can be set thin and the insulating film for field emission electron sources can be set thick, there is an advantage that device performance can be improved. Furthermore, since the channel gate electrode is configured to be embedded in the insulating film, a multi-layer wiring can be easily formed, which is suitable for matrix drive wiring.
  • a silicon thermal oxide film is used as the gate insulating film, FET control with excellent controllability and high reliability can be achieved.
  • the channel region of FET is covered with a shield electrode except for the channel gate region, the effect of the external electric field due to the ion charge during electron emission can be prevented.
  • the shield effect from the external electric field is further increased.
  • the gate electrode arrangement for FET control is designed symmetrically around the drain, electron injection from the source to the drain can be made uniform, and the uniformity of electron emission can be improved.
  • the beam trajectory can be converged without reducing the amount of field emission.
  • the inversion layer formed by the extraction electrode the same function as that of the n-type semiconductor conductive layer can be provided, and the process can be simplified.
  • the gate electrode of the FET is formed in a ring shape symmetrically around the drain, The convergence operation of the electron orbit can be performed more reliably.
  • Vg ⁇ VeX By providing a relationship of Vg ⁇ VeX between the voltage Vg applied to the gate electrode and the voltage VeX applied to the extraction electrode, a negative electric field effect is generated on electrons emitted from the cathode. Convergence of the electron orbit can be performed more reliably.

Abstract

L'invention concerne une source d'électrons à émission de champ comprenant une partie source d'électrons à émission de champ composée d'un substrat (1) en silicium de type p et une partie transistor à effet de champ à canaux n formée sur le substrat (1) en silicium de type p dans une position correspondant à la partie de source d'électrons à émission de champ et dans laquelle la partie de source d'électrons à émission de champ est disposée dans la région du drain de la partie de transistor à effet de champ, le courant à émission de champ de la partie de source à émission de champ est régulé par une tension de commande appliquée à l'électrode de grille (8) de la partie transistor à effet de champ, dans laquelle la région de drain comprend au moins deux puits (3, 4) présentant des concentrations d'impuretés différentes, le puits (4) ayant la faible concentration d'impuretés étant disposé au niveau d'une partie terminale de la région de drain en contact avec la région de canaux de la partie transistor à effet de champ.
PCT/JP1999/001423 1998-03-23 1999-03-19 Source d'electrons a emission de champ WO1999049491A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP99909285A EP1071109A4 (fr) 1998-03-23 1999-03-19 Source d'electrons a emission de champ
US09/622,734 US6818915B1 (en) 1998-03-23 1999-03-19 Field-emission electron source
KR1020007010567A KR20010034645A (ko) 1998-03-23 1999-03-19 전계 방출형 전자원 장치

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP10/73828 1998-03-23
JP7382898 1998-03-23
JP29825098 1998-10-20
JP10/298250 1998-10-20

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WO1999049491A1 true WO1999049491A1 (fr) 1999-09-30

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EP (1) EP1071109A4 (fr)
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000054299A1 (fr) * 1999-03-09 2000-09-14 Matsushita Electric Industrial Co., Ltd. Dispositif a emission de champ, son procede de fabrication et dispositif d'affichage utilisant celui-ci

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006186261A (ja) * 2004-12-28 2006-07-13 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
WO2009151170A1 (fr) * 2008-06-13 2009-12-17 Jda Technology Co., Ltd. Transistor à canal à vide
FR2934716B1 (fr) * 2008-07-31 2010-09-10 Commissariat Energie Atomique Diode electroluminescente en materiau semiconducteur et son procede de fabrication
US20110100430A1 (en) * 2009-11-05 2011-05-05 AgilePower Systems, Inc Hybrid photovoltaic and thermionic energy converter
KR101951296B1 (ko) * 2011-12-06 2019-04-26 엘지디스플레이 주식회사 산화물 반도체층을 갖는 박막트랜지스터 및 이를 구비한 어레이 기판

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6022375A (ja) * 1983-07-19 1985-02-04 Seiko Epson Corp Ｍｏｓ型半導体装置
JPS6055616A (ja) * 1983-09-07 1985-03-30 Hitachi Ltd 半導体装置の製造方法
JPH07130281A (ja) * 1993-10-28 1995-05-19 Nec Corp 電界放出型陰極装置
JPH0963467A (ja) * 1995-08-25 1997-03-07 Kobe Steel Ltd 冷電子放出素子及びその製造方法
JPH11102637A (ja) * 1997-09-29 1999-04-13 Futaba Corp Ｍｏｓｆｅｔ型電子放出素子

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124872A (ja) * 1983-12-09 1985-07-03 Matsushita Electric Ind Co Ltd 縦型ｍｏｓ電界効果トランジスタ
JPS62229880A (ja) 1986-03-31 1987-10-08 Toshiba Corp 半導体装置及びその製造方法
JPS6461953A (en) 1987-09-02 1989-03-08 Victor Company Of Japan Mos transistor
IT1223571B (it) * 1987-12-21 1990-09-19 Sgs Thomson Microelectronics Procedimento per la fabbricazione di dispositivi integrati cmos con lunghezze di porta ridotte
JPH029134A (ja) 1988-06-28 1990-01-12 Matsushita Electron Corp 半導体装置の製造方法
US5396096A (en) * 1992-10-07 1995-03-07 Matsushita Electric Industrial Co., Ltd. Semiconductor device and manufacturing method thereof
JP3195170B2 (ja) 1994-09-16 2001-08-06 アルプス電気株式会社 電界放射陰極装置
JP3380117B2 (ja) * 1995-07-24 2003-02-24 セイコーインスツルメンツ株式会社 半導体装置とその製造方法
JP3171121B2 (ja) 1996-08-29 2001-05-28 双葉電子工業株式会社 電界放出型表示装置
EP0845815A3 (fr) * 1996-11-28 1999-03-03 Matsushita Electric Industrial Co., Ltd. Dispositif semi-conducteur, méthode de conception, et dispositif de circuit intégré semi-conducteur

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6022375A (ja) * 1983-07-19 1985-02-04 Seiko Epson Corp Ｍｏｓ型半導体装置
JPS6055616A (ja) * 1983-09-07 1985-03-30 Hitachi Ltd 半導体装置の製造方法
JPH07130281A (ja) * 1993-10-28 1995-05-19 Nec Corp 電界放出型陰極装置
JPH0963467A (ja) * 1995-08-25 1997-03-07 Kobe Steel Ltd 冷電子放出素子及びその製造方法
JPH11102637A (ja) * 1997-09-29 1999-04-13 Futaba Corp Ｍｏｓｆｅｔ型電子放出素子

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1071109A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000054299A1 (fr) * 1999-03-09 2000-09-14 Matsushita Electric Industrial Co., Ltd. Dispositif a emission de champ, son procede de fabrication et dispositif d'affichage utilisant celui-ci

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EP1071109A1 (fr) 2001-01-24
EP1071109A4 (fr) 2003-07-09
KR20010034645A (ko) 2001-04-25
US6818915B1 (en) 2004-11-16

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