WO1999046815A1 - Circuit electronique integre et son procede de production - Google Patents

Circuit electronique integre et son procede de production Download PDF

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Publication number
WO1999046815A1
WO1999046815A1 PCT/DE1999/000437 DE9900437W WO9946815A1 WO 1999046815 A1 WO1999046815 A1 WO 1999046815A1 DE 9900437 W DE9900437 W DE 9900437W WO 9946815 A1 WO9946815 A1 WO 9946815A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor material
porous
electronic circuit
integrated electronic
circuit arrangement
Prior art date
Application number
PCT/DE1999/000437
Other languages
German (de)
English (en)
Inventor
Hansjörg REICHERT
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Priority to EP99917747A priority Critical patent/EP1062696A1/fr
Priority to JP2000536105A priority patent/JP2002507060A/ja
Publication of WO1999046815A1 publication Critical patent/WO1999046815A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind

Definitions

  • the invention relates to an integrated electronic circuit arrangement with a semiconductor substrate, at least one inductor and with at least one insulation region.
  • the inductance is, for example, a coil or a waveguide.
  • the invention further relates to a method for producing such an integrated electronic circuit arrangement.
  • LOCOS technology Lical Oxidation of Silicon
  • Isolation structure formed in a multi-step process In this case, a cover layer is first formed from a non-oxidizable material and then structured using an insulation mask that defines the arrangement of the insulation structures. Then isolation structures are formed by local thermal oxidation.
  • the structured cover layer acts as an oxidation mask. In the case of local thermal oxidation, the part of the semiconductor layer that is not covered by the structured cover layer is oxidized through to form the insulation structures. This creates partial areas of a structured semiconductor layer, each of which is characterized by the 2
  • LOCOS layers are generally limited to a thickness of less than 1 ⁇ m. An oxide level occurs here, which is approximately half the thickness of the LOCOS layer.
  • trenches are first etched into a semiconductor substrate using an etching mask, which trenches are then filled with insulating material. This method is not suitable for forming insulation structures of any shape.
  • CVD Chemical Vapor Deposition
  • the object of the invention is to avoid the disadvantages of the prior art.
  • an insulation structure is to be created which is suitable for use in a high-frequency component. Impairment of the functionality of the integrated electronic circuit by the insulation structure should be avoided.
  • this object is achieved in that a generic integrated electronic circuit arrangement is designed such that the insulation region is formed by a porous semiconductor material and that the insulation region extends deeper than the inductance into the semiconductor substrate.
  • the invention provides for an integrated electronic circuit arrangement to be designed in such a way that the density of the semiconductor material is deliberately reduced in at least one area contained in it. By reducing the density of the semiconductor material, its conductivity is specifically reduced. In addition, such a porous structure enables targeted further treatment of the material present in this area.
  • An insulation area formed by the porous semiconductor material penetrates deeper into the semiconductor substrate than areas with noticeable electromagnetic waves generated, for example, by a coil and / or a waveguide 4
  • the insulation region preferably penetrates deeper into the semiconductor substrate than active regions, for example channel regions of transistors.
  • An advantageous embodiment of an integrated electronic circuit arrangement according to the invention is characterized in that the insulation region is located between an electrical conductor and the semiconductor substrate.
  • the insulation region prefferably located between the electrical conductor and an electrically active element.
  • the invention relates in particular to layers which are produced from a surface of a semiconductor substrate, it being possible for the semiconductor substrate to be regarded as a counter electrode. It is possible for the entire semiconductor substrate to be made continuously porous in some areas and for the rear side of the semiconductor substrate to be metallized. Such metallization can take place, for example, following a conversion of the semiconductor substrate into its porous state. It is fundamentally conceivable here to let the process of converting the semiconductor material into its porous state take place both from the top and from the bottom.
  • the integrated electronic circuits (circuit arrangements) according to the invention can easily be designed so that high-frequency currents flow within them. With the help of such an integrated electronic circuit, microprocessors with clock rates in the GHz range can be realized. It is also possible for such an integrated electronic circuit to have a transmitter or a receiver for high-frequency electromagnetic
  • Radiation - also in the GHz range - contains or forms one.
  • any porous semiconductor material can be used in an electronic circuit according to the invention. However, it is particularly expedient that the porous semiconductor material and the rest
  • Semiconductor substrate contain essentially the same semiconductor elements.
  • the fact that the semiconductor material and the semiconductor substrate contain substantially identical semiconductor elements does not preclude the semiconductor material from being chemically converted. Such a chemical
  • Conversion is particularly expedient because it significantly improves the properties, in particular the insulating properties, of the porous semiconductor material.
  • the production of the porous semiconductor material can be inserted particularly simply into the manufacturing process of the integrated electronic circuit arrangement.
  • An identical chemical composition of the semiconductor material and the semiconductor substrate is not necessary here.
  • This embodiment includes in particular the case that the concentration of the dopant in the insulation region and in the semiconductor substrate differ from one another. Such differences can be used in a targeted manner to create defined, true-to-geometry, porous areas. For example, it is possible that a defined stop in the conversion of monocrystalline silicon into porous silicon at an n + / n ⁇ transition can be used within the process sequence. This enables a defined local conversion, in particular of single-crystalline silicon into its porous state. In this way, a precisely defined insulation structure can be generated locally.
  • the semiconductor material can consist essentially of silicon. It is advantageous that the porosity of the semiconductor material is between 20% and 80%. The lower limit results from the required mechanical stability, the upper limit from a still tolerable resulting conductivity of the layer.
  • the porosity of the semiconductor material is between 40% and 60%.
  • porous semiconductor material is chemically converted, for example nitrided or oxidized, to improve the insulation properties.
  • porous semiconductor material is doped more or less than the semiconductor material adjacent to it.
  • the porous semiconductor material is doped with a dopant of a different conductivity type than the semiconductor material adjacent to it.
  • the selected doping is particularly useful for generating an etch stop.
  • the lowest possible doping is advantageous in order to achieve the highest possible insulation.
  • a chemical conversion for example oxidation or nitridation, means that the concentration loses importance for the finished product.
  • the relevance of the selected doping therefore lies in the targeted influencing of the process flow.
  • a jump in concentration for example between an n + - 7
  • n " -doped region leads to the generation of an etch stop.
  • concentration also influences the conversion of the semiconductor material into a porous state.
  • an n + -doped region with a concentration of at least 1 x 10 18 cm -3 is converted into porous silicon, while an n ⁇ -doped region with a concentration of preferably less than 1 x 10 16 cm -3 is not converted.
  • Any n-doping substance can be used as the dopant, with silicon in particular phosphorus, Arsenic or antimony are suitable.
  • the invention uses in particular the surprising effect that a converted semiconductor material can be used as an insulator.
  • the invention particularly relates to a targeted conversion of the semiconductor material into an insulator or quasi-insulator. Even without chemical conversion or treatment of the porous semiconductor material produced, very low conductivities occur due to an impediment or interruption of current threads. A possible subsequent explanation of this unexpected insulation property could lie in the fact that the formation of current threads is avoided by the porosity of the semiconductor material.
  • the concentration of the dopant is of particular importance for the manufacturing process of the integrated electronic circuit arrangement.
  • a concentration gradient is preferably selected in each case, by means of which an etching stop can be achieved.
  • the respective etching process is preferably selected for its compatibility with the other manufacturing processes of the integrated electronic circuit arrangement.
  • the illustrations also show that the type of dopant is important for the process.
  • phosphorus is particularly suitable, since it can be redistributed particularly easily by heat treatment.
  • a coil suitable for high-frequency applications can be used in the circuit arrangement.
  • the inventive design of the integrated electronic circuit arrangement effectively prevents eddy currents and displacement currents.
  • connecting lines enables the production of microprocessors with clock frequencies in the gigahertz range.
  • porous semiconductor material prefferably be present essentially in the form of a layer.
  • Such a layer can penetrate several ⁇ m deep into the semiconductor substrate.
  • a reinforcement of the insulating effect achieved by the conversion into a porous semiconductor material can expediently be achieved by a combination of the porous layer shown, which goes deep, with one or more conventional insulating layers.
  • the conventionally insulating layer or the conventional insulating layers can be produced, for example, by one of the known CVD processes. Conventional layers of this type are expediently applied to the porous semiconductor material.
  • a particular importance of the converted porous layers shown here is that they can have other electrical properties outside their porous, insulating area. For example, other areas of such a layer are converted into active areas of transistors. 9
  • the invention further relates to a method for producing an integrated electronic circuit arrangement, in which at least one inductance is formed in the region of a main surface of a semiconductor substrate. This method is carried out according to the invention in such a way that in a region of the semiconductor substrate a semiconductor material present in an essentially solid form is converted into a porous semiconductor material.
  • Such a method can be a
  • Modification act one of the known methods for generating an integrated electronic circuit arrangement.
  • the modification consists in that the method is carried out in such a way that at least one area located in the integrated electronic circuit is designed in such a way that its density is deliberately reduced.
  • a particularly simple form of this method is characterized in that a single-crystalline semiconductor material is converted into porous semiconductor material.
  • the method according to the invention is preferably carried out such that the essentially solid semiconductor material is converted into the porous semiconductor material by an etching step.
  • Semiconductor material is converted, is doped differently than semiconductor material adjacent to this area, so that an etching stop is generated.
  • This embodiment of the method according to the invention provides for an area which is to be converted into porous semiconductor material by etching in a later method step to be doped differently than one or more other areas which are not to be converted.
  • the region is also possible for the region to be doped with a dopant of a different conductivity type than the adjoining semiconductor material.
  • the conversion of the essentially solid semiconductor material into the porous semiconductor material includes an electrochemical process step.
  • the preferably single-crystalline semiconductor substrate can be converted into a porous semiconductor substrate particularly advantageously by an electrochemical treatment, because the degree of porosity can be influenced by the process parameters of the electrochemical treatment process. Expediently, during the electrochemical
  • Process step acid added. It is thus possible to remove material from the semiconductor substrate in a targeted manner by increasing the voltage and thus the current density and / or the acid concentration.
  • An HF-containing solution is advantageously added during the electrochemical process step.
  • the substrate hardly experiences a change in volume.
  • a volume constancy is brought about by the porosity of the semiconductor material.
  • the porosity is the volume fraction of the space that is not filled by the semiconductor material.
  • the area treated accordingly has a particularly large surface area. This means that chemical reactions can take place quickly in this area or with only a very small requirement for external heat input.
  • a higher pore density, i.e. a smaller proportion of the semiconductor material leads to a “foam-like” structure, which has the further advantage that the dielectric constant ⁇ is reduced.
  • the structure according to the invention has advantageous dielectric properties solely according to the increased porosity of the semiconductor material. However, these properties are further improved by the aftertreatment.
  • Fig. 1 in four fields A to D the manufacturing process of an integrated electronic
  • Circuit arrangement in which a transistor and an electrical conductor belonging to a coil are produced side by side in a semiconductor substrate.
  • Fig. 2 in six fields A to F, the manufacturing process of an integrated electronic circuit arrangement with a transistor, an electrical conductor belonging to a coil and with a connection area.
  • the partial images A to D of FIG. 2 show cross sections through different processing stages of a semiconductor substrate.
  • a region 20 of a semiconductor substrate 10 which is provided for the formation of a transistor and which preferably consists of single-crystal, p-doped silicon, a
  • Dopants which have a low diffusion in the semiconductor substrate 10 are arsenic as or antimony Sb.
  • the implantation of the dopants is carried out by ion implantation with an energy of approximately 50 keV and a dose of, for example, 1 x 10 16 at / cm 2 .
  • Ions are implanted in the region 30 of the semiconductor substrate 10 provided for the formation of a coil, which ions have a high diffusion rate in the semiconductor substrate, for example phosphorus.
  • the implantation is also carried out by ion implantation, but the implantation energy is chosen to be as high as possible. Because of their wide availability, implanters with an implantation energy of 200 keV are used. The annealing times shown below also refer to this implantation energy. With a higher implantation energy, the annealing times decrease, while they are extended with a reduction in the implantation energy.
  • the implantation dose is again approximately 1 x 10 16 at / cm 2 .
  • Subsequent annealing preferably lasting about 200 minutes, at 1150 ° C. results in a penetration depth of the region 40 forming a buried collector of 3.5 ⁇ m.
  • the thickness of the layer 50 is approximately 6 ⁇ m.
  • a semiconductor layer 60 is then epitaxially grown on the semiconductor substrate 10 both in the region 20 which is provided for the formation of active components and in the region 30 which is provided for the formation of coils.
  • This, preferably p-doped, layer is grown, for example, to a thickness of approximately 1 ⁇ m to 3 ⁇ m, 2 ⁇ m being preferred.
  • the dopant Due to the high diffusion tendency of the dopant implanted in the region 50, the dopant also penetrates into the 14
  • epitaxial semiconductor layer 60 A cross section through the semiconductor substrate after the process steps explained last have been carried out is shown in partial image A of FIG. 1.
  • the implantation of phosphorus produces a collector connection layer 80 or a highly doped connection layer 90 for connection of the region 50 both in the region 20 intended for the formation of transistors and for the formation of coils (FIG. 1B). .
  • a lacquer mask 100 is then applied which completely covers the area of the active components and at most partially the area which is intended for the formation of coils.
  • the semiconductor substrate is then treated electrochemically.
  • the electrochemical treatment is carried out, for example, in hydrofluoric acid with a preferred concentration of about 30%.
  • a voltage between 0.5 and 10 volts is applied, 2 volts having proven particularly suitable.
  • This process is advantageously carried out at room temperature.
  • the entire highly doped region 50 and 90 is completely converted into a porous material.
  • This conversion into porous semiconductor material takes place only in the highly doped (n + -doped) regions 50 and 90. The conversion therefore stops at the borders of the n + -doped regions 50 and 90 in a self-adjusting manner.
  • This processing state is shown in FIG. 1C, the area 90 not being shown separately for the sake of simplicity.
  • the thickness of the porous semiconductor material is equal to the sum of the depth of penetration of the dopant into the semiconductor substrate and the thickness of the epitaxially grown layer. Increasing the temperature or the annealing time and, if appropriate, the implantation dose for the layer 50 can produce higher layer thicknesses. There is no basic upper limit for the layer thickness.
  • Sub-images A to F of FIG. 2 show cross sections through different processing stages of a semiconductor substrate with an active area in which, for example, a transistor can be located, an area provided for receiving a coil and an area provided for forming a connection.
  • the potential of a layer 200 can be adjusted to avoid parasitic thyristors (latch-up effect) on voltage values present in other areas of the integrated electronic circuit arrangement.
  • a dopant layer is generated by the diffusion of a dopant which has a high depth of penetration, for example phosphorus.
  • Layers 240 and 250 are created as well as areas 40 and 50 from the first example. Here too, the points of view for dimensioning the process parameters apply.
  • the substrate 200 has an n + doping, for example with arsenic, of more than 1 x 10 18 at / cm 3 .
  • the result of this processing operation is shown in partial image A in FIG. 2.
  • Layer 240 has an n + doping that can diffuse quickly while the n + doping of substrate 200 diffuses slowly.
  • a preferably p-doped semiconductor layer is deposited both in the area of the active elements as well as the coil and the connection with a thickness of preferably 1 to 5 ⁇ m, with 2 ⁇ m being particularly preferred.
  • a cross section through the semiconductor substrate after these method steps is shown in partial image B.
  • the area 220 intended for the formation of the coil and the area 230 provided for the formation of the connection in the epitaxial layer 260 become area-wide the first implantation areas, that is to say the layers 240 and 250, by the implantation of ions with a high
  • Diffusion tendency dopant layers 270 and 280 formed.
  • a dopant layer 290 is generated by the implantation of a dopant such as arsenic or antimony. This state of the semiconductor substrate is shown in partial image C in FIG. 2.
  • the layer 260 has a thickness that is so large that the slowly diffusing doping from the substrate 200 does not reach the dopant layer 290 after all process steps.
  • An upper limit on the thickness of layer 260 is 17
  • the semiconductor substrate is annealed.
  • a thickness of layer 260 of 5 ⁇ m to 10 ⁇ m and the same
  • Implantation parameters for layers 270 and 280 as for layers 240 and 250 can be diffused in at 1150 ° C. and a diffusion time of approximately 200 minutes.
  • Layers 240 and 270 on the one hand and layers 250 and 280 on the other hand combine to form thicker layers
  • Diffusion regions 300 and 310 Diffusion regions 300 and 310, the diffusion region 310 being referred to below as the 7 connection region because of its function in the finished integrated electronic circuit arrangement.
  • a semiconductor layer 320 which is preferably doped with dopants of the p-type, is applied to the diffusion region 300 and the connection region 310.
  • the dopant concentration in the semiconductor layer 320 is set so that it has the best possible properties for the formation of active electrical elements.
  • the combination of the layers 240 and 270 on the one hand and the layers 250 and 280 on the other hand into thicker diffusion regions 300 and 310 does not have to take place until after the semiconductor layer 320 has been applied.
  • the semiconductor layer 320 is applied, for example, by epitaxial growth. In the case of epitaxial growth, diffusion also takes place, that is to say the dopant penetrates from a base into the epitaxial layer. Since the epitaxial growth is a high-temperature process with process temperatures in the order of 1100 ° C, a separation of the 18th
  • the epitaxial growth process of the diffusion processes is not possible here.
  • the resulting state of the semiconductor substrate is shown in partial image D in FIG. 2.
  • a collector connection region is formed in an edge region of the layer 290, which penetrates the epitaxially grown layer 320 in this region.
  • a dopant is likewise introduced over a large area onto the diffusion region 300 and the connection region 310, which is preferably done by diffusion. This process step is shown in partial image E in FIG. 2.
  • connection region 310 penetrates the layer 260 in the region 230 and forms a junction-free connection of the substrate 200 to a surface.
  • a varnish mask is then applied, which completely covers the area 210 provided for the formation of active elements and at most partially covers the area of the coil and the area 230 in which a connection is formed.
  • the semiconductor substrate is subsequently treated electrochemically.
  • the electrochemical treatment takes place, for example, in hydrofluoric acid with a preferred concentration of about 30% and with an applied voltage between 0.5 and 10 volts, 2 volts having proven particularly suitable. This process is advantageously carried out at room temperature. As a result, the entire areas 300 and 350 are completely converted into a porous material.
  • the converted region 350 of the semiconductor substrate 200 is not limited to the region 220 provided for the formation of a coil, but it can also at least partially extend into the region 210 of the active elements or the region 230 serving to form a connection. Furthermore, the entire doped region 300 has been completely converted to its porous state.
  • a thin oxide layer 360 with a thickness that depends on the process of oxidation and is usually between 0.1 ⁇ m and 0.5 ⁇ m is formed outside the highly doped region 300, in which the porous semiconductor material is now located.
  • regions 300 and 350, which are now filled with porous material there is complete oxidation in the entire depth of the porous material, that is to say preferably in the order of magnitude of 12 ⁇ m.
  • the thicknesses shown are only to be understood as examples. A volume increase due to the chemical conversion leads to the porosity of the
  • connection region 310 penetrates the layer 260 in the region 230 and forms a barrier-free connection of the substrate 200 to a surface.
  • the regions 40 (buried collector) and 50 or 240 and 250 are diffused in together.
  • the desired properties of the integrated electronic circuit arrangement were thereby achieved.
  • the common diffusion of the areas leads to a coupling of their penetration depths.
  • Circuit arrangements in which such a coupling is to be broken for example in order to achieve particularly deep layers in combination with particularly thin layers, it makes sense to carry out the implantation in the region 30, or in the regions 220 and 230, first, this layer thermally to a desired depth of penetration and then to produce a layer in the area 20 or 210.
  • Such decoupling can take place, for example, as follows in the exemplary embodiment shown in FIG. 1.
  • the region 50 is implanted with phosphorus within the region 30 provided for the formation of a coil, with subsequent annealing at approximately 1150 ° C. in a period of approximately 800 minutes.
  • arsenic for the doping of the region 40 (buried collector) is implanted in the region 20 provided for the formation of an active element.
  • a further heat treatment for example at 1000 ° C., for the area 40 to heal. This results in a thickness of 0.5 ⁇ m for the area 40 forming a buried collector and a thickness of 10 ⁇ m for the layer 50.
  • the thickness of the layer 50 can be increased even further without the thickness of the region 40 changing.
  • a lower limit is a diffusion time that is still acceptable for the manufacturing processes.
  • the parameters are set to the desired depth of penetration.
  • the penetration depth is proportional to the root of the product of the diffusion coefficient and the diffusion time.
  • an active component is formed by a bipolar transistor.
  • other active components for example a MOS or a CMOS component, to be used. This is done, for example, by forming the region 20 or 320 as an n-doped layer and placing it in a p-doped trough. Accordingly, a p-MOS transistor can be produced directly in an n-doped epi layer.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne une circuit électronique intégré comprenant un substrat semi-conducteur (10), au moins une inductance et au moins une zone d'isolation. Le circuit selon l'invention est caractérisé en ce que la zone d'isolation est constituée d'un matériau semi-conducteur (50) poreux et en ce que la zone d'isolation s'étend dans le substrat semi-conducteur (10) sur une plus grande profondeur que l'inductance. L'invention concerne également un procédé de production d'un tel circuit électronique intégré.
PCT/DE1999/000437 1998-03-12 1999-02-17 Circuit electronique integre et son procede de production WO1999046815A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP99917747A EP1062696A1 (fr) 1998-03-12 1999-02-17 Circuit electronique integre et son procede de production
JP2000536105A JP2002507060A (ja) 1998-03-12 1999-02-17 集積電子回路装置及びその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19810825.7 1998-03-12
DE1998110825 DE19810825A1 (de) 1998-03-12 1998-03-12 Integrierte elektronische Schaltungsanordnung und Verfahren zu ihrer Herstellung

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Publication Number Publication Date
WO1999046815A1 true WO1999046815A1 (fr) 1999-09-16

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JP (1) JP2002507060A (fr)
CN (1) CN1301398A (fr)
DE (1) DE19810825A1 (fr)
WO (1) WO1999046815A1 (fr)

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CN100341133C (zh) * 2004-10-28 2007-10-03 复旦大学 Pn结衬底隔离片上电感的优化设计方法
US7425485B2 (en) * 2005-09-30 2008-09-16 Freescale Semiconductor, Inc. Method for forming microelectronic assembly

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EP1062696A1 (fr) 2000-12-27
CN1301398A (zh) 2001-06-27
JP2002507060A (ja) 2002-03-05

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