Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J31/00—Cathode ray tubes; Electron beam tubes
  • H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
  • H01J31/10—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
  • H01J31/12—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J31/00—Cathode ray tubes; Electron beam tubes
  • H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
  • H01J31/10—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
  • H01J31/12—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
  • H01J31/123—Flat display tubes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J29/00—Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
  • H01J29/02—Electrodes; Screens; Mounting, supporting, spacing or insulating thereof
  • H01J29/028—Mounting or supporting arrangements for flat panel cathode ray tubes, e.g. spacers particularly relating to electrodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J29/00—Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
  • H01J29/86—Vessels; Containers; Vacuum locks
  • H01J29/864—Spacers between faceplate and backplate of flat panel cathode ray tubes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J31/00—Cathode ray tubes; Electron beam tubes
  • H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
  • H01J31/10—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
  • H01J31/12—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
  • H01J31/123—Flat display tubes
  • H01J31/125—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection
  • H01J31/127—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection using large area or array sources, i.e. essentially a source for each pixel group
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
  • H01J9/02—Manufacture of electrodes or electrode systems
  • H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
  • H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
  • H01J9/02—Manufacture of electrodes or electrode systems
  • H01J9/18—Assembling together the component parts of electrode systems
  • H01J9/185—Assembling together the component parts of electrode systems of flat panel display devices, e.g. by using spacers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
  • H01J9/24—Manufacture or joining of vessels, leading-in conductors or bases
  • H01J9/241—Manufacture or joining of vessels, leading-in conductors or bases the vessel being for a flat panel display
  • H01J9/242—Spacers between faceplate and backplate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J2329/00—Electron emission display panels, e.g. field emission display panels
  • H01J2329/86—Vessels
  • H01J2329/8625—Spacing members
  • H01J2329/863—Spacing members characterised by the form or structure

Definitions

• the present invention relates to field emission devices ("FEDs"). More specifically, the present invention relates to large-area FED structures and the method of making such structures.
• FEDs field emission devices
• fiat panel displays In the world of computers and elsewhere, the dominate technology for constructing fiat panel displays is liquid crystal display (“LCD”) technology and the current benchmark is active matrix LCDs (“AMLCDs").
• LCD liquid crystal display
• AMLCDs active matrix LCDs
• the drawbacks of fiat panel displays constructed using AMLCD technology are the cost, power consumption, angle of view, smearing of fast moving video images, temperature range of operation, and the environmental concerns of using mercury vapor in the AMLCD's backlight.
• each micropoint resembles an inverted cone.
• the forming and sharpening of each micropoint is carried out in a conventional manner.
• the micropoints may be constructed of a number of materials, such as silicon or molybdenum, for example.
• the tips of the micropoints can be coated or treated with a low work function material.
• the structure substrate, emitter electrode, and micropoints may be formed in the following manner.
• the single crystal silicon substrate may be made from a P-type or an N-type material.
• the substrate may then be treated by conventional methods to form a series of elongated, parallel extending strips in the substrate.
• the strips are actually wells of a conductivity type opposite that of the substrate. As such, if the sub- strate is P-type, the wells will be N-type and vice-versa.
• the wells are electrically connected and form the emitter electrode for the FED.
• Each conductivity well will have a predetermined width and depth (which it is driven into the substrate).
• the number and spacing of the strips are determined to meet the desired size of field mission cathode sites to be formed on the substrate.
• the wells will be the sites over which the micropoints will be formed. No matter which of the two methods of forming the strips is used, the resulting parallel conductive strips serve as the emitter electrode and form the columns of the matrix structure.
• a micropoint or pattern of micropoints are disposed on the emitter strip. Each micropoint or pattern of micropoints are meant to illuminate one pixel of the screen display.
• faceplate 140 is fixed a predetermined distance above the top surface of the extraction structure 132. Typically, this distance is several hundred ⁇ m. This distance may be maintained by spacers that are formed by conventional methods and have the following characteristics: (1) non-conductive or highly resistive to prevent an electrical breakdown between the anode (at faceplate 140) and cathode (at emitter electrodes 104, 106, and 108), (2) mechanically strong and slow to deform, (3) stable under electron bombardment (low secondary emission yield), (4) capable of withstanding the high bakeout temperatures in the order of 500° C, and (5) small enough not to interfere with the opera- tion of the FED. Representative spacers 136 and 138 are shown in Figures 1.
• Black matrix 149 is disposed on the surface of the ITO layer 142 facing extraction structure 132.
• Black matrix 149 defines the discrete pixel areas for the screen display of the FED.
• Phosphor material is disposed on ITO layer 142 in the appropriate areas defined by black matrix 149.
• Representative phosphor material areas that define pix- els are shown at 144, 146, and 148.
• Pixels 144, 146, and 148 are aligned with the openings in extraction structure 132 so that a micropoint or group of micropoints that are meant to excite phosphor material are aligned with that pixel.
• Zinc oxide is a suitable material for the phosphor material since it can be excited by low energy electrons.
• the electron emission streams that emanate from the tips of the micropoints fan out conically from their respective tips. Some of the electrons strike the phosphors at 90° to the faceplate while others strike it at various acute angles.
• the basic structure of the FED just described generally will not include spacers when the diagonal screen size is below 5 inches.
• spacers are needed to maintain the correct separation between the emitter electrode and the faceplate under the force of atmospheric pressure on the FED.
• the need for spacers increases so this separation is properly maintained.
• An alternative to the use of spacers is the use of thick glass. However, this thick glass is heavy and expensive.
• the present invention is a large-area FED and a method of making same.
• the large-area FEDs of the present invention are those with a diagonal screen size of 10 inches of greater.
• the large-area FED of the present invention has a substrate into which an emitter electrode is formed.
• the emitter electrode consists of a number of spaced apart, parallel elements that are electrically connected.
• the elements that form the emitter electrode generally extend in one direction across the large- area FED. The width, number, and spacing of the parallel, spaced apart elements are determined by the needs of the FED.
• the low work function material also will result in more uniform performance among the micropoints across the entire large-area FED.
• Cermet Cr 3 Si+SiO 2
• cesium rubidium
• tantalum nitride barium
• chromium suicide titanium carbide
• bium are low work function materials that may be used.
• the faceplate is a cathodoluminescent screen that is transparent.
• the faceplate is capable of transmitting the light of cathodoluminescent photons, which the viewer sees.
• Another object of the present invention is to provide a large-area FED that operates at a relatively low anode voltage and has low power consumption.
• Figure 1 shows a partial cross-section of a prior art FED.
• Figure 2 is a partial top perspective view of a portion of a large-area FED with a portion cut away according to the present invention.
• Figure 4A is a side and cross-sectional view of a "+" shaped spacer.
• Figure 4B is a side and cross-sectional view of a "L" shaped spacer.
• Figure 4D is a side and cross-sectional view of a "I-beam" shaped spacer.
• Figure 5A shows a first step in the deposition, CMP process, and wet chem- ical etching method according to the present invention.
• Figure 5B shows a second step in the deposition, CMP process, and wet chemical etching method according to the present invention.
• Figure 5C shows a third step in the deposition, CMP process, and wet chemical etching method according to the present invention.
• Figure 5D shows a fourth step in the deposition, CMP process, and wet chemical etching method according to the present invention.
• a portion of a large-area FED of the present invention is shown generally at 200.
• the portion that is shown in Figure 2 is near the center of the large-area FED.
• substrate 202 has emitter electrode 204 formed therein or thereon.
• emitter electrode 204 consists of a number of spaced apart, parallel elements that are electrically connected. It is particularly useful to form the emitter electrode in the form of strips given the area that the emitter electrode must cover in a large-area FED, such as that shown in Figure 2.
• the width, number, and spacing of the parallel, spaced apart elements is determined by the needs of the FED, e.g., resolution or diagonal screen size.
• substrate 202 has emitter electrode 204 disposed over it.
• Emitter electrode 204 is the cathode conductor of the FED of the present invention.
• the use of parallel electrodes, spaced, well apart is preferred rather than a continuous emitter electrode that would cover the entire substrate because the use of the elements or strips will reduce the RC times for the large-area FED of the present invention.
• the substrate may be a single structure or it may be made from a number of sections disposed side by side. Either substrate embodiment may be used in carrying our the present invention.
• the micropoints that are placed on the emitter electrode elements are tall micropoints that have a height in thel ⁇ m range.
• these tall micropoints are formed by a conventional etch process and then a low work function material coating is placed on the micropoints according to the present invention.
• the substrate with the emitter electrode elements and coated micropoints thereon is subject to processing according to a deposition, CMP process, and wet chemical etching method of the present invention. This method will permit the micropoints formed on the emitter electrode elements to retain their size and sharpness and have improved performance in opera- tion in the large-area FED of the present invention.
• the micropoints may be coated at any of a variety of steps in the formation process.
• the micropoints may be coated by any suitable method after completion of the cathode, such as ion implantation or deposition.
• micropoints formed on the emitter electrode elements at the predetermined locations. For example, in Figure 2 at representative location 207, a square pattern of 15 x 15 may be provided. This pattern of micropoints is spaced from the adjacent patterns of micropoints on the emitter electrode elements.
• micropoints 310 are shown disposed on emitter electrode element 204, which, in turn, is disposed in substrate 202. These micropoints are part of a 5 x 5 pattern of micropoints. Although only square patterns of micropoints have been described, other patterns may be used and still be within the scope of the present invention.
• Insulating layer 302 5 electrically insulates the positive electrical elements of the large-area FED from the negative emitter electrode.
• insulating layer 302 is formed from silicon dioxide (SiO 2 ).
• Conductive layer 304 surrounds the micropoints for the purpose of causing an electron emission stream to be emitted from the micropoints.
• conductive layer 304 is a series of electrically connected, parallel strips disposed on insulating layer 15 302. The strips are shown as 305 in Figure 2.
• Conductive layer 304 serves as an extraction structure and, hereafter, will be referred to as such.
• ITO layer 308 is disposed on the bottom surface of faceplate 306 which faces extraction structure 304.
• ITO layer 308 is a layer of electrically conductive material that may be disposed as a separate layer on faceplate 306 or made as part of the faceplate.
• ITO layer 308, in any case, is transparent to the light from cathodoluminescent photons 25 and serves as the anode for the FED.
• pixel 318 is shown disposed on the surface of ITO layer 308 facing extraction structure 304. As is shown, pixel 318 is disposed above a pattern of micropoints. More particularly, pixel 318 is associated with a 5 x 5 pattern of micropoints 310. 30 The pixel areas have phosphor material 320 deposited on the bottom of ITO layer 308 in a desired pattern. Generally, the pixel areas, such as 318, are square in shape, however, if desired, other shapes may be used. The phosphor material that is used is preferably one that can be excited by low energy electrons. Preferably, the response time for the phosphor material should be in the range equal to or less than 2 ms.
• Black matrix 322 may be of any suitable material.
• the material should be opaque to the transmission of light and not affected by electron bombardment.
• An example of a suitable material is cobalt oxide.
• Faceplate 306 is spaced away from substrate 202. This is a predetermined distance usually in the 200-1000 ⁇ m range. This spacing is maintained by spacers which are shown generally as spacers 330 in Figure 2, and, more specifically, as spacers 332 and 334 in Figure 3.
• the area between faceplate 306 and substrate 202 preferably, is under high vacuum.
• the large-area FED of the present invention is connected to a power source or multiple power sources for powering the emitter electrode, electron emitter structure, and ITO so that electron streams are emitted from the micropoints directed to the pixels.
• Spacers that normally are placed in FEDs with diagonal screen sizes in the 5-8 inch range are in the form of cylindrical columns. These columns have the same height and are placed at various locations between the anode and cathode. In larger area FEDs, cyndrical spacers are not optimal and spacers with different cross-sectional configuration may be preferred.
• spacers such as spacers 332 and 334, are placed in patterns between insulating layer 302 or extraction structure 304, and ITO layer 308. These spacers are placed between the cathode and anode in such a manner that the FED is sectioned according to the patterns of the spacers.
• Fig- ure 2 which is a portion of the large-area FED near the center of the FED, there are a large number of spacers shown to maintain the anode/cathode separation. Other areas will have different patterns to maintain the desired separation.
• the spacers are in various patterns depending of area of interest within the large-area FED, even though they are cylindrical columns.
• Spacers that may be used with respect to the present invention may be formed according to U.S. Patent Nos. 5,100,838; 5,205,770; 5,232,549; 5,232,863; 5,405,791; 5,433,794; 5,486,126; and 5,492,234.
• Figure 4A, 4B, 4C and 4D show four cross-sectional shapes for spacers that may be used for large-area FEDs.
• Figure 4A at 402 shows a side and cross- sectional view of a "+" shaped spacer
• Figure 4B at 404 shows a side and cross-sectional view of a "L" shaped spacer
• Figure 4C at 406 shows a side and cross-sectional view of a square shaped spacer
• Figure 4D at 408 shows a side and cross-sectional view of an "I- beam" shaped spacer.
• the spacers at various locations in the large-area FED also may have differ- ent lengths to maintain uniform separation between the anode and cathode across the entire area of the large-area FED.
• the spacers near the center of the large-area FED may be slightly longer than the spacers near the edges.
• the spacers between these two extremes may be graded in length to transition from the shortest spacers at the edge to the longest near the center.
• the different length spacers will compensate for the slight sag- gings in the faceplate due to the high vacuum within the FED that occurs near the center that does not occur near edges because near the edges, the FED wall structure adds substantial support to the faceplate.
• the process according to the present invention will be described.
• the electrically connected emitter electrode elements 204 are formed in substrate 202
• the patterns of micropoints 310 are formed on these elements.
• the forming of the micropoints by a separate processing step provides greater control over formation of the micropoints and greater uniformity in the size of the micropoints across the entire large area of the large-area FED.
• the micropoints that are formed have a substantially inverted conical shape as shown in Figure 5A.
• the micropoints preferably are formed from silicon.
• a suitable low work function material is placed on the micropoints. This coating will be applied to at least the tips of the micropoints.
• Suitable low work func- tion materials are cermet (Cr 3 Si+Si ⁇ 2 ), cesium, rubidium, tantalum nitride, barium, chromium suicide, titanium carbide, and niobium. These are deposited on the micropoints using conventional semiconductor processing methods, such as vapor deposition, or according to the preferred method described below. It is understood that other suitable materials also may be used.
• the low work function material that is used to treat the micropoints is cesium.
• the cesium preferably is implanted on the micropoints with very low energy and at high doses.
• conductive layer 304 is deposited on insulating layer 302 as shown in Figure 5B.
• conductive layer 304 is made from amorphous silicon or polysilicon.
• the thickness of the insulating and conductive layers is selected so that the total layer thickness is greater than the height of the original micropoint. The process of the present invention allows for flexibility in material selection for the micropoints, and the insulating and conductive layers, even though silicon is the preferred material for the micropoints, and conductive layer.
• a conductor with the lowest resistance e.g., gold, silver, aluminum, copper, or other suitable material, and make the conductor thick, e.g., > 0.2 ⁇ m, or in some way increase the cross-sectional area of the line that is acting as the conductor.

Landscapes

• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
• Manufacture Of Electron Tubes, Discharge Lamp Vessels, Lead-In Wires, And The Like (AREA)
• Vessels, Lead-In Wires, Accessory Apparatuses For Cathode-Ray Tubes (AREA)
• Diaphragms For Electromechanical Transducers (AREA)
• Separation By Low-Temperature Treatments (AREA)
• Gas-Filled Discharge Tubes (AREA)
• Luminescent Compositions (AREA)

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• 1998
  • 1998-02-27 US US09/032,127 patent/US6255772B1/en not_active Expired - Lifetime
• 1999
  • 1999-02-26 KR KR1020007009573A patent/KR100597056B1/ko not_active Expired - Fee Related
  • 1999-02-26 AT AT99909683T patent/ATE249096T1/de not_active IP Right Cessation
  • 1999-02-26 EP EP99909683A patent/EP1057200B1/en not_active Expired - Lifetime
  • 1999-02-26 WO PCT/US1999/004382 patent/WO1999044218A1/en not_active Ceased
  • 1999-02-26 AU AU28836/99A patent/AU2883699A/en not_active Abandoned
  • 1999-02-26 JP JP2000533887A patent/JP4001460B2/ja not_active Expired - Fee Related
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• 2001
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• 2002
  • 2002-10-02 US US10/262,747 patent/US7033238B2/en not_active Expired - Fee Related
• 2006
  • 2006-04-17 US US11/405,112 patent/US7462088B2/en not_active Expired - Fee Related

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