WO1999025019A1 - Procede d'amincissement de plaquettes en semi-conducteur a circuits et plaquettes ainsi produites - Google Patents

Procede d'amincissement de plaquettes en semi-conducteur a circuits et plaquettes ainsi produites Download PDF

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Publication number
WO1999025019A1
WO1999025019A1 PCT/US1998/023929 US9823929W WO9925019A1 WO 1999025019 A1 WO1999025019 A1 WO 1999025019A1 US 9823929 W US9823929 W US 9823929W WO 9925019 A1 WO9925019 A1 WO 9925019A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
front surface
substrate
grooves
dies
Prior art date
Application number
PCT/US1998/023929
Other languages
English (en)
Inventor
Douglas M. Albert
Volkan H. Ozguz
Original Assignee
Irvine Sensors Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Irvine Sensors Corporation filed Critical Irvine Sensors Corporation
Priority to JP2000519921A priority Critical patent/JP2001523046A/ja
Priority to EP98957755A priority patent/EP1038315A4/fr
Publication of WO1999025019A1 publication Critical patent/WO1999025019A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)

Abstract

Des puces (34) de circuit intégré amincies et/ou flexibles sont fabriquées par définition d'une pluralité de rainures (30) dans la surface avant d'une plaquette (22) en semi-conducteur. Les rainures (30) isolent chaque circuit intégré dans une puce séparée. Les rainures tracées s'étendent uniquement partiellement dans la surface avant dans laquelle les circuits sont formés, typiquement de 50 microns ou moins (32). Une couche d'aplanissement et de soulagement des contraintes en polyimide est disposée sur la surface avant avant formation des rainures. Un adhésif à faible viscosité et faible contrainte est déposé sur la surface rainurée revêtue de polyimide. La plaquette est ensuite collée à la surface marquée d'un substrat en verre optiquement plat sous pression et à une température de durcissement. L'ensemble est ensuite monté sur une meule laquelle élimine la partie arrière de la plaquette jusqu'à mise à nu des rainures. Le meulage s'effectue par avance à une vitesse de meulage décroissante suivie de périodes de passage. Les rainures dans la plaquette en semi-conduceur tendent à inhiber la formation de fissures. L'ensemble est ensuite placé verso vers le bas sur un bloc à broche dans un bain de solvant. Le solvant dissout la couche adhésive laissant les puces séparées du bloc à broche pour un montage sur une couche mince flexible. Les puces sont couplées à des métallisations sur la couche mince flexible au moyen d'un epoxy conducteur et scellées à l'aide d'un revêtement flexible.
PCT/US1998/023929 1997-11-11 1998-11-10 Procede d'amincissement de plaquettes en semi-conducteur a circuits et plaquettes ainsi produites WO1999025019A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000519921A JP2001523046A (ja) 1997-11-11 1998-11-10 回路を備える半導体ウェハをシンニングするための方法および同方法によって作られるウェハ
EP98957755A EP1038315A4 (fr) 1997-11-11 1998-11-10 Procede d'amincissement de plaquettes en semi-conducteur a circuits et plaquettes ainsi produites

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US6508897P 1997-11-11 1997-11-11
US60/065,088 1997-11-11

Publications (1)

Publication Number Publication Date
WO1999025019A1 true WO1999025019A1 (fr) 1999-05-20

Family

ID=22060262

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/023929 WO1999025019A1 (fr) 1997-11-11 1998-11-10 Procede d'amincissement de plaquettes en semi-conducteur a circuits et plaquettes ainsi produites

Country Status (3)

Country Link
EP (1) EP1038315A4 (fr)
JP (1) JP2001523046A (fr)
WO (1) WO1999025019A1 (fr)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001003180A1 (fr) * 1999-07-01 2001-01-11 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. Procede de separation d'une plaquette de silicium
WO2001088970A1 (fr) * 2000-05-16 2001-11-22 Shin-Etsu Handotai Co.,Ltd. Procede permettant d'amincir une tranche semi-conductrice et tranche semi-conductrice mince
DE10063794A1 (de) * 2000-12-21 2002-06-27 E & E Elektronik Gmbh Verfahren zur Herstellung von Dünnschichtsensoren, insbesondere Heissfilmanemometern
US6656819B1 (en) * 1999-11-30 2003-12-02 Lintec Corporation Process for producing semiconductor device
EP1388890A1 (fr) * 2002-01-25 2004-02-11 Matsushita Electric Industrial Co., Ltd. Procede servant a fabriquer un composant electronique
DE10238444A1 (de) * 2002-08-22 2004-03-04 United Monolithic Semiconductors Gmbh Verfahren zur Herstellung von vereinzelten monolithisch integrierten Halbleiterschaltungen
DE10258509A1 (de) * 2002-12-14 2004-07-08 Infineon Technologies Ag Verfahren zur Herstellung eines bruchfesten scheibenförmigen Gegenstandes
EP1451873A2 (fr) * 2001-07-16 2004-09-01 Irvine Sensors Corporation Biomoniteur portable a circuit integre mince souple
US6841027B2 (en) 2000-10-20 2005-01-11 Süss MicroTec Laboratory Equipment GmbH Method for applying a substrate
US7041577B2 (en) 2002-04-30 2006-05-09 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for manufacturing a substrate and associated substrate
DE102004052921A1 (de) * 2004-10-29 2006-05-11 Infineon Technologies Ag Verfahren zur Herstellung von Halbleiterbauelementen mit externen Kontaktierungen
US7078320B2 (en) 2004-08-10 2006-07-18 International Business Machines Corporation Partial wafer bonding and dicing
US7786562B2 (en) 1997-11-11 2010-08-31 Volkan Ozguz Stackable semiconductor chip layer comprising prefabricated trench interconnect vias
US7960247B2 (en) 2008-04-04 2011-06-14 The Charles Stark Draper Laboratory, Inc. Die thinning processes and structures
EP2715780A1 (fr) * 2011-05-27 2014-04-09 Corning Incorporated Plaquette de verre non polie, système d'amincissement et procédé pour utiliser celle-ci afin d'amincir un semi-conducteur étagé
CN113013061A (zh) * 2021-02-23 2021-06-22 绍兴同芯成集成电路有限公司 一种利用有机薄膜进行化合物半导体加工的方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5202754A (en) * 1991-09-13 1993-04-13 International Business Machines Corporation Three-dimensional multichip packages and methods of fabrication
US5393706A (en) * 1993-01-07 1995-02-28 Texas Instruments Incorporated Integrated partial sawing process

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4023260A (en) * 1976-03-05 1977-05-17 Bell Telephone Laboratories, Incorporated Method of manufacturing semiconductor diodes for use in millimeter-wave circuits
DE3043903A1 (de) * 1980-11-21 1982-07-01 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung von kontaktverbindungen, insbesondere fuer mesfets
JPH0215652A (ja) * 1988-07-01 1990-01-19 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5185292A (en) * 1989-07-20 1993-02-09 Harris Corporation Process for forming extremely thin edge-connectable integrated circuit structure
JPH0574934A (ja) * 1991-09-13 1993-03-26 Sony Corp 薄型チツプの形成方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5202754A (en) * 1991-09-13 1993-04-13 International Business Machines Corporation Three-dimensional multichip packages and methods of fabrication
US5393706A (en) * 1993-01-07 1995-02-28 Texas Instruments Incorporated Integrated partial sawing process

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1038315A4 *

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7786562B2 (en) 1997-11-11 2010-08-31 Volkan Ozguz Stackable semiconductor chip layer comprising prefabricated trench interconnect vias
US6756288B1 (en) 1999-07-01 2004-06-29 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Method of subdividing a wafer
WO2001003180A1 (fr) * 1999-07-01 2001-01-11 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. Procede de separation d'une plaquette de silicium
US6656819B1 (en) * 1999-11-30 2003-12-02 Lintec Corporation Process for producing semiconductor device
WO2001088970A1 (fr) * 2000-05-16 2001-11-22 Shin-Etsu Handotai Co.,Ltd. Procede permettant d'amincir une tranche semi-conductrice et tranche semi-conductrice mince
US6930023B2 (en) 2000-05-16 2005-08-16 Shin-Etsu Handotai Co, Ltd. Semiconductor wafer thinning method, and thin semiconductor wafer
US6841027B2 (en) 2000-10-20 2005-01-11 Süss MicroTec Laboratory Equipment GmbH Method for applying a substrate
DE10063794A1 (de) * 2000-12-21 2002-06-27 E & E Elektronik Gmbh Verfahren zur Herstellung von Dünnschichtsensoren, insbesondere Heissfilmanemometern
EP1451873A2 (fr) * 2001-07-16 2004-09-01 Irvine Sensors Corporation Biomoniteur portable a circuit integre mince souple
EP1451873A4 (fr) * 2001-07-16 2007-01-17 Irvine Sensors Corp Biomoniteur portable a circuit integre mince souple
EP1388890A1 (fr) * 2002-01-25 2004-02-11 Matsushita Electric Industrial Co., Ltd. Procede servant a fabriquer un composant electronique
EP1388890A4 (fr) * 2002-01-25 2007-10-31 Matsushita Electric Ind Co Ltd Procede servant a fabriquer un composant electronique
US7041577B2 (en) 2002-04-30 2006-05-09 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for manufacturing a substrate and associated substrate
DE10238444A1 (de) * 2002-08-22 2004-03-04 United Monolithic Semiconductors Gmbh Verfahren zur Herstellung von vereinzelten monolithisch integrierten Halbleiterschaltungen
US7084047B2 (en) 2002-08-22 2006-08-01 United Monolithic Semiconductors Gmbh Method for the production of individual monolithically integrated semiconductor circuits
DE10238444B4 (de) * 2002-08-22 2011-05-12 United Monolithic Semiconductors Gmbh Verfahren zur Herstellung von vereinzelten monolithisch integrierten Halbleiterschaltungen
DE10258509A1 (de) * 2002-12-14 2004-07-08 Infineon Technologies Ag Verfahren zur Herstellung eines bruchfesten scheibenförmigen Gegenstandes
DE10258509B4 (de) * 2002-12-14 2005-10-20 Infineon Technologies Ag Verfahren zur Herstellung eines dünnen bruchfesten Halbleiterwafers
US7078320B2 (en) 2004-08-10 2006-07-18 International Business Machines Corporation Partial wafer bonding and dicing
DE102004052921A1 (de) * 2004-10-29 2006-05-11 Infineon Technologies Ag Verfahren zur Herstellung von Halbleiterbauelementen mit externen Kontaktierungen
US7960247B2 (en) 2008-04-04 2011-06-14 The Charles Stark Draper Laboratory, Inc. Die thinning processes and structures
EP2715780A1 (fr) * 2011-05-27 2014-04-09 Corning Incorporated Plaquette de verre non polie, système d'amincissement et procédé pour utiliser celle-ci afin d'amincir un semi-conducteur étagé
EP2715780A4 (fr) * 2011-05-27 2014-11-19 Corning Inc Plaquette de verre non polie, système d'amincissement et procédé pour utiliser celle-ci afin d'amincir un semi-conducteur étagé
US9227295B2 (en) 2011-05-27 2016-01-05 Corning Incorporated Non-polished glass wafer, thinning system and method for using the non-polished glass wafer to thin a semiconductor wafer
US9573835B2 (en) 2011-05-27 2017-02-21 Corning Incorporated Non-polished glass wafer, thinning system and method for using the non-polished glass wafer to thin a semiconductor wafer
CN113013061A (zh) * 2021-02-23 2021-06-22 绍兴同芯成集成电路有限公司 一种利用有机薄膜进行化合物半导体加工的方法
CN113013061B (zh) * 2021-02-23 2023-06-02 绍兴同芯成集成电路有限公司 一种利用有机薄膜进行化合物半导体加工的方法

Also Published As

Publication number Publication date
EP1038315A1 (fr) 2000-09-27
JP2001523046A (ja) 2001-11-20
EP1038315A4 (fr) 2001-07-11

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