EP1038315A1 - Procede d'amincissement de plaquettes en semi-conducteur a circuits et plaquettes ainsi produites - Google Patents

Procede d'amincissement de plaquettes en semi-conducteur a circuits et plaquettes ainsi produites

Info

Publication number
EP1038315A1
EP1038315A1 EP98957755A EP98957755A EP1038315A1 EP 1038315 A1 EP1038315 A1 EP 1038315A1 EP 98957755 A EP98957755 A EP 98957755A EP 98957755 A EP98957755 A EP 98957755A EP 1038315 A1 EP1038315 A1 EP 1038315A1
Authority
EP
European Patent Office
Prior art keywords
wafer
front surface
substrate
grooves
dies
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98957755A
Other languages
German (de)
English (en)
Other versions
EP1038315A4 (fr
Inventor
Douglas M. Albert
Volkan H. Ozguz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Irvine Sensors Corp
Original Assignee
Irvine Sensors Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Irvine Sensors Corp filed Critical Irvine Sensors Corp
Publication of EP1038315A1 publication Critical patent/EP1038315A1/fr
Publication of EP1038315A4 publication Critical patent/EP1038315A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Definitions

  • the field of endeavor of the invention relates to a method of thinning a semiconductor layer containing electronic circuits and the wafers made by such a method.
  • Silicon wafer thinning has been practiced in packaging technologies to reduce package thickness or to provide for a limited degree of flexibility for use in flexible electronic cards or smart cards. Examples of such manufacturing methods can be seen in Flesher, et al., "Flexible Electronic Card and Method, " U.S. Patent 5,733,814 (1998). Flesher, however, is typical of the prior art processes wherein the backside of the wafer is mechanically ground before dicing the wafer to extract the semiconductor devices which are fabricated in the front side. Typically, the grinding process induces stresses in the wafer causing it to warp. The warped wafers are more likely to break during dicing as well as to disintegrate or fracture during the grinding process itself.
  • Flesher describes a modification of a mounting process to allow for back grinding, but still dices the wafers after the grinding and polishing of the back side of the wafer has been completed.
  • the minimum thickness of the wafers reported in Flesher still exceeds 200 microns thick even for the thinnest wafers manufacturable according to Flesher's process.
  • dies made by Flesher's method may be suited for use within thick packages or a unreinforced credit card which is subject to oniy slight bending, wafers of this thickness are still too thick and friable to be mounted on flexible film
  • Another prior art method for thinning wafers involves various types of methods for chemically etching away the back of the wafer such as described by Clifton, et al., "Method for Fabricating Thin, Strong, Flexible Die for Smart
  • the invention is a method for manufacturing a plurality of thinned integrated circuits from a semiconductor wafer having a thickness, a front surface and a backside surface.
  • the wafer has a plurality of integrated circuits conventionally prefabricated in its front side.
  • the circuits are organized into regions or dies which are separated by die streets which have been prescribed on the wafer.
  • the method comprises the steps of defining a plurality of grooves into the die streets in the front side of the wafer.
  • the grooves are allowed to penetrate into the surface by a predetermined distance which is less than the thickness of the semiconductor wafer so that the plurality of dies remain integral with the wafer.
  • the grooves have a predetermined depth designed to provide stress relief in the following grinding step, which depth is equal to or greater than the final thickness of the thinned dies.
  • the grooved wafer is mounted face down onto a flat rigid substrate which supports the wafer, i.e. the front side toward the substrate.
  • the wafer is mounted to the substrate with the front surface turned toward the substrate.
  • a predetermined portion of the backside of the wafer is mechanically removed until the thickness of the wafer is reduced to expose the plurality of grooves from the backside in preparation to separating the plurality of the dies.
  • the dies remain mounted to the substrate.
  • the plurality of dies are then released from the substrate.
  • the method further comprises the step of disposing a pianarizing layer of low stress material on the front surface of the wafer into which the plurality of grooves have been defined prior to defining the grooves into the front surface of the wafer.
  • the method further comprises the step of disposing a layer of low stress, low viscosity adhesive material on the front surface of the wafer into which the plurality of grooves have been defined prior to mounting the front surface of the wafer to the flat substrate.
  • the step of mounting the flat substrate to the front surface of the wafer comprises affixing an optically flat substrate to the front surface of the wafer.
  • the substrate has vertical variations of approximately one micron or less across its horizontal surface.
  • the method comprises in particular the step of disposing a polyimide layer on the front surface before the grooves had been defined therein and prior to mounting to the flat substrate, so that the polyimide layer absorbs stress induced into the wafer when mechanically removing a portion of the wafer.
  • the step of defining the plurality of the grooves in the wafer comprises defining grooves approximately 25 - 50 microns or less into the front surface of the wafer.
  • the step of mechanically removing a portion of the wafer removes the backside portion of the wafer until the wafer has a thickness of 50 microns or less.
  • the step of releasing the plurality of dies comprises disposing the thinned backside surface of the wafer onto a pin block and dissolving the adhesive layer, thereby leaving the plurality of separated poiyimide-coated dies on the pin block.
  • the method further comprises mounting the dies onto a flexible film and sealing the die mounted on the flexible film.
  • the integrated circuit in the die is coupled to metalizations provided on the film.
  • the die is disposed with the front surface in contact with the metalizations on the film and coupled thereto by means of anisotropic conductive epoxy.
  • the step of mounting the wafer to the substrate comprises affixing the front surface of the wafer to substrate on a surface of the substrate provided with a plurality of grooves defined in the substrate to facilitate the flow of adhesive material across the surface of the substrate between the surface of the substrate and the front surface of the wafer.
  • the wafer and substrate are pressed together with a low viscosity and low stress material therebetween and the material cured while the pressure is maintained between the wafer and substrate.
  • the step of mechanically removing the wafer comprises grinding the backside portion of the wafer with at least one cycle of a predetermined grinding advance rate followed by a nonadvancing dwell.
  • the grinding cycle is repeated two or more times with at least one reduction in the advance rate.
  • the method further comprises the step of polishing the thinned backside surface of the wafer by a dry chemical etch having an etch rate of less than one micron per minute.
  • the invention can also be characterized as an intermediate work product produced in a manufacturing process of thinning dies.
  • the intermediate product is an assembly used for manufacturing a plurality of flexible integrated circuits from a semiconductor wafer having a thickness, a front surface and a backside surface.
  • the assembly comprises a plurality of grooves defined into the front surface of the semiconductor wafer to define the plurality of dies.
  • the grooves penetrate into the front surface a predetermined distance which is less than the thickness of the semiconductor wafer so that the plurality of dies remain integral with the wafer.
  • a flat rigid substrate is mounted to the wafer to support the wafer.
  • the wafer is mounted to the substrate with the front surface turned toward the substrate and to expose the backside of the wafer for partial mechanical removal of the backside by an amount sufficient to expose the plurality of grooves to the backside in preparation to separating the plurality of the dies.
  • the dies remain mounted to the substrate.
  • Fig 1 is a perspective view of a glass substrate used in the method of the invention to support the wafer as it is thinned
  • Fig. 2 is a side cross-sectional view in enlarged scale of a portion of a wafer showing the stress-relief grooves defined into the front surface
  • Fig. 3 is a side elevational view of a wafer of Fig. 2 mounted on the substrate of Fig. 1 to form an assembly, which can be used for holding the wafer as its back side is ground.
  • Fig. 4 is a side cross-sectional view of the assembly of Fig. 3 after grinding showing the detachment of the thinned wafer from the substrate of Fig. 1
  • Fig. 5 is a side cross-sectional of the thinned wafer obtained by the method of the invention shown mounted on a flexible film.
  • a conventional silicon wafer, having integrated circuits formed into its upper surface, can be successfully thinned to 50 microns or less using a conventional, mechanical grinding apparatus, if performed by the method of the present invention
  • wafer Prior to grinding, wafer is partially grooved or scored to create scribed grooves to a depth at least as deep or deeper than the final thickness desired in the thinned wafer
  • the grooves in the front surface provide stress relief and/or barriers to cracking Any cracks or stress built up during the mechanical grinding operation should they occur, propagate only to the edge of the nearest die street where the stress is relieved by breakage or crack termination
  • the silicon wafer is mounted on grooved or scored optically flat giass substrate with the front surface of the wafer bonded to the flat glass substrate using low viscosity, low stress bonding materials, such as a low stress adhesive
  • the thickness of the substrate bonding material and the surface variations of substrate is within plus or minus 0 1 micron
  • the use of the bonding materials eliminates affects arising from the nonuniformity of the surface topology of the integrated circuits of the silicon wafer
  • the back surface of the silicon wafer is then ground according to the methodology described in greater detail below
  • the wafer is then thinned to 50 microns thickness or less by grinding down the back side of the mounted wafer
  • the grooves are ultimately exposed to result in an automatic separation of the dies mounted on the substrate
  • the polyimide layer disposed on the front surface of wafer also provides stress relief What results is a thinned integrated circuit chips fabricated by defining a plurality of grooves into the surface of a semiconductor wafer into which the integrated circuits are defined
  • the grid of grooves isolates each integrated circuit into a separate chip or die
  • the grooves are extended only partially into the silicon, typically 50 microns by using conventional dicing or chemomechanical methods
  • the grooved wafer is then coated with a pianarizing and stress relieving layer on the front surface of the wafer, which is that side of the wafer into which the circuits have been fabricated
  • the coated front surface wafer is then bonded with a low stress adhesive under pressure and at a
  • the dies may be coupled to metalizations on the flexible film by means of a conductive epoxy and sealed using a flexible coating
  • Fig 1 wherein the grooved, optically flat substrate 10 used in the methodology of the invention is shown in perspective view
  • Substrate 10 is formed of an optically flat glass disc of thickness 12, typically in the range of 0 5 to 1 5 cm
  • Upper surface 14 of substrate 10 is prepared so that it is optically flat, typically plus or minus 0 1 micron in variation from any one point on surface 14 to any other point
  • optically flat includes surfaces in which the surface variations may be constrained to the range of approximately ⁇ /2 to ⁇ /20 or flatter, where ⁇ is the wavelength of light used as a standard of measurement
  • Opposing surface 16 (not visible in Fig 1 ) is similarly prepared to be parallel and optically flat to surface 14
  • Substrate 10 is rigid and has a diameter sufficient to
  • groove depth and center to center spacing of grooves 18 is variable and the illustrated embodiment groove depth is in the range of 75 to 125 microns with a groove width of 125 to 250 microns Grooves are spaced apart from each other on 1 ,250 micron centers These numerical examples are choosing only for illustration and any other shape, dimension or spacing may be used in the invention as may be desired and expedient Grooves 18 run across the entire surface 14 with a second set of orthogonal grooves perpendicular to the first set to create a grid or checkerboard pattern
  • the topology of grooves 18, their thickness and spacing is not critical to the invention provided that grooves 18 provide a means wherein a low viscosity low stress bonding material later disposed on surface 14 is free to propagate or flow on surface 14 as facilitated by grooves 18 to form a layer of uniform thickness.
  • Fig. 2 is a side cross-sectional view of wafer 20 in which front surface 24 of wafer 20 has been partially diced to form a plurality of grooves 30 into surface 24.
  • Grooves 30 define dies 34 in surface 24 in which the integrated circuit has been formed. Thus, each die 34 will ultimately form a separate integrated circuit chip.
  • Grooves 30 have a depth 32 equal to or slightly exceeding the final thickness desired for wafer 20 after thinning.
  • grooves 30 in the illustrated embodiment have a depth 32 in the range of 10 to 75 microns.
  • the total thickness 36 of wafer 20 before thinning typically is in the range of 500 to 1000 microns.
  • the pattern formed by grooves 30 is thus dictated by the chip size and geometry and is otherwise conventional.
  • Die street 30 may be created by any method now known or later devised, such as photolithographic etching or mechanical grinding with a diamond saw wheel.
  • Surface 24 is provided first with a polyimide layer 26 and then partial diced to create grooves 30 on surface 24, and then an adhesive layer 28 as described below in connection with Fig. 3 is disposed on the grooved poiyimide-coated surface 24.
  • grooves 30 form a grid of trenches or grooves of about 25 to 50 microns in depth around each die 34 on front surface 24 of each die.
  • Grooves 30 typically follow the streets of wafer 20 as manufactured as an integrated circuit wafer.
  • Grooves 30 are made by photolithographic etchings or scribings. The use of a photolithographic etch will aliow the formation of die 34 with smooth edges and will tend to eliminate chipping or cracking that may result from a standard wheel based dicing.
  • wafer 20 is then thinned to 25 microns from backside 22 and grooves 30 will be exposed to automatically separate dies 34 on wafer 20 when released from substrate 10.
  • formation grooves 30 act as a means for stress relief during thinning of wafer 20 by eliminating crack formation, or, if a crack is formed, by restricting its propagation within a single die boundary
  • Fig. 3 is a side cross-sectional view of substrate 10 shown mounted to silicon wafer 20.
  • Backside 22 of silicon wafer is exposed while its front surface 24 is coated with a polyimide layer 26.
  • the thickness of polyimide layer 26 is approximately 4 to 8 microns and is disposed on surface 24 on wafer 20 by spinning, spraying or film forming.
  • the function of polyimide layer 26 is to provide a degree of plana ⁇ zation for the front surface 24 of wafer 20 and to act as a stress relieving layer
  • An adhesive layer 28 of approximately 10 microns thickness is disposed on polyimide layer 24 by spraying or spinning.
  • Wafer 20 is then mounted on surface 14 of substrate 10 using a press at a regulated pressure and temperature.
  • a 6 inch diameter wafer 20 of about 70 psi applied for about 5 minutes at about 23°C forces the assembly 38 of Fig. 3 together so as to spread and cure adhesive layer 28 in order to provide a secure bond of wafer 22 substrate 10 with a uniform thickness. Any excess bonding material squeezed out from between wafer 20 and substrate 10 can then be manually removed with a razor blade. Grooves 18 in substrate 10 provide a means whereby adhesive 28 and polyimide layer 24 may flow and be distributed across surface 14 so that backside surface 22 of wafer 20 is parallel to surfaces 14 and 16 of substrate 10 in preparation for the following grinding operation. After wafer 20 is securely mounted to substrate 10 as described in connection with Fig. 3, assembly 38 of Fig.
  • a course grind is first performed on backside 22 at a rate of about 3 microns per second until reaching the desired set point using a 40/60 micron diamond grit wheel at about 2500 rpm. The grinding rate is then slowed to about 1 micron per second for the next 10 microns of grind. The grinding wheel is then held in a stationary or dwell position for about 10 seconds, which has been found according to the invention to further provides stress relief.
  • a conventional mechanical grinding machine such as Model 7AA manufactured by R.H.Strausbaugh of San Luis Obispo, California.
  • a course grind is first performed on backside 22 at a rate of about 3 microns per second until reaching the desired set point using a 40/60 micron diamond grit wheel at about 2500 rpm. The grinding rate is then slowed to about 1 micron per second for the next 10 microns of grind. The grinding wheel is then held in a stationary or dwell position for about 10 seconds, which has been found according to the invention to further provides stress relief.
  • thin backside 22 is then ground or polished with a finer grinding wheel, such as 4/6 micron grit diamond wheel at 4350 rpm.
  • the final grinding cycles are again performed at predetermined advance rates followed by dwell times until the finai wafer thickness 36 of 50 microns or less is obtained.
  • the numerical examples have been set forth only to illustrate the invention, which is not to be taken as limited by the numerical example given.
  • the grinding rates, wheel speeds and grits may change if a different wafer grinder is used.
  • Assembly 38 of Fig. 3 is then removed from the grinding machine and wafer 20 demounted.
  • Wafer 20 is demounted by immersing assembly 38 into a solvent, such as acetone which serves to dissolve adhesive layer 28 as shown in Fig. 4.
  • Grooves 30 may be partially or completely filled with adhesive layer 28 which is dissolved by warm solvent 40.
  • Assembly 38 is placed upon a pin block 42 which is provided with a plurality of pins or apexes 44 on its upper surface so that the backside layer 22 of thin wafer 20 is in contact with pin block 42 only in a plurality of small areal points. This prevents any substantial liquid surface tension from being created between dies 34 and pin block 42. If surface tension had been allowed to develop between pin block 42 and die 34, thinness of dies 34 is such that any attempt to remove die 34 from pin block 42 would subject die 34 to substantial stresses resulting in a high probability of breakage.
  • Solvent 40 dissolves away adhesive layer 28 from substrate 10, which can then be gently shaken to separate the plurality of dies 34 from substrate 10. Dies 34 are then left, each separated from the other in their original position on points 44 of pin block 42 Dies 34 are then individually removed from pin block 42 using vacuum tweezers or other means and placed in chip carriers and handled or processed in a conventional manner
  • a backside dry or wet etching is avoided in the present invention to eliminate the damage to the circuits in front side 24. Dry etching from backside 22 of wafer 20 may create defects due to the close proximity of the active layers and front surface 24 Wet etching of backside 24 leaves etch pits and enhances the propagation of microcracks Nevertheless, a final touch up chemical etch with a very slow silicon etch of less than one micron per minute may optionally be used in some cases
  • the thin flexible dies 34 are attached to conventional Kapton cable and interconnected to the cable using metal depositions.
  • Kapton film 46 in Fig. 5 is conventional 25 micron thick film using quarter ounce laminated substrates.
  • Single dies 34 mounted on film 46 are capable of flexing to radii of curvature of less than 20 millimeters without breaking Multiple numbers of the thinned die 34 may be stacked by providing additional passivation layers on dies 34 and metalizations on top of die 34 Lead connections to dies 34 are provided on the side of die 34, which result in pad pitches as low as 3 mils.
  • the thinnest dies 34 also allow for clear visualization of circuit layers in die 34 thereby creating an opportunity for optical quality control of the multiple layers of the finished die.
  • the opaque metalizations are dearly delineated against the illuminated translucent silicon when die 34 is back lit.
  • Thin die 34 can be electrically connected to flexible Kapton carrier using z-bonding as shown in Fig. 5.
  • Die 34 is bonded to Kapton film 46 through the use of a z-conductive epoxy 48.
  • Z-conductive epoxy is preferred because it allows the die-to-substrate connection process to be simplified and the adhesive properties of the epoxy support die 34.
  • thermoplastic z-conductive adhesive manufactured by A.I. Technologies under the part no. ZSP8150-FP has been used. This particular epoxy can support line pitches in the range of 2 - 6 mils. When cured, its thickness is less than 0.5 mils and is characterized as a film. Because thin die 34, z-conductive epoxy 48 and Kapton film 46 are all transparent, die 34 can be easily aligned so that its circuit metalizations 50 are matched with conforming metalizations 52 on the opposing surface 54 of Kapton film 46.
  • a flexible seal such as additionally adhesively disposed Kapton layers or sprayed coatings.
  • different materials may be chosen for film 46.
  • Inorganic coatings which are deposited, sprayed, sputtered or evaporated on to film 46 and die 34 are also possible as seals.
  • circuit die 34 having a thickness of 50 microns or less, circuits can be mounted on flexible plastic fiims and bent into nonpianar shapes without significant danger of fracture
  • Thin circuit chips devised according to the invention can tolerate more stress in packaging and in operation because of this flexibility
  • the minimum mass in die 34 results in a mechanical stability of the integrated circuit under high acceleration loads and shocks.
  • High frequency electrical performance of the circuit is also enhanced, since parasitic capacitance in the substrate is reduced or eliminated Radiation tolerance of the circuit is also improved, since the carrier generation volume is minimized
  • the flexibility of circuits is exploited where space is a premium and odd shapes need to be obtained such as in rollup displays, wrist worn electronic products, shaped conforming sensors and flexible smart cards.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)

Abstract

Des puces (34) de circuit intégré amincies et/ou flexibles sont fabriquées par définition d'une pluralité de rainures (30) dans la surface avant d'une plaquette (22) en semi-conducteur. Les rainures (30) isolent chaque circuit intégré dans une puce séparée. Les rainures tracées s'étendent uniquement partiellement dans la surface avant dans laquelle les circuits sont formés, typiquement de 50 microns ou moins (32). Une couche d'aplanissement et de soulagement des contraintes en polyimide est disposée sur la surface avant avant formation des rainures. Un adhésif à faible viscosité et faible contrainte est déposé sur la surface rainurée revêtue de polyimide. La plaquette est ensuite collée à la surface marquée d'un substrat en verre optiquement plat sous pression et à une température de durcissement. L'ensemble est ensuite monté sur une meule laquelle élimine la partie arrière de la plaquette jusqu'à mise à nu des rainures. Le meulage s'effectue par avance à une vitesse de meulage décroissante suivie de périodes de passage. Les rainures dans la plaquette en semi-conduceur tendent à inhiber la formation de fissures. L'ensemble est ensuite placé verso vers le bas sur un bloc à broche dans un bain de solvant. Le solvant dissout la couche adhésive laissant les puces séparées du bloc à broche pour un montage sur une couche mince flexible. Les puces sont couplées à des métallisations sur la couche mince flexible au moyen d'un epoxy conducteur et scellées à l'aide d'un revêtement flexible.
EP98957755A 1997-11-11 1998-11-10 Procede d'amincissement de plaquettes en semi-conducteur a circuits et plaquettes ainsi produites Withdrawn EP1038315A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US6508897P 1997-11-11 1997-11-11
US65088P 1997-11-11
PCT/US1998/023929 WO1999025019A1 (fr) 1997-11-11 1998-11-10 Procede d'amincissement de plaquettes en semi-conducteur a circuits et plaquettes ainsi produites

Publications (2)

Publication Number Publication Date
EP1038315A1 true EP1038315A1 (fr) 2000-09-27
EP1038315A4 EP1038315A4 (fr) 2001-07-11

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EP98957755A Withdrawn EP1038315A4 (fr) 1997-11-11 1998-11-10 Procede d'amincissement de plaquettes en semi-conducteur a circuits et plaquettes ainsi produites

Country Status (3)

Country Link
EP (1) EP1038315A4 (fr)
JP (1) JP2001523046A (fr)
WO (1) WO1999025019A1 (fr)

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EP1038315A4 (fr) 2001-07-11
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