WO1998047326A1 - Wiring board having vias - Google Patents
Wiring board having vias Download PDFInfo
- Publication number
- WO1998047326A1 WO1998047326A1 PCT/JP1998/001746 JP9801746W WO9847326A1 WO 1998047326 A1 WO1998047326 A1 WO 1998047326A1 JP 9801746 W JP9801746 W JP 9801746W WO 9847326 A1 WO9847326 A1 WO 9847326A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- wiring board
- vias
- sheath
- surface side
- conductor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
- H01L2223/6622—Coaxial feed-throughs in active or passive substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09836—Oblique hole, via or bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10287—Metal wires as connectors or conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0235—Laminating followed by cutting or slicing perpendicular to plane of the laminate; Embedding wires in an object and cutting or slicing the object perpendicular to direction of the wires
Definitions
- the present invention relates to a wiring board, and more specifically, a plurality of vias penetrating the wiring board from one surface side to the other surface side, wherein an interval between the vias on the one surface side of the wiring board is between the vias on the other surface side.
- the present invention relates to a wiring board having vias, which is formed radially from one surface side to the other surface side of the wiring board so as to have a smaller interval.
- a conventional wiring board wiring is performed on a plane portion of the surface. For this reason, when the number of terminals in a semiconductor element or the like to be mounted is increased, a high-density wiring board having an increased wiring density or a multilayer wiring board having a plurality of flat wiring layers is usually used.
- JP-A-56-146264 As a prior art for this purpose, there is JP-A-56-146264, in which the wiring boards shown in FIGS. 9 (a) to 9 (e) have been proposed.
- vias 102, 102,... Penetrating a resin wiring board 100 from one side 100a to the other side 100b are formed on one side of the wiring board 100, as shown in FIG. It is formed radially from the side 100a to the other side 100b.
- the gap between the vias of the one side 100a of the wiring board 100 The spacing Wa is smaller than the spacing Wc between the vias on the other side 100b.
- the wiring board 100 shown in FIGS. 9 (a) to 9 (c) it is possible to mount a flip-chip type semiconductor element (not shown) in which a large number of bumps as electrode terminals are provided on the bottom surface. Therefore, even if the vias 102, 102,... Are arranged at high density on one side 100a of the wiring board 100, the vias 102, 102b on the other side 100b on which external connection terminals and the like are provided are provided. 102, ⁇ ⁇ ⁇ can be arranged in a state of low density. Therefore, it is possible to obtain a wiring board on which a highly integrated flip-chip type semiconductor element can be mounted.
- the insulation between the plurality of vias 102 is due to the insulating property of the resin unit forming the wiring board 100, and thus the vias 102 are not provided.
- 102, ⁇ are arranged at high density on the one side 100a of the wiring board 100, the thickness of the resin that insulates the vias 102 becomes extremely thin, and the vias 102 come into contact with each other and become There is a risk of short circuit. Disclosure of the invention
- an object of the present invention is to provide a wiring board in which a via penetrating a wiring board from one surface to another surface has a smaller interval between vias on one surface side of the wiring board than the other surface side.
- An object of the present invention is to provide a wiring board that is not likely to be electrically short-circuited even when a space between vias is extremely small.
- the present inventors have studied to solve the above-described problems, and as a result, by enclosing the conductor forming the via with an organic insulator, the vias of the via provided on one surface side of the wiring board are formed.
- the present inventors have found that even when the distance between the electrodes is extremely narrow, it is possible to eliminate the possibility that the conductor will contact and electrically short-circuit when the vias come into contact with each other, and have arrived at the present invention. That is, according to the present invention, the plurality of vias penetrating the wiring board from one surface side to the other surface side may be such that the spacing between the vias on one side of the wiring board is greater than the spacing between the vias on the other side.
- the vias is adjacent to the one side of the wiring board where the distance between the vias is smaller than the distance between the vias on the other side.
- the plurality of vias penetrating the wiring board from one surface side to the other surface side may have a smaller interval between the vias on one side of the wiring board than the gap between the vias on the other side.
- the conductor formed radially from one surface side to the other surface side of the wiring board so as to form the core of the via is covered with a first sheath portion made of an insulator, and
- the wiring board is characterized in that the first sheath is covered with a second sheath which is a conductor layer.
- the window is provided on one surface side of the wiring board where the space between the vias is smaller than the space between the vias on the other side.
- the vias are formed at high density on one surface side of the wiring board by forming the vias such that the second sheaths forming the vias come into contact with the second sheaths of the adjacent vias. it can.
- a coaxial cable-shaped shield surrounding the conductor of the core portion is formed. Vias can be formed and the wiring board can be used for high frequencies.
- the via is formed by covering the outer peripheral surface of the metal wire with an insulator, and by forming the outer peripheral surface of the insulator with a wire covered with a conductor layer. Vias with a two-layer structure can be easily formed.
- the conductor forming the core of the via is covered with the sheath made of an insulator, even if the sheath of the via comes into contact with the sheath of an adjacent via, There is no electrical short-circuit due to contact between the cores.
- the vias penetrating the wiring board from one surface side to the other surface side are so arranged that the spacing between the vias on one side of the wiring board is smaller than the spacing between the vias on the other side.
- the spacing between the vias on the one side of the wiring board is extremely small, and the via sheath is adjacent to the via. Even if it comes into contact with the sheath of the via, it is possible to eliminate the risk of electrical short-circuit due to contact between the cores.
- FIGURES 1 (a) to 1 (c) are cross-sectional views of a wiring board having vias according to the present invention.
- FIG. 3 is an explanatory diagram illustrating a state in which a via is in contact with one surface side of the wiring board shown in FIGS. 2 (a) to 2 (c).
- FIG. 5 is an explanatory diagram illustrating a state in which a via is in contact with one surface side of the wiring board shown in FIGS. 4 (a) to 4 (c).
- 6 to 8 are explanatory diagrams for explaining one process of manufacturing a wiring board according to the present invention in the order of processes.
- FIGS. 9 (a) to 9 (c) are explanatory views for explaining a conventional wiring board.
- FIGS. 2 (a) to 2 (c) are explanatory views showing a part thereof.
- the wiring board according to the present invention comprises a via 12, which penetrates a resin wiring board 10 (upper side shown) from one side 10a to the other side (lower side shown) 10b. 12, 'are formed radially from the one surface side 10a of the wiring board 10 to the other surface side 10b.
- FIG. 1 (a) showing the state of the one side 10 a of the wiring board 10
- FIG. 1 (a) showing the state of the one side 10 a of the wiring board 10 and FIG.
- the spacing Wa between the vias a is smaller than the spacing Wc between the vias on the other side 10b.
- the interval Wa is substantially zero.
- the via 12 has a core-in-sheath structure (two-layer structure) in which a core 14 made of a conductor such as copper or aluminum is covered with a sheath 16 made of an insulator. Since the interval Wa is zero, the via 12 is substantially in contact with the adjacent via 12 on the one surface side 10 a of the wiring board 10 via the sheath 16.
- the spacing Wa between the vias on the one side 10a is extremely narrow, as shown in FIG. Even if the sheaths 16 of the vias 12 and 12 are in contact with each other or a pressing force is applied to each other, the core 14 made of a conductive material is insulated by the sheaths 16 It is possible to prevent the portions 14 from being electrically short-circuited. For this reason, in order to be able to mount a highly integrated flip-chip type semiconductor element in which bumps are formed on the bottom surface as a large number of electrode terminals, a via 12 , 12 ⁇ ⁇ can be formed at high density.
- the distance Wc between the vias of the vias 12, 12-′ should be widened so that external connection terminals (not shown) such as solder balls can be provided. And external connection terminals can be easily attached.
- the via 12 forming such a wiring board can be formed using a metal wire made of a metal such as copper or aluminum covered with an insulator.
- the insulator include polyimide, epoxy and maleimid.
- Organic insulators such as resin, cyanate ester, polyvinyl ether, polyolefin, silicone, and polynuclear aromatic resin can be used.
- a thermosetting type or a thermoplastic type may be used, but an insulator having elasticity is preferable.
- an inorganic filler into the insulator, the via It is preferable because it can reduce the coefficient of thermal expansion, improve heat dissipation, and improve mechanical strength.
- an inorganic filler inorganic powder or short fibers such as alumina, silicon glass, aluminum nitride, and mullite can be used.
- the thickness of the insulator, that is, the sheath portion 16 is determined by the via pitch (distance between via centers) and the via diameter on the one surface side 10 a of the wiring board 10. For example, when vias 12, 12,... Having a diameter of 100 zm are formed at a via pitch of 250 ⁇ m on one surface side 10a of the wiring board 10 by contacting the sheath portions 16 of adjacent vias 12, A metal wire having a diameter of 100 ⁇ m and coated with an insulator of 75 ⁇ m can be used.
- the vias 12 shown in FIGS. 1 (a) to 2 (c) are formed in a straight line, but a non-linear portion may exist in a part of the via 12.
- the via 12 has a core portion 14 made of a conductor and a sheath portion 16 made of an insulator. Although it has a two-layered structure, the via 12 may have a three-layered structure as shown in FIGS. 4 (a) to 4 (c).
- a core 14 made of a conductor such as copper or aluminum is covered with a first sheath 16 made of an insulator, and the first sheath 16 is made of a conductor layer. It has a three-layer structure formed by being covered by a second sheath 18 made of.
- the core 14 made of a conductive material is formed by the first sheath 16 made of an insulator. Since it is insulated, it is possible to prevent an electrical short circuit between the cores. For this reason, it is highly integrated and has many electrode terminals on the bottom. Vias 12, 12... Can be arranged with high density on one side 10 a of wiring board 10 so that a flip-chip type semiconductor element having bumps formed thereon can be mounted.
- the distance Wc between vias of the vias 12, 12-′ can be widened to the extent that external connection terminals such as solder balls can be provided.
- the external connection terminal can be easily attached.
- a coaxial cable-shaped via 12 that is shielded by surrounding the conductor can be formed, and the wiring board 10 can support a high frequency.
- connection between the second sheath portion 18 of the via 12 and the ground line provided on the wiring board 10 is made on the side 10a of the one side of the wiring board 10 as shown in FIG.
- the connection between the second sheath 16 of the via 12 and the ground line can be reduced as much as possible.
- a conductor layer made of a metal such as copper can be formed on the peripheral surface of the first sheath 16 by electroless plating or the like.
- a plurality of metal wires such as copper or aluminum are covered with a sheath made of an insulator.
- a metal wire such as copper or aluminum is covered with a first sheath made of an insulator, and the first sheath is made of a second sheath made of a conductor.
- guide holes passing through the wire 20 are formed at predetermined intervals. It is preferable to use two guide plates 22a and 22b arranged in parallel. By passing each of the wires 20, 20- through each of the guide holes formed in each of the guide plates 22a, 22b, the wires 20, 20, O can be aligned in parallel via
- the linear bodies 20, 20,... which are aligned so as to be parallel at a predetermined interval, are converged as shown in FIG. Also in this focusing, it is possible to easily focus the linear bodies 20, 20- ⁇ by inserting the focusing tools 24, 24 between the guide plates 22a, 22b in parallel with the guide plates. it can.
- the wire 20 pressed by the focusing tools 24, 24 has a length between the guide plates 22a, 22b, and between the guide plates 22a, 22b shown in FIG. It is preferable that the guide holes formed in the guide plates 22a and 22b have a diameter that allows the wire 20 to move freely.
- a fluid resin precursor may be injected and solidified.
- the distance between the vias of the vias 12 provided on one surface side of the wiring board 10 can be extremely narrow, and the electrode terminals Highly integrated flip-chip type semiconductor device with many bumps on the bottom Can be installed.
- the distance between the vias of the vias 12 can be made as wide as possible, and external connection terminals such as solder balls can be easily mounted. .
- the spacing between the vias can be made even smaller on one surface side of the wiring board, and the spacing between the vias can be reduced on the other surface side of the wiring board. Since the external connection terminals can be easily mounted at a wide interval, it can sufficiently cope with a demand for a higher density of a wiring board accompanying a higher integration of a semiconductor element and the like.
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/202,432 US6271483B1 (en) | 1997-04-16 | 1998-04-16 | Wiring board having vias |
KR1019980710276A KR100281381B1 (ko) | 1997-04-16 | 1998-04-16 | 비아를 갖는 배선 기판 |
EP98914051A EP0926931B1 (en) | 1997-04-16 | 1998-04-16 | Wiring board having vias |
DE69839006T DE69839006T2 (de) | 1997-04-16 | 1998-04-16 | Leiterplatte mit durchkontaktierungen |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9/98681 | 1997-04-16 | ||
JP09868197A JP3629348B2 (ja) | 1997-04-16 | 1997-04-16 | 配線基板 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998047326A1 true WO1998047326A1 (en) | 1998-10-22 |
Family
ID=14226262
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1998/001746 WO1998047326A1 (en) | 1997-04-16 | 1998-04-16 | Wiring board having vias |
Country Status (6)
Country | Link |
---|---|
US (1) | US6271483B1 (ja) |
EP (1) | EP0926931B1 (ja) |
JP (1) | JP3629348B2 (ja) |
KR (1) | KR100281381B1 (ja) |
DE (1) | DE69839006T2 (ja) |
WO (1) | WO1998047326A1 (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW434821B (en) * | 2000-02-03 | 2001-05-16 | United Microelectronics Corp | Allocation structure of via plug to connect different metal layers |
US6774315B1 (en) * | 2000-05-24 | 2004-08-10 | International Business Machines Corporation | Floating interposer |
US6815621B2 (en) * | 2000-10-02 | 2004-11-09 | Samsung Electronics Co., Ltd. | Chip scale package, printed circuit board, and method of designing a printed circuit board |
KR20030065698A (ko) * | 2002-01-30 | 2003-08-09 | 삼성전자주식회사 | 볼의 피치가 작은 반도체 패키지의 테스트를 용이하게 할수 있는 반도체 패키지 테스트 보드 |
US7230247B2 (en) | 2002-03-08 | 2007-06-12 | Hamamatsu Photonics K.K. | Detector |
JP4237966B2 (ja) * | 2002-03-08 | 2009-03-11 | 浜松ホトニクス株式会社 | 検出器 |
KR20050065038A (ko) * | 2003-12-24 | 2005-06-29 | 삼성전기주식회사 | 비수직 비아가 구비된 인쇄회로기판 및 패키지 |
US20050251777A1 (en) * | 2004-05-05 | 2005-11-10 | International Business Machines Corporation | Method and structure for implementing enhanced electronic packaging and PCB layout with diagonal vias |
KR100858075B1 (ko) | 2004-07-06 | 2008-09-11 | 도쿄엘렉트론가부시키가이샤 | 인터포저 |
US7915537B1 (en) * | 2005-10-19 | 2011-03-29 | Edward Herbert | Interposer and method for making interposers |
US7629541B2 (en) * | 2006-06-19 | 2009-12-08 | Endicott Interconnect Technologies, Inc. | High speed interposer |
JP5772970B2 (ja) | 2011-10-21 | 2015-09-02 | 株式会社村田製作所 | 多層配線基板、プローブカード及び多層配線基板の製造方法 |
US8946757B2 (en) * | 2012-02-17 | 2015-02-03 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
JP2014038884A (ja) * | 2012-08-10 | 2014-02-27 | Murata Mfg Co Ltd | 電子部品および電子部品の製造方法 |
US9496212B2 (en) * | 2014-12-19 | 2016-11-15 | Freescale Semiconductor, Inc. | Substrate core via structure |
US20200072871A1 (en) * | 2017-03-31 | 2020-03-05 | Intel Corporation | Ultra low-cost, low leadtime, and high density space transformer for fine pitch applications |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56146264A (en) * | 1980-04-14 | 1981-11-13 | Mitsubishi Electric Corp | Carrier for equipment of chip |
JPS63193587A (ja) * | 1987-02-06 | 1988-08-10 | 株式会社日立製作所 | 導体シ−ルド付微細スルホ−ル基板 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5197892A (en) * | 1988-05-31 | 1993-03-30 | Canon Kabushiki Kaisha | Electric circuit device having an electric connecting member and electric circuit components |
US5055966A (en) * | 1990-12-17 | 1991-10-08 | Hughes Aircraft Company | Via capacitors within multi-layer, 3 dimensional structures/substrates |
JP3004071B2 (ja) * | 1991-04-16 | 2000-01-31 | 日本特殊陶業株式会社 | 集積回路用パッケージ |
JP3167141B2 (ja) * | 1991-04-16 | 2001-05-21 | 日本特殊陶業株式会社 | 集積回路用パッケージ |
US5315072A (en) * | 1992-01-27 | 1994-05-24 | Hitachi Seiko, Ltd. | Printed wiring board having blind holes |
US5340947A (en) * | 1992-06-22 | 1994-08-23 | Cirqon Technologies Corporation | Ceramic substrates with highly conductive metal vias |
JP2570617B2 (ja) * | 1994-05-13 | 1997-01-08 | 日本電気株式会社 | 多層配線セラミック基板のビア構造及びその製造方法 |
JP3252635B2 (ja) * | 1995-01-13 | 2002-02-04 | 株式会社村田製作所 | 積層電子部品 |
JPH08330469A (ja) * | 1995-05-30 | 1996-12-13 | Hitachi Ltd | 半導体装置用配線基板およびその製造方法 |
US5699613A (en) * | 1995-09-25 | 1997-12-23 | International Business Machines Corporation | Fine dimension stacked vias for a multiple layer circuit board structure |
US5920123A (en) * | 1997-01-24 | 1999-07-06 | Micron Technology, Inc. | Multichip module assembly having via contacts and method of making the same |
US5949030A (en) * | 1997-11-14 | 1999-09-07 | International Business Machines Corporation | Vias and method for making the same in organic board and chip carriers |
-
1997
- 1997-04-16 JP JP09868197A patent/JP3629348B2/ja not_active Expired - Fee Related
-
1998
- 1998-04-16 KR KR1019980710276A patent/KR100281381B1/ko not_active IP Right Cessation
- 1998-04-16 WO PCT/JP1998/001746 patent/WO1998047326A1/ja active IP Right Grant
- 1998-04-16 DE DE69839006T patent/DE69839006T2/de not_active Expired - Lifetime
- 1998-04-16 US US09/202,432 patent/US6271483B1/en not_active Expired - Fee Related
- 1998-04-16 EP EP98914051A patent/EP0926931B1/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56146264A (en) * | 1980-04-14 | 1981-11-13 | Mitsubishi Electric Corp | Carrier for equipment of chip |
JPS63193587A (ja) * | 1987-02-06 | 1988-08-10 | 株式会社日立製作所 | 導体シ−ルド付微細スルホ−ル基板 |
Non-Patent Citations (1)
Title |
---|
See also references of EP0926931A4 * |
Also Published As
Publication number | Publication date |
---|---|
JPH10290059A (ja) | 1998-10-27 |
EP0926931A1 (en) | 1999-06-30 |
EP0926931B1 (en) | 2008-01-16 |
EP0926931A4 (en) | 2006-12-06 |
DE69839006D1 (de) | 2008-03-06 |
US6271483B1 (en) | 2001-08-07 |
KR100281381B1 (ko) | 2001-02-01 |
DE69839006T2 (de) | 2009-01-08 |
KR20000016676A (ko) | 2000-03-25 |
JP3629348B2 (ja) | 2005-03-16 |
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