WO1998039864A1 - Recepteur numerique de signaux - Google Patents

Recepteur numerique de signaux Download PDF

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Publication number
WO1998039864A1
WO1998039864A1 PCT/JP1998/000929 JP9800929W WO9839864A1 WO 1998039864 A1 WO1998039864 A1 WO 1998039864A1 JP 9800929 W JP9800929 W JP 9800929W WO 9839864 A1 WO9839864 A1 WO 9839864A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
signal
receiving
multiplex
multiplexed
Prior art date
Application number
PCT/JP1998/000929
Other languages
English (en)
Japanese (ja)
Inventor
Hironori Mitoh
Masahiro Sata
Hiroyuki Tachibana
Morihiko Sumino
Takeharu Matsui
Original Assignee
Sanyo Electric Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co., Ltd. filed Critical Sanyo Electric Co., Ltd.
Priority to JP53838198A priority Critical patent/JP3604703B2/ja
Priority to EP98905792A priority patent/EP0977386A4/fr
Publication of WO1998039864A1 publication Critical patent/WO1998039864A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H40/00—Arrangements specially adapted for receiving broadcast information
    • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
    • H04H20/16—Arrangements for broadcast or for distribution of identical information repeatedly
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
    • H04H20/28—Arrangements for simultaneous broadcast of plural pieces of information

Definitions

  • the present invention relates to a digital signal receiving apparatus capable of receiving programs from a plurality of networks by multiplex broadcasting, and more particularly to an FM multiplex signal receiving apparatus in which the program data is transmitted by FM multiplex broadcasting.
  • FM multiplex broadcasting is a new media that multiplexes a new digital signal into a higher frequency band than the audio signal of the current FM stereo broadcast and broadcasts traffic information, text and graphic information, and so on. Its features include the ability to use frequencies effectively, the simplicity of broadcasting equipment, and the ability to easily receive traffic information and other information from vehicles, such as automobiles.
  • FM multiplex broadcasting can be used as a means of transmitting real-time traffic congestion information and the like to an automatic vehicle equipped with a receiver, or the information necessary for a user having a handy type receiver can be provided at any time. Some of them have been put into practical use as a means of providing inexpensive transmission lines that can be accessed anywhere.
  • the transmission path characteristics are generally very poor. Even in such a case, a system that can completely receive data at the same time as possible is desirable. However, in practice, the data transmitted in one reception is completely completed. In some cases, it may not be possible to receive all the data. In such a case, it is assumed that the retransmitted data is received and the data that could not be received is supplemented. It is desirable that the FM multi-broadcast service area be the same as the FM stereo broadcast service area, but there are places in this service area where the average bit error rate exceeds 10 -2. Therefore, the structure of the data to be transmitted has its error correction method and frame configuration determined in consideration of such poor transmission path characteristics.
  • the data has a two-dimensional frame structure including error correction codes in both the vertical and horizontal directions.
  • the transmission data has a data structure having a hierarchical structure with the data in one frame as a basic unit.
  • Figure 12 shows the specifications of the hierarchical structure of the above data.
  • L + R and L-R signals which are ordinary FM stereo broadcast signals
  • multiple signals are superimposed on the higher frequency side than the L-R signal.
  • This superposition method considers that the interference from the multiplexed signal to the audio signal is remarkable when the audio modulation is small, and controls the level of the multiplexed signal by the modulation of the L-R signal. led Minimum Shift Keying) method is adopted.
  • Layer 2 specifies the data frame structure including the error correction method.
  • Each frame consists of 272 blocks in the column direction, and is preceded by a 16-bit BIC (Block Identification Code) is added, and frame synchronization and block synchronization are performed based on this BIC.
  • BIC Block Identification Code
  • 190 blocks are packets for transmitting data
  • 82 blocks are parity buckets for transmitting parity in the column direction.
  • Each bucket is composed of a 176-bit information section in the row direction, a 14-bit cyclic redundancy code (CRC) as an error detection code, and an 8-bit parity section as an error correction code.
  • CRC cyclic redundancy code
  • transmission data is subjected to error correction first at this stage using this one frame as a basic unit.
  • Layer 3 defines the structure of the data packet.
  • the data packet consists of 176 bits excluding BIC, CRC, and parity in each row in the frame.
  • this data packet consists of a prefix and a data block.
  • the prefix includes information for identifying the content of the data, and specifies, for example, which program content described later the data bucket belongs to.
  • Tier 4 specifies the structure of the data group.
  • a data group consists of one or more data blocks. In other words, based on the information in the prefix in the data packet, the data packet number is arranged in the order of the data packet number from "0" to the data block with the information end flag in the prefix. You.
  • This data group also includes a CRC which is an error detection code, and the transmission data is subjected to error detection also in this layer.
  • One data group corresponds to one display unit, that is, one page of data.
  • Layer 5 defines the structure of a group of information data transmitted by FM multiplex broadcasting, that is, program data.
  • FIG. 13 shows the structure of this program data.
  • a program with text and graphic information is composed of multiple data groups, and the first data group consists of coded information related to the entire program, such as the program number and the total number of pages, as program management data. Following the program management data, there are a plurality of page data, and the data for each page is encoded.
  • Program data and page data consist of a data header section and a data unit group.
  • the data unit group consists of the character data section ⁇ photographic figure data And a plurality of data units divided for each encoding, such as a unit. That is, in the above data structure, the program data forms a group of data indicating a group of information on the receiving side. For example, in the case of traffic information, the program information indicates the congestion status at each junction of a specific route (such as an expressway), and in the case of a weather forecast, it indicates the weather forecast information in a specific area.
  • FIG. 14 is a schematic block diagram showing a configuration of a conventional FM multiplex broadcast receiver 10.
  • the FM multiplex broadcast signal received by the antenna 12 and the tuner 14 is detected by the detection circuit 16, and further supplied to the LMSK demodulation circuit 20 via the band pass filter 18.
  • the LMSK demodulation circuit 20 demodulates the data of the FM multiplex broadcast signal which is LMSK modulated, and extracts the FM multiplex signal.
  • the demodulated data signal is subjected to frame synchronization and block synchronization in the synchronous reproduction circuit 22 based on BIC as described in the hierarchy 2 in FIG.
  • the synchronized data signal is error-corrected in the error correction circuit 24 based on the parity code and the CRC.
  • the packet data (having the configuration shown in layer 3 in FIG. 12) of the FM multiplex broadcast which has been normally received or subjected to error correction is output.
  • the central processing unit 40 (hereinafter referred to as a CPU) extracts data blocks, reconstructs data groups, corrects errors at the data drop stage, and converts program data into input packet data. After the reconstruction, the program data is output to the display device 42.
  • the display device 42 outputs the input program data as graphics or characters.
  • the display device 42 a liquid crystal screen or the like having a display area for one page, that is, 248 ⁇ 60 dots (corresponding to 15.5 sentence X2.5 lines in Japanese display) is used.
  • the CPU 40 when receiving a program from a different network, that is, a program from a different program provider, for example, the CPU 40 controls channel selection by a tuner. Can be configured is there.
  • the tuning information data for specifying the network selected by the CPU 40 is supplied to the tuner 14 and the LMSK demodulation circuit 20, and the tuner 14 selects the selected network, and the LMSK demodulation circuit 20 is selected.
  • the tuner 14 selects the selected network, and the LMSK demodulation circuit 20 is selected.
  • the configuration of the FM multiplex broadcast receiving apparatus includes not only the integrated configuration as shown in Fig. 14, but also FM demodulation, LMSK demodulation, and packet data extraction (including synchronous reproduction and packet data error correction).
  • the circuit that performs this is converted into a so-called PC card (PCMC IA card: Personal Computer Memory Card International As sociation card), and a host personal computer (hereinafter referred to as host PC) via a predetermined interface. ) Is also possible.
  • FIG. 15 is a schematic block diagram showing a configuration of the FM multiplex broadcast receiving apparatus 80 having a configuration in which the PC card and the host PC are connected via an interface as described above.
  • the tuner 14 and the detection circuit 16 in FIG. 14 are represented by an FM demodulation circuit 17 of one block, and the LMSK demodulation circuit 20 and the error correction circuit 24 are represented by one block. It is represented by an LMSK demodulation integrated circuit 25. Therefore, the FM multiplex broadcast signal received by the antenna 12 and demodulated by the FM demodulation circuit 17 is further provided to the LMSK demodulation integrated circuit 25 via the band pass filter 18.
  • the LMSK demodulation integrated circuit 25 demodulates the data of the FM multiplex broadcast signal that has been subjected to the LMSK modulation. Against M multiplexed signal, after frame synchronization and block synchronization based on the BIC as described in the hierarchy 2 in FIG. 1 2, Bruno. Error correction based on the parity code and CRC.
  • the LMSK demodulation integrated circuit 25 outputs FM multiplex broadcast packet data (having the configuration shown in layer 3 in FIG. 12) that has been normally received or error-corrected.
  • An interface unit (hereinafter, referred to as an IZF unit) 30 receives the bucket data from the LMSK demodulation / integration circuit 25 and outputs it to the interface unit 38 on the host PC side.
  • the central processing unit (hereinafter referred to as CPU) of the host PC extracts data blocks from input packet data, reconstructs data groups, detects errors at the data group stage, and converts program data to data. After reconstructing the program, the program data is output to a display device (not shown).
  • the memory for transmitting and receiving data to and from the CPU and the CPU are represented by one block 45.
  • the display device of the host PC for example, a liquid crystal flat panel display, is used as the display device, and the display area has a resolution of, for example, 640 X 400 dots or more. Can be done.
  • the FM multiplex broadcast receiver 80 having a configuration in which a PC card and a host PC are connected via an interface has the following problems.
  • the circuit incorporated in the PC card must be as simple as possible in construction.
  • the connection with the host PC must have a configuration in which the received data is immediately transferred to the host PC without having a reception buffer or the like. Data transfer from the PC card to the host PC must be performed asynchronously.
  • the host PC instructs the PC card to switch networks.
  • the bucket data corresponding to the switched network immediately after that is not output from the PC card. Therefore, if the system is simply configured with an asynchronous interface, there is an inconvenience that the program before the switching is output from the display device for a certain period of time even after the network is switched.
  • the information provided by FM multiplex broadcasting is intended for different services for each network (broadcasting station), and if such services are to be completely received, the following problems will also occur.
  • the different services it may transmit news information as character information, so-called radio and visible, traffic information (hereinafter, referred to as VI CS information VI CS:. Ve hi C le I nf oma tion Commun ication Syst em);
  • a method of mounting a plurality of receiving systems such as a double tuner configuration shown in FIG. 16, is conceivable.
  • simply using multiple reception systems requires multiple systems for data transfer to the host PC.
  • the data receiving software on the host PC becomes complicated, and the load on the hardware becomes large.
  • Another object of the present invention is to simplify the configuration of a receiving unit and a data reconstructing unit when receiving and reconstructing bucket data received by switching a plurality of networks asynchronously in a multiplex broadcast, and simplifying the manufacturing cost.
  • An object of the present invention is to provide a digital signal receiving device capable of reducing the number of digital signals.
  • Still another object of the present invention is to efficiently acquire data from a plurality of networks in a multiplex broadcast when switching and switching between a plurality of networks and receiving and reconstructing bucket data asynchronously. It is an object of the present invention to provide a digital signal receiving device capable of performing the following.
  • each of a plurality of program data is divided into a plurality of packets, and each bucket includes attribute data indicating to which of a plurality of networks the corresponding program data belongs.
  • a digital signal receiving device in a communication system that is multiplexed with main signal data as a bucket stream and transmitted, and receives the bucket stream and extracts a corresponding digital signal according to an external control signal. And a multiplexed signal separating means for outputting.
  • the multiplex signal separating means receives a carrier wave for transmitting the multiplex signal corresponding to the selected network according to the control signal, demodulates the carrier wave, receives an output of the demodulation means, extracts the multiplex signal, Multiplex signal decoding means for outputting as a plurality of packet data composed of corresponding digital signals, and receiving the output from the multiple signal decoding means, adding identification data for each packet data according to attribute data, and outputting.
  • Interface control means receives a carrier wave for transmitting the multiplex signal corresponding to the selected network according to the control signal, demodulates the carrier wave, receives an output of the demodulation means, extracts the multiplex signal, Multiplex signal decoding means for outputting as a plurality of packet data composed of corresponding digital signals, and receiving the output from the multiple signal decoding means, adding identification data for each packet data according to attribute data, and outputting.
  • Interface control means receives a carrier wave for transmitting the multiplex signal corresponding to the selected network according to the control signal, demodulates the carrier wave, receive
  • each of a plurality of program data is divided into a plurality of buckets, and each packet is a program data corresponding to a plurality of networks.
  • a digital signal receiving device in a communication system which is multiplexed with main signal data and transmitted as a bucket stream including attribute data indicating which of the A multiplexed signal separating means for extracting and outputting a corresponding digital signal in response.
  • the multiplex signal demultiplexing means receives, according to the control signal, a first demodulation means for receiving and demodulating a carrier transmitting a multiplex signal corresponding to the selected network, and receiving an output of the first demodulation means, A first multiplex signal decoding means for extracting a multiplex signal and outputting it as a plurality of first bucket data composed of corresponding digital signals; and transmitting a multiplex signal corresponding to a selected network according to a control signal.
  • a second demodulation means for receiving and demodulating a carrier wave, receiving an output of the second demodulation means, extracting a multiplexed signal, and outputting as a plurality of second bucket data comprising corresponding digital signals.
  • each of the plurality of program data is divided into a plurality of buckets, and each bucket stores attribute data indicating to which of the plurality of networks the corresponding program data belongs.
  • a digital signal receiving apparatus in a communication system which is multiplexed with main signal data and transmitted as a bucket stream including a multiplex signal separating means, an information reconstructing means, and a display means.
  • the multiplex signal separating means receives the packet stream, extracts a corresponding digital signal in response to an external control signal, and outputs the digital signal.
  • the multiplex signal separating means receives a carrier wave for transmitting the multiplex signal corresponding to the selected network according to the control signal, demodulates the carrier wave, receives an output of the demodulation means, extracts the multiplex signal, It includes multiplex signal decoding means for outputting as a plurality of packet data composed of corresponding digital signals, and interface control means for receiving an output from the multiplex decoding means, buffering and outputting the result.
  • the information reconstructing means provides a control signal to the multiplex signal separating means, receives an output of the interface controlling means, reconstructs and outputs display data corresponding to the program data.
  • the information reconstructing means includes a timing detecting means for determining a timing to start acquiring bucket data for reconstructing display data after outputting a control signal for switching the network.
  • the display means outputs display data.
  • each of the plurality of program data is harmed to a plurality of buckets, and attribute data indicating which of the plurality of networks the corresponding program data belongs to is stored as attribute data.
  • the packet is multiplexed with the main signal data and transmitted as a packet stream included in the bucket, and at least one of the networks is configured such that the content of the information broadcast at the first predetermined time is updated every second predetermined time interval.
  • a digital signal receiving apparatus in a communication system for supplying cyclic program data comprising: a multiplexed signal separating unit; an information reconstructing unit; and a display unit.
  • the multiplex signal separating means receives the packet stream, extracts a corresponding digital signal in response to an external control signal, and outputs the digital signal.
  • the multiplex signal separating means receives a carrier wave for transmitting the multiplex signal corresponding to the selected network according to the control signal, demodulates the carrier wave, receives an output of the demodulation means, extracts the multiplex signal, A multiplex signal decoding means for outputting as a plurality of packet data comprising corresponding digital signals; and an interface for receiving the output from the multiplex decoding means and adding identification data for each bucket data according to the attribute data and outputting the same. Control means.
  • the information reconstructing means provides a control signal to the multiplex signal separating means, receives an output of the interface controlling means, reconstructs and outputs display data corresponding to the program data according to the identification data.
  • the information reconstructing means includes a first process for reconstructing the traveling program data for at least a first predetermined time, and a second process for reconstructing program data of another network by selecting another network. And a network selection control means for controlling the processing to be repeated at a second predetermined time interval.
  • the display means outputs display data.
  • each of the plurality of program data is divided into a plurality of buckets, and the corresponding program data belongs to any of the plurality of networks.
  • Attribute data indicating whether or not the packet is transmitted is multiplexed on the main signal data as a bucket stream included in each bucket, and at least one of the networks includes information content broadcast within a first predetermined time.
  • a digital signal receiving apparatus in a communication system that supplies cyclic program data updated every second predetermined time interval, comprising: a multiplexed signal separating unit; an information reconstructing unit; and a display unit.
  • the multiplex signal separating means receives the packet stream, extracts a corresponding digital signal in response to an external control signal, and outputs the digital signal.
  • the multiplex signal separating means receives a carrier wave for transmitting the multiplex signal corresponding to the selected network according to the control signal, demodulates the carrier wave, receives an output of the demodulation means, extracts the multiplex signal, It includes multiplex signal decoding means for outputting as a plurality of packet data composed of corresponding digital signals, and interface control means for receiving an output from the multiplex decoding means, buffering and outputting the result.
  • the information reconstructing means provides a control signal to the multiplex signal separating means, receives an output of the interface controlling means, reconstructs and outputs display data corresponding to the program data.
  • the information reconstructing means includes a first process for reconstructing the traveling program data for at least a first predetermined time, and a second process for reconstructing the program data of another network by selecting another network.
  • a network selection control means for controlling the processing of step 2 to be repeated at a second time interval, and a timing for starting acquisition of bucket data for reconstructing display data after outputting a control signal for switching networks. And timing detecting means.
  • the display means outputs display data.
  • a main advantage of the present invention is that, in multiplex broadcasting, when packet data received by switching a plurality of networks is asynchronously received and reconfigured, information from the network before the switching is prevented from being output. It becomes possible.
  • Another advantage of the present invention is that, in multiplex broadcasting, when a plurality of networks are switched and received bucket data is asynchronously received and reconfigured, the configuration of a receiving unit and a data reconfiguring unit is simplified and manufacturing costs are reduced. It is possible to achieve. Still another advantage of the present invention is that in multiplex broadcasting, multiple networks are disconnected. In other words, it is possible to efficiently obtain data from a plurality of networks when asynchronously receiving and reconstructing received bucket data and the like.
  • FIG. 1 is a schematic block diagram illustrating a configuration of the FM multiplex broadcast receiving apparatus 100 according to the first embodiment.
  • FIG. 2 is a schematic block diagram illustrating an example of an appearance of the FM multiplex broadcast receiving apparatus 100 according to the first embodiment.
  • FIG. 3 is a schematic diagram showing a configuration of a data group in an FM multiplex broadcast signal.
  • FIG. 4 is a flowchart showing the operation of the CPU 40 of the first embodiment.
  • FIG. 5 is a schematic diagram illustrating a configuration of ID data according to the second embodiment.
  • FIG. 6 is a timing chart showing the transmission cycle of VICS information.
  • FIG. 7 is a flowchart illustrating the operation of the CPU 40 according to the third embodiment.
  • FIG. 8 is a schematic block diagram illustrating a configuration of the FM multiplex broadcast receiving apparatus 200 according to the fourth embodiment.
  • FIG. 9 is a partial block diagram showing the configuration of the FM multiplex broadcast receiving apparatus 200 shown in FIG. 8 in detail.
  • FIG. 10 is a schematic diagram showing a format of data output from the LMSK demodulation circuit.
  • FIG. 11 is a flowchart showing the operation of the CPU 52 of the fourth embodiment.
  • FIG. 12 is a specification diagram showing the specifications of FM multiplex broadcasting.
  • FIG. 13 is a schematic diagram showing the configuration of program data.
  • FIG. 14 is a schematic block diagram showing the configuration of the first conventional FM multiplex broadcast receiving apparatus 10. As shown in FIG.
  • FIG. 15 is a schematic block diagram showing a configuration of a second conventional FM multiplex broadcast receiving apparatus 80.
  • FIG. 16 is a schematic block diagram showing a modification of the FM multiplex broadcast receiver 10 of FIG. is there. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a schematic block diagram illustrating a configuration of an FM multiplex broadcast receiving apparatus 100 according to a first embodiment of the present invention.
  • the FM multiplex broadcast receiver 100 receives antennas 12 for receiving FM radio waves, an FM tuner section 14 for receiving the output of the antenna 12 for FM demodulation, and receiving an output of the FM tuner section 14 for extracting and error-correcting the FM multiplex signal.
  • a personal computer 120 that receives the digital signal, forms display unit data (page data), and displays corresponding characters and the like.
  • the difference from the configuration of the conventional FM multiplex broadcast receiving apparatus 10 shown in FIG. 14 is that the FM multiplex decoding section 15 extracts an FM multiplex signal from the signal demodulated by the FM tuner section 14 and outputs the bucket.
  • the personal computer 120 receives a digital signal output as packet data, reconstructs the bucket data into program data, and displays the program data.
  • the FM multiplex broadcast signal received by the antenna 12 is output from the phase locked loop circuit 4 (hereinafter, referred to as a PLL circuit) in the FM demodulation circuit 2 in the FM tuner 14.
  • the signal is synchronously detected by the wave and output to the FM multiplex decoding unit 15 via the buffer 6.
  • the FM multiplex decoding unit 15 receives the FM demodulated signal via the buffer circuit 8, extracts a signal component in a predetermined frequency region by the band pass filter 18, performs LMSK demodulation in the demodulation LSI 20, and Extract multiple signals.
  • the CPU 26 receives the output of the demodulation LSI 20 and outputs packet data on which block synchronization, error correction and the like of the received data have been performed. At this time, if there is bucket data that cannot be corrected, this data is deleted by the CPU 26, and only the data necessary for display is selected and output.
  • RAM 28 receives the output from CPU 26 and Operates as a buffer for outputting data.
  • the address decoder 32 When detecting that the personal computer 120 has been accessed, the address decoder 32 causes the interface 30 to output data. Normally, controller 34 receives output data from interface 30 and outputs data to personal computer 120. However, at the time of starting up the apparatus, initial settings between interfaces are performed based on data stored in the ROM 36.
  • the personal computer 120 serving as the host PC receives the packet data output from the FM multiplex decoding section 15 via the interface 38.
  • the CPU 40 receives the output data from the interface 38, that is, the packet data, extracts the data blocks from the data packets according to the hierarchical structure shown in FIG. 10, reconstructs the data groups from the data blocks, and forms the data groups. Then, error detection is performed. Further, the CPU 40 extracts a data header and a data unit group corresponding to the page data from the data group data in the data group, and reconstructs the program data.
  • the CPU 40 performs FM decoding via the interface 38 and the interface 30 in accordance with the data supplied from the input section 46 or the data stored in the memory 44 as described later.
  • a tuning instruction is given to the CPU 26 in the unit 15.
  • the CPU 26 controls the FM tuner part 14 based on the channel selection instruction to select the specified network.
  • the CPU 40 Based on the program data reconstructed as described above, the CPU 40 outputs the corresponding display data to the display unit 42, and the display unit 42 converts the corresponding character information or graphic information based on the received display data. Output.
  • the display unit 42 is, for example, a liquid crystal flat panel display or the like in a hand-held type personal computer, and its display area has a resolution of 640 ⁇ 400 dots or more.
  • FIG. 2 is a schematic diagram showing a case where the FM multiplex broadcast receiving apparatus 100 shown in FIG. 1 is configured using a notebook computer 120 and a PC card.
  • the FM multiplex decoding unit 15 is converted to a PC card, Data 120.
  • the FM tuner section 14 is configured to be connected to the FM multiplex decoding section 15 by a connection cord. With the above configuration, it is possible to keep the FM tuner section 14 away from the personal computer 120 and to prevent noise from the personal computer 120 from being mixed into the received signal. .
  • the FM tuner section 14 and the FM multiplex decoding section 15 are not connected by a connection cord, but they can be integrated into a more convenient form. It is possible.
  • FIG. 3 is an example of a schematic diagram showing the configuration of the data group shown in FIG.
  • the data group includes a heading start code (SOH) at the beginning of the data group, which indicates the start of the data group, followed by a data group link code, which is a flag indicating whether the data group is connected, and the number of bytes of the data group data. Includes data group size data indicating Subsequently, there is data group data, which is the body of the data to be transmitted. Following this, a NULL area for length adjustment to adjust the data group length to an integer multiple of the data block length, an end code indicating the end of the data group, and error detection of the data group CRC code exists.
  • SOH heading start code
  • the data group data includes data indicating whether the data is dynamic data or static data in the VICS data.
  • FIG. 4 is a flowchart showing an example of the operation of the CPU 40.
  • step S104 the CPU 40 determines whether or not a channel selection operation, that is, switching of the receiving network has been instructed, by an external instruction given to the input unit 46 (step S104). If the switching is instructed, the CPU 40 resets the value of a variable n for counting the number of bucket data provided from the FM multiplex decoding unit 15 to 0 (step S106). Subsequently, the CPU 40 determines whether an interrupt for data transfer has been performed from the FM multiplex decoding unit (step S108). On the other hand, if the switching of the network has not been instructed, the CPU 40 advances the processing to step S108 (step S104).
  • step S108 If it is determined in step S108 that there is no data transfer interrupt (step S108), the process returns to step S104.
  • step S108 If it is determined that there is a data transfer interrupt (step S108), then the magnitude relationship between the variable n and the predetermined number N is compared (step S110). If n> N, that is, if reading of a predetermined number N or more of packet data has already been completed (step S 110), the CPU 40 sends data to be taken in thereafter from the switched network. It is determined that the data is bucket data, the data is read, and the process returns to step S104 (step S112).
  • step S110 if n> N is not satisfied, that is, if reading of a predetermined number N of packet data has not been completed (step S110), the CPU 40 discards the received data (step S1). 14) Then, the value of the variable n is incremented by 1, and the process returns to step S104 (step S116).
  • the CPU 40 prevents the data from the network before the power switching from being reconstructed and output to the display device 42. .
  • the CPU 40 is configured to discard a predetermined number N of packet data after instructing to switch the network.However, after instructing the CPU 40 to switch the network, data is fetched until a certain time elapses. It is also possible to adopt a configuration without such.
  • step S104 the CPU 40 Based on the instruction from the section, it is determined whether the channel selection operation, that is, the switching of the receiving network is instructed (step S104).
  • step S106 the CPU 40 resets the value of the timer 41 (step S106). Subsequently, the CPU 40 determines whether an interrupt for data transfer has been performed from the FM multiplex decoding unit (step S108). On the other hand, if the switching of the network has not been instructed, the CPU 40 advances the processing to step S108 (step S104).
  • step S108 If it is determined in step S108 that there is no data transfer interrupt (step S108), the process returns to step S104.
  • step S108 If it is determined that there is a data transfer interrupt (step S108), then a comparison is made between the time measured by the timer and the predetermined time t (step S110). If the time t has elapsed (step S110), the CPU 40 determines that the data to be captured thereafter is bucket data from the switched network, and reads the data. The process is returned to step S104 (step S112).
  • step S110 if the time t has not elapsed (step S110), the CPU 40 returns the processing to step S104 (step S116).
  • the CPU 40 receives a predetermined number of buckets without specially determining whether the data is data from the network before the switching and data from the network after the switching.
  • program data is not reconstructed from packet data until program data is captured or a predetermined time has elapsed. Therefore, even if data is actually received from the switched network, that data is unconditionally discarded. Conversely, a stable operation cannot be realized unless a predetermined number N and a predetermined time t are set in advance in anticipation of such useless data.
  • the above-mentioned waste of data can be eliminated.
  • the configuration of the digital signal receiving apparatus of the second embodiment is basically the same as the configuration of the digital signal receiving apparatus 100 of the first embodiment, but as described below, the digital signal receiving apparatus shown in FIG.
  • the operation of the CPU 26 of the FM multiplex decoding unit 15 in the configuration of the signal receiving device 100 is different.
  • the CPU 26 adds, at the time of reception, identification data to the data (all P-layers 3 or 4) data received from the demodulation LSI 20 and transferred to the host PC, which can identify the data of which station.
  • the CPU 26 mixes the data of each station to which the identification data is added in a data unit (layer 3 or layer 4 data) in an arbitrary order and transfers the data to the host PC.
  • FIG. 5 is a conceptual diagram showing the configuration of the data format when such identification data (hereinafter referred to as ID) is added.
  • the frequency value of the network received as ID As a first example, it is possible to add the frequency value of the network received as ID. Also, as a second example, a parameter corresponding to the reception frequency on a one-to-one basis is used.For example, when the reception frequency is 80.2 MHz, the numerical value 1 is used. It is possible.
  • a configuration is possible in which a flag is set only for the first data from a newly selected network, that is, the value of ID is set to "1".
  • the data after the flagged data (these flags are "0") will be the data after tuning.
  • the CPU 40 can determine, from the network switching instruction, the point at which the data from the switched network starts after the network switching instruction. .
  • data transmission to the host PC does not require a plurality of reception systems even when data from a plurality of networks is switched and received.
  • the configuration has been described in which, when the receiving network is switched, a break is provided between data from the switched network and previous data.
  • detection of such data breaks is important even when receiving different services, for example, news information and VICS information, without fail.
  • information acquisition from multiple networks may be more important than information output in real time.
  • the host PC cannot detect the break in the information when the network is switched.
  • scanning can be performed efficiently according to characteristics such as VICS information.
  • the configuration of the digital signal receiving apparatus of the third embodiment is basically the same as the configuration of the digital signal receiving apparatus 100 of the first embodiment in that the data is separated. As described below, the operation of the CPU 40 in the configuration of the host PC shown in FIG. 1 is different.
  • the configuration of the digital signal receiving apparatus according to the third embodiment is basically the same as the configuration of the digital signal receiving apparatus 100 according to the second embodiment in that the data break is detected. It is also possible to adopt a configuration in which the operation of the CPU 40 in the above configuration is different.
  • FIG. 6 is a timing chart showing the transmission timing of the VICS information.
  • the VICS information is updated every 5 minutes, but the dynamic information (information that changes every moment) such as traffic congestion information (information on which roads are congested and how much) is the first minute. Complete the transmission within In the remaining time, static information (information that does not change with time) such as map information is retransmitted.
  • the reason why the static information is constantly retransmitted as described above is so that the traffic information as a whole can be reproduced on the display device whenever the receiving side starts receiving. In other words, once the static information has been received, there is no need to receive it again unless the program itself is changed so that the static information is changed.
  • the network is automatically scanned every 5 minutes (or a multiple thereof) from that point on, and the mobile station returns to the original station as soon as dynamic information reception is completed. A configuration of returning is possible.
  • FIG. 7 is a flowchart for explaining the operation of the CPU 40 when performing such a scan operation.
  • the CPU 40 selects a station A that transmits the ICS information (step S204).
  • the CPU 40 waits until the start of receiving dynamic data of the station A based on the data in the data group data (step S204).
  • the CPU 40 resets the timer 41 (step S208) and starts the clocking operation.
  • step S210 the CPU 40 maintains the standby state (step S210), and when it confirms the reception of the dynamic data again (step S210), the timing at which the dynamic data is transmitted, that is, The period of the VI CS information is obtained (step S212). However, using the period from step S206 to step S212, acquisition of static data is performed in parallel with the above processing.
  • the A station is selected by the instruction from the CPU 40 (step S216).
  • the CPU 40 enters a standby state until it detects the start of reception of dynamic data (step S218).
  • the CPU 40 When detecting the start of the reception of the dynamic data (step S218), the CPU 40 resets the timer 41 and starts the timer operation (step S220).
  • the CPU 40 When the CPU 40 detects that the reception of the dynamic data of the station A has been completed, the CPU 40 instructs the selection of the station B (step S224).
  • the CPU 40 receives the data of the station B (step S226), and determines whether or not the counted value of the timer has reached the transmission cycle of the VICS information (step S228). If the transmission period has not been reached, the reception of the station B is continued again (step S226). If the transmission period has been reached, the process returns to step S216.
  • the transmission cycle of the VICS information is obtained by monitoring for one cycle after the operation of the CPU 40 is started.
  • the transmission cycle is fixed in advance, for example, the transmission cycle of the transmission cycle may be determined. It is also possible to adopt a configuration in which data is stored in the memory 44 in the host PC in advance.
  • the operation of the CPU 40 may be performed by the CPU 26 of the FM multiplex decoding unit in FIG.
  • At least two reception systems are required to receive all data from multiple networks.
  • FIG. 8 is a schematic block diagram showing a configuration of a digital signal receiving device 200 according to the fourth embodiment, and is a diagram to be compared with FIG. 15 showing a configuration of a conventional digital signal receiving device 80.
  • the configuration of the digital signal receiving device 200 is different from the configuration of the digital signal receiving device 80 in the following two points.
  • the digital signal receiver 200 is configured to have two FM demodulation circuits 17a and 17b, two filters 18a and 18b, and two LMSK demodulation circuits 25a and 25b. It is.
  • the corresponding IDs are added to the data as in the second embodiment.
  • the two are mixed, in other words, they are configured to output to the host PC in a time-sharing manner.
  • the other configuration is the same as that of the conventional digital signal receiving device 80, and therefore, the same portions are denoted by the same reference characters and description thereof will not be repeated.
  • the proc 45 includes a CPU 40, a timer 41, a display unit 42, a memory 44, and an input unit 46.
  • FIG. 9 is a block diagram for explaining in more detail the configuration of the IZF section 50 and the LMSK demodulation circuits 25a and 25b in the configuration shown in FIG.
  • the IZF unit 50 receives the outputs of the LMSK demodulation circuits 25a and 25b and adds a corresponding ID to the CPU 52, and receives the output of the CPU 52 and sends data to the interface on the host PC side. And circuit 56.
  • the CPU 52 includes a random access memory (hereinafter, referred to as a RAM) 54 that operates as a buffer.
  • a RAM random access memory
  • the CPU 52 outputs the active interrupt signal in response to the activation of either the interrupt signal 1 or the interrupt signal 2 output from the LMSK demodulation circuits 25a and 25b and indicating completion of data reception. Outputs internal clock CLK1 or CLK2.
  • the LMSK demodulation circuit that has received the internal clock CLK 1 or CLK 2 outputs data DATA 1 or DATA 2 to the CPU 52 in synchronization with the internal clock.
  • the CPU 52 adds the ID described in FIG. 5 to the received data and sequentially outputs the data to the IZF circuit 56.
  • FIG. 10 is a conceptual diagram showing an example of a format of data output from the LMSK demodulation circuits 25a and 25b.
  • FIG. 11 is a flowchart for explaining the operation of CPU 52 shown in FIG.
  • CPU 52 determines whether there is an interrupt from LMSK demodulation circuit 25a receiving station A (step S304), and executes the interrupt. If there is, data is read from the LMSK demodulation circuit 25a (for 24 bytes) (step S306).
  • the CPU 52 adds an ID corresponding to the read data (step S308), and stores it in the RAM 54 (step S310).
  • the CPU 52 determines whether there is an interrupt from the LMSK demodulation circuit 25b receiving the station B (step S312), and if there is an interrupt, the CPU 52 receives the data from the LMSK demodulation circuit 25b. Read (24 bytes) (Step S 314) o
  • the CPU 52 adds an ID corresponding to the read data (step S316), and stores it in the RAM 54 (step S318).
  • Step S320 when there is no interrupt from the LMSK demodulation circuit 25b, the CPU 52 advances the processing to Step S320.
  • the CPU 52 determines whether data is held in the RAM 54 (step S320), and if the data is held, transfers the data to the host PC (step S322).
  • step S320 the process returns to step S304 (step S320).

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Circuits Of Receivers In General (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

Selon l'invention, des signaux FM multiples sont reçus au moyen d'une antenne (12), démodulés dans le syntoniseur FM (14) et introduits dans le décodeur (15) de signaux FM multiples dans laquelle on extrait les signaux bande de base. L'UC (40) d'un ordinateur (120) reconstitue les données de programme d'après le signal bande de base ainsi extrait. L'UC (40) lance la reconstitution des données de programme après avoir commandé la commutation du réseau et reçu une quantité définie de données en paquets.
PCT/JP1998/000929 1997-03-07 1998-03-06 Recepteur numerique de signaux WO1998039864A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP53838198A JP3604703B2 (ja) 1997-03-07 1998-03-06 デジタル信号受信装置
EP98905792A EP0977386A4 (fr) 1997-03-07 1998-03-06 Recepteur numerique de signaux

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP5348897 1997-03-07
JP9/53488 1997-03-07

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WO1998039864A1 true WO1998039864A1 (fr) 1998-09-11

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PCT/JP1998/000929 WO1998039864A1 (fr) 1997-03-07 1998-03-06 Recepteur numerique de signaux

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EP (1) EP0977386A4 (fr)
JP (1) JP3604703B2 (fr)
WO (1) WO1998039864A1 (fr)

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JP2004343745A (ja) * 2003-05-08 2004-12-02 Harman Becker Automotive Systems Gmbh 無線放送受信機のバックグラウンドチューナにおける交通および運行情報受信

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DE10042320A1 (de) * 2000-08-29 2002-03-14 Trend Network Ag Verfahren zum Vorführen von Informationen
GB0207764D0 (en) * 2002-04-04 2002-05-15 Genrad Ltd Data conversion device

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JPH03277022A (ja) * 1990-03-27 1991-12-09 Pioneer Electron Corp Ｒｄｓ受信機における受信周波数選択方法
JPH04227127A (ja) * 1990-12-29 1992-08-17 Sony Corp データ放送受信装置
JPH04278741A (ja) * 1991-03-06 1992-10-05 Nippon Hoso Kyokai <Nhk> データチャンネル受信装置
JPH08191255A (ja) * 1995-01-10 1996-07-23 Sumitomo Electric Ind Ltd 多重放送受信装置
JPH08274666A (ja) * 1995-03-30 1996-10-18 Sanyo Electric Co Ltd Ｆｍ受信機およびこれに用いられる信号処理装置
JPH0915320A (ja) * 1995-06-30 1997-01-17 Mitsumi Electric Co Ltd 衛星受信装置及び衛星受信システム

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JPH08274667A (ja) * 1995-03-30 1996-10-18 Sanyo Electric Co Ltd Ｆｍ受信機およびこれに用いられる信号処理装置
JP3594428B2 (ja) * 1996-12-17 2004-12-02 三洋電機株式会社 Ｆｍ多重放送受信機

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JPH03277022A (ja) * 1990-03-27 1991-12-09 Pioneer Electron Corp Ｒｄｓ受信機における受信周波数選択方法
JPH04227127A (ja) * 1990-12-29 1992-08-17 Sony Corp データ放送受信装置
JPH04278741A (ja) * 1991-03-06 1992-10-05 Nippon Hoso Kyokai <Nhk> データチャンネル受信装置
JPH08191255A (ja) * 1995-01-10 1996-07-23 Sumitomo Electric Ind Ltd 多重放送受信装置
JPH08274666A (ja) * 1995-03-30 1996-10-18 Sanyo Electric Co Ltd Ｆｍ受信機およびこれに用いられる信号処理装置
JPH0915320A (ja) * 1995-06-30 1997-01-17 Mitsumi Electric Co Ltd 衛星受信装置及び衛星受信システム

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Publication number Priority date Publication date Assignee Title
JP2004343745A (ja) * 2003-05-08 2004-12-02 Harman Becker Automotive Systems Gmbh 無線放送受信機のバックグラウンドチューナにおける交通および運行情報受信

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EP0977386A1 (fr) 2000-02-02
EP0977386A4 (fr) 2006-06-28

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