WO1998013874A1 - Circuit integre hybride, de grande puissance et a frequences micro-ondes - Google Patents
Circuit integre hybride, de grande puissance et a frequences micro-ondes Download PDFInfo
- Publication number
- WO1998013874A1 WO1998013874A1 PCT/RU1996/000276 RU9600276W WO9813874A1 WO 1998013874 A1 WO1998013874 A1 WO 1998013874A1 RU 9600276 W RU9600276 W RU 9600276W WO 9813874 A1 WO9813874 A1 WO 9813874A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- height
- grounding
- integrated circuit
- crystal
- πlaτy
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
- H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48101—Connecting bonding areas at the same height, e.g. horizontal bond
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
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- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H01L2924/1517—Multilayer substrate
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- H01L2924/30105—Capacitance
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- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- the fasten- ing invention is not available in the area of electronic equipment, but the exact hybrid scheme of the midrange is more specific.
- the main task of the invention was to create a portable hybrid integrated circuit for the midrange, faster execution would improve the
- Terminals connecting contact parts suitable for grounding may be located between the walls of the inlet and the inlet to the isolator
- FIG. 2 the same as in Fig. 1 (view of the top); 20 FIG. 3 - another embodiment of the patented hybrid integrated circuit of the midrange (single); Fig. 4 - the same as in Fig. 3 (view of the top); Fig. 5 is another version of the implementation of the patented hybrid integrated circuit of the RMS range (one time); 25 Fig. 6 - the same as in Fig. 5 (view from above).
- Pa ⁇ en ⁇ ue maya m ⁇ schnaya gib ⁇ idnaya in ⁇ eg ⁇ alnaya s ⁇ ema S ⁇ CH dia ⁇ az ⁇ na 30 s ⁇ de ⁇ zhi ⁇ me ⁇ alliches ⁇ e ele ⁇ - and ⁇ e ⁇ l ⁇ v ⁇ d present ⁇ sn ⁇ vanie 1 ( ⁇ ig.1) with vys ⁇ u ⁇ m 2 on ⁇ m us ⁇ an ⁇ vlen and za ⁇ e ⁇ len ⁇ is ⁇ all 3 bes ⁇ usn ⁇ g ⁇ ⁇ lu ⁇ v ⁇ dni ⁇ v ⁇ g ⁇ ⁇ ib ⁇ a, na ⁇ ime ⁇ , ⁇ anzis ⁇ a ZP603B-5 ⁇ azme ⁇ m 0,5x0,45x0, 3 mm with contact plates 4, located on the base 1 of the dielectric board 5, for example, a standard size 30x48x0.5 mm with a standard design of 6 metalization on the front panel of plate 5 and an electronic grounding metal 7 on the
- a recess 10 was made, increasing the length and width of the height of 2 bases, for example, by 1 mm, and the depth of 10 was cut out by 0.2 mm. Days of deepening 10 long and wide
- the upper part of the elevation 2 of the base 1, free from the crystal 3, is connected to the bottom of the recess 10, for example, is soldered ( ⁇ - ⁇ ) or connected to the interface.
- Grounding chas ⁇ i ⁇ n ⁇ a ⁇ ny ⁇ ⁇ l ⁇ schad ⁇ 4 ⁇ is ⁇ alla 3 vy ⁇ lnen ⁇ che ⁇ ez ⁇ ve ⁇ s ⁇ ie 11 in the bottom of recess 10, and 0 za ⁇ lnenn ⁇ e ele ⁇ - ⁇ e ⁇ l ⁇ v ⁇ dyaschim ma ⁇ e ⁇ ial ⁇ m, na ⁇ ime ⁇ , ⁇ i ⁇ em ( ⁇ i-8 ⁇ ), ⁇ ym ⁇ i ⁇ ayan ⁇ dn ⁇ recess 10 vys ⁇ u ⁇ u ⁇ 2 or ⁇ ve ⁇ s ⁇ iya m ⁇ gu ⁇ by ⁇ za ⁇ ascheny galvaniches ⁇ i, na ⁇ ime ⁇ , copper with the next exposure to nickel and gold.
- the distance between Crystal 3 and 1 1 for grounding is selected to be 100 ⁇ m, and 5 the distance between Crystal 3 and 8 to 80 ⁇ M is also selected.
- a frame in the form of 12 for example, a width of 1 mm, a height of 0.3 mm, and at a height of 1.2 mm, a wide height of 14 mm , 2 mm.
- Terminals connecting contact areas 4 to 5 ground are located between openings 8 and 5 apart from a small port
- a variant of the implementation of the patented circuit is provided, where the grounding is connected to the side wall of the outlet 8 at the outlet of 3. 0 box. 5 and 6, there is one more version of the implementation of the patented circuit with grounding terminals 15 located between the walls of the outlet 8 in the board 5 and the connection to the terminal 3 and connected to the terminal
- the invention may be used in the consumer microelectronics industry.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structure Of Printed Boards (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Junction Field-Effect Transistors (AREA)
- Credit Cards Or The Like (AREA)
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-1998-0703938A KR100420792B1 (ko) | 1996-09-26 | 1996-09-26 | 파워마이크로웨이브하이브리드집적회로 |
US09/077,630 US6057599A (en) | 1996-09-26 | 1996-09-26 | Hybrid high-power microwave-frequency integrated circuit |
RU98111687/28A RU2148872C1 (ru) | 1996-09-26 | 1996-09-26 | Мощная гибридная интегральная схема свч диапазона |
PCT/RU1996/000276 WO1998013874A1 (fr) | 1996-09-26 | 1996-09-26 | Circuit integre hybride, de grande puissance et a frequences micro-ondes |
JP51553998A JP3354575B2 (ja) | 1996-09-26 | 1996-09-26 | パワーマイクロ波ハイブリッド集積回路 |
SE9801793A SE522049C2 (sv) | 1996-09-26 | 1998-05-20 | Integrerad mikrovåghybridströmkrets |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/RU1996/000276 WO1998013874A1 (fr) | 1996-09-26 | 1996-09-26 | Circuit integre hybride, de grande puissance et a frequences micro-ondes |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998013874A1 true WO1998013874A1 (fr) | 1998-04-02 |
Family
ID=20130039
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/RU1996/000276 WO1998013874A1 (fr) | 1996-09-26 | 1996-09-26 | Circuit integre hybride, de grande puissance et a frequences micro-ondes |
Country Status (6)
Country | Link |
---|---|
US (1) | US6057599A (ru) |
JP (1) | JP3354575B2 (ru) |
KR (1) | KR100420792B1 (ru) |
RU (1) | RU2148872C1 (ru) |
SE (1) | SE522049C2 (ru) |
WO (1) | WO1998013874A1 (ru) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030062610A1 (en) * | 2001-09-28 | 2003-04-03 | Kovacs Alan L. | Multilayer thin film hydrogen getter |
KR100547709B1 (ko) * | 2003-07-07 | 2006-01-31 | 삼성전자주식회사 | 자기 치유 파장분할다중방식 수동형 광 가입자망 |
DE102008026765A1 (de) | 2008-04-16 | 2009-10-22 | Rohde & Schwarz Gmbh & Co. Kg | Mikrowellen-Baugruppe |
RU2659752C1 (ru) * | 2017-05-22 | 2018-07-03 | Андрей Александрович Григорьев | Мощная гибридная интегральная схема свч-диапазона |
CN111586964A (zh) * | 2020-05-25 | 2020-08-25 | 上海航天电子通讯设备研究所 | 基于lcp基板的高密度高频微波组件制备方法及微波组件 |
RU2750860C1 (ru) * | 2020-09-21 | 2021-07-05 | Акционерное общество "Научно-производственное предприятие "Исток" имени А.И. Шокина" (АО "НПП "Исток" им. Шокина") | Гибридная интегральная схема свч-диапазона |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1426539A (en) * | 1973-03-10 | 1976-03-03 | Tokyo Shibaura Electric Co | Multiple chip integrated circuits and method of manufacturing the same |
DE3501710A1 (de) * | 1985-01-19 | 1986-07-24 | Allied Corp., Morristown, N.J. | Leiterplatte mit integralen positioniermitteln |
US4975065A (en) * | 1989-09-26 | 1990-12-04 | Avantek, Inc. | Microwave circuit module connector |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4115043A1 (de) * | 1991-05-08 | 1997-07-17 | Gen Electric | Dichtgepackte Verbindungsstruktur, die eine Kammer enthält |
US5073814A (en) * | 1990-07-02 | 1991-12-17 | General Electric Company | Multi-sublayer dielectric layers |
US5559363A (en) * | 1995-06-06 | 1996-09-24 | Martin Marietta Corporation | Off-chip impedance matching utilizing a dielectric element and high density interconnect technology |
-
1996
- 1996-09-26 RU RU98111687/28A patent/RU2148872C1/ru not_active IP Right Cessation
- 1996-09-26 US US09/077,630 patent/US6057599A/en not_active Expired - Fee Related
- 1996-09-26 KR KR10-1998-0703938A patent/KR100420792B1/ko not_active IP Right Cessation
- 1996-09-26 JP JP51553998A patent/JP3354575B2/ja not_active Expired - Lifetime
- 1996-09-26 WO PCT/RU1996/000276 patent/WO1998013874A1/ru active IP Right Grant
-
1998
- 1998-05-20 SE SE9801793A patent/SE522049C2/sv not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1426539A (en) * | 1973-03-10 | 1976-03-03 | Tokyo Shibaura Electric Co | Multiple chip integrated circuits and method of manufacturing the same |
DE3501710A1 (de) * | 1985-01-19 | 1986-07-24 | Allied Corp., Morristown, N.J. | Leiterplatte mit integralen positioniermitteln |
US4975065A (en) * | 1989-09-26 | 1990-12-04 | Avantek, Inc. | Microwave circuit module connector |
Also Published As
Publication number | Publication date |
---|---|
KR100420792B1 (ko) | 2004-05-31 |
SE522049C2 (sv) | 2004-01-07 |
US6057599A (en) | 2000-05-02 |
RU2148872C1 (ru) | 2000-05-10 |
SE9801793D0 (sv) | 1998-05-20 |
JP3354575B2 (ja) | 2002-12-09 |
JP2000503482A (ja) | 2000-03-21 |
SE9801793L (sv) | 1998-05-20 |
KR19990071662A (ko) | 1999-09-27 |
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