WO1997011497A1 - Procede de fabrication d'un transistor a effet de champ vertical - Google Patents

Procede de fabrication d'un transistor a effet de champ vertical Download PDF

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Publication number
WO1997011497A1
WO1997011497A1 PCT/JP1995/001885 JP9501885W WO9711497A1 WO 1997011497 A1 WO1997011497 A1 WO 1997011497A1 JP 9501885 W JP9501885 W JP 9501885W WO 9711497 A1 WO9711497 A1 WO 9711497A1
Authority
WO
WIPO (PCT)
Prior art keywords
arsenic
epi layer
layer
concentration
effect transistor
Prior art date
Application number
PCT/JP1995/001885
Other languages
English (en)
Japanese (ja)
Inventor
Shiroo Kamohara
Kouzou Sakamoto
Satoshi Meguro
Yuzuru Fujita
Tetsuo Iijima
Eiji Yanokura
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1995/001885 priority Critical patent/WO1997011497A1/fr
Publication of WO1997011497A1 publication Critical patent/WO1997011497A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors

Definitions

  • the present invention relates to a vertical field effect transistor, and more particularly to a method for manufacturing a vertical field effect transistor having high output and high-speed switching characteristics.
  • Japanese Patent Application Laid-Open No. 63-175754 / 78 discloses that an N ion implanted layer is formed by ion implantation to not only increase the concentration of only the surface but also make the entire N + connection region uniform. It has an O degree distribution to reduce the on-resistance.
  • n-type impurity ions are implanted to form an n + connection region.
  • Implanted impurity ions, or low port n- A method is described in which a conductive type drain region is formed by epitaxial growth, a high-concentration n + connection region is grown, and a low-concentration n-conductive region is formed by epitaxy growth. It is described that the parasitic capacitance is reduced and the resistance during conduction is reduced by these methods. Disclosure of the invention
  • Japanese Unexamined Patent Publication No. 63-175574 / 98 discloses that not only the concentration on the surface alone is increased, but also the N ions which can make the entire N + connection region have a uniform distribution. Since high-energy ions are implanted, the port on the substrate surface could not be sufficiently lowered, and it was not possible to reduce the return volume S between the gate and drain.
  • the realization method is to reduce the n-one conductivity type drain region.
  • the method of implanting n-type impurity ions to form an n + contact region after forming by epitaxial growth, and then implanting p-type impurity ions requires two ion implantation steps.
  • the n-type impurity ion concentration near the substrate surface is made to be isotopically low by offsetting by the p-type impurity ion, so that the carrier is small in spite of the fact that the amount of impurities including np is very large.
  • n + connection region is formed at the same depth as immediately below the gate even in the source region, so that latch-up due to breakdown in the case of avalanche breakdown is sufficiently suppressed. There was also a problem that it was not done.
  • the present invention provides a manufacturing method in which the n-type impurity concentration in the vicinity of the substrate surface immediately below the gate is sufficiently reduced, and the impurity concentration distribution is increased toward the inside of the substrate in one step. Aim.
  • Another object of the present invention is to provide a vertical field effect transistor that suppresses latchup.
  • the surface concentration is equal to or less than the concentration of the N-epi layer, and the peak concentration is N. 500 ke so that the range in the depth direction of the region above the concentration of the N-epi layer and above the concentration of the N-epi layer is located between the surface of the N-epi layer and the lower end of the channel region.
  • Arsenic is ion-implanted with ⁇ energy of V or more. In this method, since arsenic is used as an impurity, impurity diffusion is small, and the concentration near the substrate surface does not increase.
  • the surface concentration is equal to or less than the concentration of the N-epi layer, and the range in the depth direction of the region where the portability of the N-epi layer is equal to or more than the N-epi layer is N-epi.
  • a vertical field-effect transistor having an arsenic distribution located therein is formed by ion implantation of arsenic with an energy of 500 keV or more using the gate polysilicon and the resist as a mask. in this case, Since the breakdown current path changes depending on the arsenic distribution directly below the channel, the latch-up phenomenon is suppressed.
  • FIG. 1 is a sectional view of a vertical field-effect transistor according to the present invention.
  • FIG. 2 is a view showing an impurity distribution along a depth direction of a cut surface at the center of a gate electrode.
  • FIG. 3 is a conceptual diagram of Embodiment 1 of the manufacturing method.
  • FIG. 4 is a conceptual diagram of Embodiment 1 of the manufacturing method.
  • FIG. 5 is a conceptual diagram of Embodiment 1 of the manufacturing method.
  • FIG. 6 is a conceptual diagram of Embodiment 2 of the manufacturing method.
  • FIG. 7 is a conceptual diagram of Embodiment 2 of the manufacturing method.
  • Fig. 8 is a conceptual diagram of Embodiment 2 of the manufacturing method.
  • FIG. 9 is a diagram showing a change in on-resistance when the dose of the ⁇ energy arsenic implantation is changed.
  • FIG. 10 is a diagram showing a change in the feedback capacitance S with respect to the impurity distribution shape immediately below the gate.
  • FIG. 11 is a diagram showing a conventional impurity distribution.
  • FIG. 12 is a diagram showing a conventional impurity distribution.
  • FIG. 13 is a view showing a conventional impurity distribution.
  • FIG. 14 is a view showing a vertical field effect transistor structure according to the present invention.
  • FIG. 15 is a diagram showing a conventional structure for avoiding destruction due to latch-up.
  • FIG. 16 shows a method for manufacturing a vertical field-effect transistor structure according to the present invention.
  • FIG. 17 is a view showing a method of manufacturing a vertical field-effect transistor structure according to the present invention.
  • FIG. 18 is a diagram showing a breakdown current path in the embodiment according to the present invention.
  • FIG. 19 is a diagram showing a breakdown current path in the conventional structure.
  • FIG. 1 is a sectional view of a vertical field-effect transistor according to an embodiment of the present invention.
  • the structure shown in Fig. 1 has a structure in which an N-epi layer 4 is laminated on the surface of an N-substrate 5, and in addition to the channel region 3 and the N + source region 2 inside the N-epi layer 4, Implanted layer 1 is formed.
  • a gate electrode 6 is formed on the N-epi layer 4 via an oxide film.
  • the surface concentration of the high-energy arsenic-implanted layer 1 becomes less than the concentration of the N-epi layer 4 and the peak concentration is more than the concentration of the N-epi layer 4
  • the distribution in the depth direction in which the S-degree of the N-epi layer 4 is equal to or more than the S degree is a distribution located between the surface of the N-epi scrap 4 and the lower end 10 of the channel region.
  • This high-energy arsenic implanted layer 1 is formed on the entire surface of the N-epi layer 4 by using high-energy ion implantation of 500 keV or more.
  • FIG. 2 shows the impurity distribution along the depth direction 11 of the cut surface at the center of the gate electrode 6 in FIG.
  • the horizontal axis in FIG. 2 represents the depth direction 11 and the vertical axis represents the impurity concentration.
  • an N-epi layer and a high energy arsenic implanted layer 1 are formed on an N substrate 5. As shown in Fig.
  • the surface concentration is lower than the concentration of the N-epi layer
  • the peak concentration is higher than the concentration of the N-epi layer
  • the range is a distribution located between the surface of the N-epi layer and the bottom of the channel region.
  • the impurity concentration of the N-epi layer 4 and the impurity concentration of the N-connection region 8 do not always match, but in the present invention, the impurity concentration of the N-epi layer 4 and the impurity concentration of the N-connection region 8 are different. The impurity concentrations are completely consistent.
  • FIG. 3 One embodiment of the manufacturing method for the embodiment shown in FIG. 1 is shown in FIG. 3, FIG. 4, and FIG.
  • FIGS. 3, 4, and 5 One embodiment of the manufacturing method for the embodiment shown in FIG. 1 is shown in FIGS. 3, 4, and 5.
  • the N-epi layer 4 is seeded on the N substrate 5 by epitaxial growth (Fig. 3).
  • phosphorus is doped to make the N-epi layer N-type.
  • a high-energy arsenic implanted layer 1 is formed using high-energy ion implantation of 500 keV or more (Fig. 4). After the above steps, a channel region 3 and an N + source region 2 are formed (FIG. 5).
  • the channel region 3 is formed by implanting boron into the substrate 5 after forming a predetermined mask, and further diffusing boron by heat treatment.
  • the lower end of the channel region 3 is located deeper than the lower end of the high-energy arsenic implanted layer 1.
  • the N + source region 2 is formed by implanting arsenic after forming a predetermined mask. In the arsenic distribution formed in Fig. 4, the diffusion coefficient of arsenic is different. It is not changed by the heat treatment shown in Fig. 5 because it is smaller than the impurity by one order of magnitude.
  • FIG. 6, FIG. 7, and FIG. The channel region 3 is formed after the N-epi layer 4 is laminated on the N substrate 5 by epitaxial growth (FIG. 6).
  • phosphorus is doped to make the N-epi layer N-type.
  • the channel region 3 is formed by implanting po- ron into the substrate 5 after forming a predetermined mask, and further diffusing boron by heat treatment.
  • a high-energy arsenic implanted layer 1 is formed using high-energy ion implantation of 500 keV or more (Fig. 7).
  • the lower end of the channel region 3 is located deeper than the lower end of the high-energy arsenic implanted layer 1.
  • an N + source region 2 is formed (FIG. 8).
  • the N + source region 2 is formed by implanting arsenic after forming a predetermined mask. Since the diffusion coefficient of arsenic is one order of magnitude lower than that of other impurities, the impurity distribution formed in Fig. 7 does not change due to the heat treatment in Fig. 8.
  • FIG. 9 shows a change in on-resistance when the dose of the high-energy arsenic implantation is changed in the embodiment shown in FIG. Fig. 9 shows the calculation results using a device simulator.
  • the horizontal axis in FIG. 9 shows the arsenic dose, and the vertical axis shows the on-resistance. From Fig. 9, it can be seen that if arsenic is implanted at 1.0E16 (cm-2), a low resistance with an on-resistance of 100m ⁇ mm2 or less can be obtained. This value is at the same level as when only N + connection region 7 is formed.
  • FIG. 10 shows a change in the feedback capacitance with respect to the impurity distribution shape immediately below the gate.
  • FIG. 10 shows a calculation result using a device simulator.
  • the axis represents the impurity distribution shape just below the gate, and the vertical axis represents the feedback capacitance. It can be seen that the feedback capacitance can be reduced when the high energy arsenic implanted layer 1 is formed, as compared with the case where only the N + connection region 7 is formed. When the N + connection region 7 is not formed, the feedback capacitance S can be further reduced, but as shown in FIG. 9, the on-resistance becomes as high as about 120 m ⁇ mm 2. From FIGS. 9 and 10, it can be seen that this embodiment is effective not only in reducing the conventional two steps to one step but also in reducing the resistance and the feedback capacitance. Due to the reduction of the resistance and the reduction of the return capacitance, the vertical field effect transistor according to the present embodiment has a high output and a high speed switching characteristic.
  • FIGS. 11, 12 and 13 show differences in impurity distribution between the conventional technology and the high-energy arsenic-implanted layer 1 according to the embodiment of the present invention.
  • the horizontal axis in FIGS. 11, 12, and 13 represents the depth direction 11, and the vertical axis represents the impurity concentration.
  • N + connection region 7 is formed by N + epi layer 1 101 on top of N-epi layer 4, and N-connection region 8 is further formed by N-epi layer 1
  • An example in the case of forming with 102 is shown.
  • the diffusion coefficient of arsenic is at least one order of magnitude smaller than that of other impurities, so that there is a flat portion of the impurity distribution.
  • an N + connection region 7 is formed on the N-epi layer 4 by the N + epi layer 1 101, and the surface of the N + connection region 7 is opposite to arsenic.
  • An embodiment in which the N-connection region 8 is formed by forming a conductive type polon diffusion layer 1221 will be described.
  • boron is introduced to form the N-connection region 8. When the high energy arsenic implanted layer 1 is used, no boron exists in the N-connection region 8.
  • FIGS. 11 and 12 require two steps to form the N + connection region 7 and the N ⁇ connection region 8.
  • the N + connection region 7 and the N ⁇ connection region 8 can be formed in one step, so that the cost per chip is reduced.
  • FIG. 13 shows an embodiment in which high-energy ion implantation is used to flatten the impurity concentration of the N + connection region 7.
  • the surface concentration of the N + connection region 7 formed by the high-energy ion-implanted layer 1301 shown in FIG. 13 is higher than the concentration of the N-epi layer 4. Furthermore, in order to form such a distribution, it is necessary to use phosphorus instead of arsenic.
  • FIG. 15 shows an embodiment of the prior art.
  • the N-epi layer 4 is removed above the N-substrate 5, and the channel region 3, N + source region 2, N + connection region 7, N + -The connection area 8 is formed.
  • a P + connection region 9 is formed to avoid destruction due to latch-up.
  • a total of three steps are required to form the N + connection region 7, the N- connection region 8, and the P + connection region 9. The reason why the conventional P + connection region 9 is effective in avoiding latch-up will be described with reference to FIG. FIG.
  • the vertical field effect transistor has an edge portion of the gate electrode 6 in the channel region 3.
  • the base turns on and a large current flows. This phenomenon is We call it top. If the vertical field-effect transistor latches up, the device will be destroyed. In order to prevent latch-up, it is necessary to suppress the voltage rise at the edge of the gate electrode 6.
  • the P + connection region 9 is a technology that suppresses an increase in compressibility at the edge of the gate electrode 6 due to a voltage drop by reducing the resistance of the channel portion 3.
  • an N + connection region, an N ⁇ connection region, and a P + connection region are formed in a total of three steps.
  • FIG. 14 shows an embodiment of the present invention.
  • Fig. 14 shows an N + connection region, an N- connection region, and a device structure that enables a structure to avoid latch-up to be formed in a single process, which was conventionally formed in three processes. It is.
  • an N-epi layer 4 is laminated on an N substrate 5, and a channel region 3 and an N + source region 2 are formed in the region of the N-epi layer 4.
  • the surface area in the depth direction where the surface concentration is less than the concentration of the N-epi layer 4 and higher than the portability of the N-epi layer 4 is N-
  • the arsenic distribution located between the surface of the epitaxial layer 4 and the lower end 10 of the channel region, and the area directly below the channel region 10 in the depth direction where the concentration of the N-epi layer is higher than the lower end of the channel region 1 It has a rectangular high-energy arsenic implanted layer 12 which simultaneously constitutes an arsenic distribution located between 0 and the N substrate 5.
  • the arsenic distribution directly under the gate 3 ⁇ 4 pole 6 of the rectangular high-energy arsenic implanted layer 12 plays a role in obtaining high output and high switching characteristics, and the arsenic distribution directly under the channel region 10 avoids damage due to latch-up. Play a role.
  • the reason why the arsenic distribution immediately below the channel region 10 avoids destruction due to latch-up will be described with reference to FIG. In the prior art shown in FIG. 19, the avalanche breakdown occurs near the left end of the gate electrode 6 in the channel region 3. On the other hand, in the embodiment shown in FIG. + Source area 2 Occurs near the left end. Therefore, the breakdown current flows along the path 1801.
  • FIGS. 16 and 17 show the manufacturing method of the embodiment shown in FIG.
  • the manufacturing method shown in Fig. 16 and Fig. 17 makes it possible to form the N + connection area, N-connection area, and P + connection area in one process, which were conventionally formed in three processes.
  • An N-epi layer 4 is formed on the substrate 5 and a channel region 3 and an N + source region 2 are formed in the N-epi layer 4 (FIG. 16).
  • phosphorus is doped to make the N-epi layer N-type.
  • the channel region 3 is formed by implanting boron into the substrate 5 after forming a predetermined mask, and further diffusing boron by heat treatment.
  • the N + source region 2 is formed by implanting arsenic after forming a predetermined mask.
  • a resist 1701 is applied on the polysilicon, and the resist 1701 is applied only to a predetermined region by photolithography. Remove and remove. By etching the polysilicon after removing the resist 1701, the structure shown in Fig. 17 can be formed.
  • a rectangular high-energy arsenic implanted layer 12 is formed by high-energy arsenic implantation 1702.
  • a rectangular high energy arsenic implanted layer 12 is formed.
  • the lower end of the arsenic distribution directly below the gate 3 ⁇ 4 pole 6 is located above the lower end of the channel region 3, and the upper end of the arsenic distribution immediately below the channel region 3 is located below the lower end of the channel region 3.
  • the positions of the arsenic distribution directly below the gate electrode 6 and the arsenic distribution directly below the channel region 3 in the depth direction 11 can be separately specified by the resist film thickness and the implantation energy.
  • high-energy arsenic implantation 1702 By using high-energy arsenic implantation 1702, a structure that conventionally required three processes can be configured by the ⁇ process.
  • N + connection region and the N ⁇ connection region which are conventionally formed in two steps, can be formed in one step, and the cost per chip can be made equal to the case where only the N + connection region is formed.
  • Another advantage of the present invention is that the N + connection region conventionally formed in three steps, The structure to avoid destruction due to N-connection area and latch-up can be formed in one process, and the unit cost of the chip can be reduced to less than the conventional one.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Cette invention concerne un procédé de fabrication d'un transistor à effet de champ vertical qui possède un rendement et des propriétés de commutation élevés. Selon ce procédé, une seule étape est nécessaire à la formation d'une zone de connexion N+ et d'une zone de connexion N-, au lieu des deux étapes traditionnelles. A cette fin, de l'arsenic est implanté dans une zone N-épitaxiale par un processus d'implantation ionique d'une grande énergie et d'au moins 500 keV. Ce procédé permet d'obtenir une répartition verticale des impuretés dans le substrat de type basse (ou sensiblement basse)-élevée-basse (ou sensiblement basse) par rapport à la concentration de la couche N-épitaxiale.
PCT/JP1995/001885 1995-09-20 1995-09-20 Procede de fabrication d'un transistor a effet de champ vertical WO1997011497A1 (fr)

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Application Number Priority Date Filing Date Title
PCT/JP1995/001885 WO1997011497A1 (fr) 1995-09-20 1995-09-20 Procede de fabrication d'un transistor a effet de champ vertical

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1995/001885 WO1997011497A1 (fr) 1995-09-20 1995-09-20 Procede de fabrication d'un transistor a effet de champ vertical

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WO1997011497A1 true WO1997011497A1 (fr) 1997-03-27

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002084745A2 (fr) 2001-04-11 2002-10-24 Silicon Wireless Corporation Dispositifs semi-conducteurs de puissance presentant des zones ecran de base s'etendant lateralement qui empechent de traverser la base et procedes de fabrication associes
EP1770787A2 (fr) * 2005-10-03 2007-04-04 AMI Semiconductor Belgium BVBA Dispositif semi-conducteur avec un transistor MOS et sa méthode de fabrication
EP2362422A3 (fr) * 2001-04-11 2012-01-04 Silicon Semiconductor Corporation Dispositif semi-conducteur vertical de puissance et sa méthode de fabrication
CN103296089A (zh) * 2012-02-29 2013-09-11 株式会社东芝 半导体器件及其制造方法
JP2014063949A (ja) * 2012-09-24 2014-04-10 Sumitomo Electric Ind Ltd 炭化珪素半導体装置およびその製造方法
WO2017204964A1 (fr) * 2016-05-26 2017-11-30 General Electric Company Dispositif à semi-conducteur et son procédé de fabrication

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Publication number Priority date Publication date Assignee Title
JPS63133678A (ja) * 1986-11-26 1988-06-06 Nec Corp 縦型電界効果トランジスタの製造方法
JPH01253966A (ja) * 1988-04-01 1989-10-11 Nec Corp 縦型電界効果トランジスタ
JPH01291469A (ja) * 1988-05-19 1989-11-24 Sanyo Electric Co Ltd パワーｍｏｓｆｅｔの製造方法
JPH0349266A (ja) * 1989-07-18 1991-03-04 Fuji Electric Co Ltd Ｍｏｓ型半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63133678A (ja) * 1986-11-26 1988-06-06 Nec Corp 縦型電界効果トランジスタの製造方法
JPH01253966A (ja) * 1988-04-01 1989-10-11 Nec Corp 縦型電界効果トランジスタ
JPH01291469A (ja) * 1988-05-19 1989-11-24 Sanyo Electric Co Ltd パワーｍｏｓｆｅｔの製造方法
JPH0349266A (ja) * 1989-07-18 1991-03-04 Fuji Electric Co Ltd Ｍｏｓ型半導体装置

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002084745A2 (fr) 2001-04-11 2002-10-24 Silicon Wireless Corporation Dispositifs semi-conducteurs de puissance presentant des zones ecran de base s'etendant lateralement qui empechent de traverser la base et procedes de fabrication associes
EP2362422A3 (fr) * 2001-04-11 2012-01-04 Silicon Semiconductor Corporation Dispositif semi-conducteur vertical de puissance et sa méthode de fabrication
EP2362423A3 (fr) * 2001-04-11 2012-01-04 Silicon Semiconductor Corporation Dispositif semi-conducteur vertical de puissance et sa méthode de fabrication
EP1770787A2 (fr) * 2005-10-03 2007-04-04 AMI Semiconductor Belgium BVBA Dispositif semi-conducteur avec un transistor MOS et sa méthode de fabrication
EP1770787A3 (fr) * 2005-10-03 2008-06-04 AMI Semiconductor Belgium BVBA Dispositif semi-conducteur avec un transistor MOS et sa méthode de fabrication
CN103296089A (zh) * 2012-02-29 2013-09-11 株式会社东芝 半导体器件及其制造方法
JP2014063949A (ja) * 2012-09-24 2014-04-10 Sumitomo Electric Ind Ltd 炭化珪素半導体装置およびその製造方法
WO2017204964A1 (fr) * 2016-05-26 2017-11-30 General Electric Company Dispositif à semi-conducteur et son procédé de fabrication
US10541300B2 (en) 2016-05-26 2020-01-21 General Electric Company Semiconductor device and method of making thereof
US11063115B2 (en) 2016-05-26 2021-07-13 General Electric Company Semiconductor device and method of making thereof
EP4290583A3 (fr) * 2016-05-26 2023-12-27 General Electric Company Procédé de fabrication d'un dispositif à semi-conducteur

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