WO1994013018A1 - Transistor a couches minces possedant un dielectrique de grille a trois couches, son procede de fabrication, et affichage a matrice active muni d'une pluralite de transistors de ce type - Google Patents

Transistor a couches minces possedant un dielectrique de grille a trois couches, son procede de fabrication, et affichage a matrice active muni d'une pluralite de transistors de ce type Download PDF

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Publication number
WO1994013018A1
WO1994013018A1 PCT/CA1992/000519 CA9200519W WO9413018A1 WO 1994013018 A1 WO1994013018 A1 WO 1994013018A1 CA 9200519 W CA9200519 W CA 9200519W WO 9413018 A1 WO9413018 A1 WO 9413018A1
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WO
WIPO (PCT)
Prior art keywords
thin film
layer
film transistor
films
gate insulator
Prior art date
Application number
PCT/CA1992/000519
Other languages
English (en)
Inventor
David Waechter
Original Assignee
Litton Systems Canada Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Litton Systems Canada Limited filed Critical Litton Systems Canada Limited
Priority to EP92923642A priority Critical patent/EP0672301A1/fr
Priority to CA002150573A priority patent/CA2150573A1/fr
Priority to PCT/CA1992/000519 priority patent/WO1994013018A1/fr
Priority to JP6512598A priority patent/JPH08503815A/ja
Publication of WO1994013018A1 publication Critical patent/WO1994013018A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/471—Inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/471—Inorganic layers
    • H01L21/473—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT

Definitions

  • T h in film transistor having a triple layer dielectric ⁇ ate insula tor method of fabricating such a thin film transistor an d an active matrix display having a plurality of such thin film tran ⁇ sistors.
  • This invention relates in general to gate insulators 5 in thin film transistors (TFTs) , and more particularly to a triple layer dielectric for use as the TFT gate insulator in an active matrix liquid crystal display (AMLCD) .
  • TFTs thin film transistors
  • AMLCD active matrix liquid crystal display
  • AMLCDs Active matrix liquid crystal displays
  • AMLCDs will increasingly replace well known CRT technology for such applications as television and computer terminal monitors since the AMLCD has significant advantages over CRT technology in terms of power consumption, weight and volume.
  • a TFT-based AMLCD typically comprises top and bottom polarizers and a TFT plate containing a matrix of transistors for selectively enabling and disabling associated LCD pixels.
  • gate dielectric is especially important for electro-optic display media such as electroluminescent films and NCAP (nematic
  • the gate insulating layer of a TFT comprises a single or double layer of appropriate dielectric material such a Si 3 N 4 , Sio 2 , SiO x N ⁇ , Ta 2 0 5 ,
  • SUBSTITUTE SHEET dielectric is provided for use as the TFT gate insulation in an active matrix display.
  • an active matrix display having a plurality of thin film transistors for selectively enabling and disabling pixels of said display, the improvement comprising a gate insulator for each of said thin film transistors having a triple layer dielectric.
  • Figure 2 is a cross-sectional view of a capacitor structure fabricated for break-down field measurements between single layer and triple layer dielectrics
  • Figures 3 and 4 show breakdown field distributions for Si0 2 and triple layer insulation of Figure 2 with aluminum and chromium electrodes, respectively;
  • Figure 5 shows drain current as a function of gate voltage for CdSe TFTs with Si0 2 and triple layer gate insulation;
  • Figure 6 shows the drain current characteristics of a CdSe TFT at high drain voltage, for a TFT having triple layer gate insulation in accordance with the present invention
  • Figure 7 shows drain current as a function of gate
  • Figure 8 shows the time dependence of the drain current after switching from the OFF to ON state for CdSe TFTs with Si0 2 and ONO gate insulation.
  • a layer of chromium (Cr) is deposited on a Corning 7059 glass substrate 13, and patterned to form gate electrode 14.
  • a 5000 A film of triple layer dielectric, serving as the gate insulator 15, is then deposited, followed by a 500 A layer of the evaporated CdSe semiconductor.
  • the semiconductor layer 16 is patterned and then passivated with a SiO x layer 17.
  • ITO indium tin oxide
  • the final two steps in the fabrication process are to open up contact vias 19a and 20a in the passivation oxide, deposit the source/drain metal, and pattern the metal to form the source and drain electrodes 19 and 20.
  • the contact vias are formed by a dry etch process using reactive gasses. Since conductivity properties of the semiconductor are disturbed when the semiconductor is uncovered as a result of the reactive ion etch, a sputter etch is performed, according to the present invention, to etch away contaminated areas. A final anneal is then performed to ensure good oh ic contact between the semiconductor 16 and the source and drain electrodes 19 and 20.
  • the gate insulation 15 is fabricated as a triple layer comprising the two oxide layers 4 and 5, and an intermediate dielectric layer 6.
  • the insulation layer 15, as sub-divided into layers 4, 5, and 6 was characterized by total thickness of 500 nanometres, divided roughly evenly in thickness for each
  • the dielectric layer 6 may be of reduced thickness relative to oxide layers 4 and 5, in order to yield a slightly co pressive stress, as discussed below in greater detail.
  • the layers 4, 6 and 5 are fabricated as Si0 2 /Si 3 N 4 /Si0 2 .
  • the layers are formed as Si0 2 /Al 2 0 3 /Si0 2 .
  • the layers are formed as Si0 2 /Ta 2 0 5 /Si0 2 .
  • nonstoichiometric films may be utilized wherein the oxide and dielectric layers may be designated as SiO x , A10 x , SiN x , TaO x , etc.
  • a layer of semiconductor material 16 is deposited on the gate insulation layer in the usual manner.
  • Metallic source and drain electrodes 19 and 20 are then deposited so as to contact the semiconductor layer.
  • An additional pixel pad connector 18 may be deposited so as to contact the source electrode 20 where the TFT is to be used in an AMLCD.
  • a transparent alignment layer 21 is deposited so as to overly the entire structure.
  • the triple layer gate insulation 15 was deposited by plasma enhanced chemical vapor deposition (PECVD) , although other fabrication techniques may be used.
  • PECVD plasma enhanced chemical vapor deposition
  • the films 4, 5 and 6 are preferably deposited at 300°C to a combined total thickness which is sufficient for high voltage operation.
  • the triple layer gate insulation of the present invention is characterized by a much higher dielectric strength than the prior art single layer of Si0 2 , and provides similar transconductance in a TFT device.
  • the capacitor structure of Figure 2 was fabricated. More particularly, two capacitors were fabricated - one to measure the breakdown characteristics of a single layer
  • SUBSTITUTE SHEET oxide and a second capacitor fabricated to test the breakdown characteristics of the triple layer dielectric of the present invention.
  • the Si0 2 layers were deposited using gas phase combinations of SiH 4 , He, N 2 0.
  • the SiN x films were deposited in the same reactor using SiH 4 , He, NH 3 and N 2 .
  • the deposition system utilized a capacitively coupled parallel plate design with 13.56 megahertz as the excitation frequency. Substrates were placed on the grounded lower electrode, and the deposition rate was 8.5 nm/min for Si0 2 and 2.3 nm/min for SiN x .
  • the resulting structure of Figure 2 shows a glass substrate 20, onto which a "layer under test" 21 of either Si0 2 according to the first test capacitor, or ONO according to the second test capacitor, was deposited.
  • the dielectric layer 21 was 150 n thick in the case of the first capacitor utilizing Si0 2 , and was 60/60/60 nm thick with ONO used for the second test capacitor. These thicknesses resulted in the same capacitance per unit area for both device types and resulted in the same oxide field for a given applied voltage.
  • Electrodes 22 and 23 were deposited covering a device area of 0.012 cm 2 and were composed in one instance of sputtered Al and in another instance of sputtered Cr.
  • Aluminum contacts 24 and 25 were deposited on the electrodes 22 and 23, respectively, and the completed capacitors received an anneal (not shown) in the usual manner. Where the electrodes 22 and 23 are fabricated as Al, then the additional contact deposition 24 and 25 may be omitted and the electrode 23 deposited to a greater thickness.
  • the average ramp rate during break down testing was lV/s.
  • films were deposited for ellipsometry, stress and FT-IR measurements. These films were deposited on Si wafers which were polished on both sides. All samples received
  • SUBSTITUTE SHEET a 45 minute anneal in N 2 ambient 400°C.
  • the stress was determined by measuring the change of wafer curvature resulting from the film deposition and anneal. Infrared absorption spectra were obtained using a NicoletteTM 5 DXC spectrometer with a resolution of 16 cm "1 . An Si wafer identical to the sample substrates was used as a reference.
  • Table I summarizes the results of the ellipsometry and stress measurements for the deposited films.
  • the index of refraction (at 633 nm) of the Si0 2 was higher than that of thermally grown oxide, suggesting that the films were oxygen deficient or had some nitrogen content.
  • the film grown was in fact a form of siliconoxynitride (SiO x N ⁇ ) , although much closer to silicon dioxide than to silicon nitride. It has been found that by varying the values of X and Y a continuous variation is possible between silicon oxide and silicon nitride.
  • the dielectric breakdown events for capacitors with Cr electrodes were qualitatively different from those with Al electrodes in a number of respects. First of all, most of the breakdown events with the Cr electrodes were not self-healing. This resulted in a requirement to test more devices in order to record the same number of breakdown events. Also, it was discovered that if a series resistor was not used in the driving circuit, the damaged region would propagate from the initial breakdown point. In some cases, the damage would consume the entire the area of the capacitor. A chemical reaction between the chromium, silicon dioxide and ambient air was likely responsible for this effect. Finally, a much larger proportion of the breakdown events were initiated where the top metal crossed over the bottom metal edge.
  • Figure 4 shows the breakdown field distributions for the capacitors with chromium electrodes. The breakdown events were more broadly distributed, which is consistent with defect-related breakdown. However, the dielectric strength was again improved with the ONO film, with the mean breakdown field being 4.35 MV/cm for Si0 2 and 8.7 MV/cm for ONO.
  • Figure 5 shows the drain current as a function of gate voltage for a CdSe TFT with single layer Si0 2 gate insulation compared to the ONO gate insulation 15 of the TFT transistor according to the present invention ( Figure 1) .
  • Both insulation types exhibited the same capacitance per unit area, with an equivalent oxide thickness of 150 nanometres.
  • the transistors were 25 ⁇ m long and 36 ⁇ m wide. Good switching characteristics were obtained for both device types. However, the ONO curve rises a little more quickly in the subthreshold region and is characterized by a slightly higher ON current.
  • Figure 6 shows the drain current characteristics of the CdSe TFT structure of Figure l , at high drain voltage.
  • the device was 60 ⁇ m long, 36 ⁇ m wide and had ONO gate insulation 15 with layer thicknesses 200/100/200 nm.
  • the device had good transistor characteristics up to a drain voltage of 200 volts, which was the maximum limit of the test apparatus.
  • charge trapping in the nitride layer can produce a reversible threshold voltage shift [S.K. Lee, J.H. Chen, Y.H. Ku, D.L. Kwong, B.Y. Nguyen and K.W. Tseng, Solid State Electron 3JL, 1501 (1988)].
  • This effect is greatly reduced by providing a thick ONO film in accordance with the invention, whereby the tunneling current is greatly reduced.
  • Further testing has been undertaken to compare the properties of thin film transistor with Si0 2 and ONO gate and to determine whether the D.C. drift was degraded by the presence of the nitride layer. For the thickness range considered, the nitride layer was found to have no effect on the D.C. drift, and the subthreshold swing was improved with the ONO films.
  • Figure 7 shows the drain current as a function of gate voltage for two further CdSe thin film transistors under test, one with 440 nm thick Si0 2 gate insulation, and the other with 180/130/180 nm think ONO gate insulation.
  • the capacitance per unit area was
  • SUBSTITUTE SHEE approximately the same (within 10%) for both insulator types.
  • the devices were fabricated as described in detail above, and had dimensions 40 x 36 ⁇ m (lxw) .
  • the drain current of the ONO device rose more quickly in the subthreshold region and reached a higher ON current.
  • the subthreshold swing near I D 1 nA averaged 1.31 V/decade for Si0 2 devices and 0.83 V/decade for ONO devices.
  • Figure 8 shows the normalized drain current as a function of time after switching from the OFF to ON state.
  • the initial current exceeded 100 ⁇ A for both device types (slightly more for ONO) .
  • the curves were quite similar for both device types, indicating that the nitride layer in the ONO films does not degrade the drift.
  • the integrity of the gate dielectric is an important consideration for the display media such as electroluminescent films and NCAP (nematic curvilinear aligned phase) materials, which require high operating voltage.
  • the present invention provides for high dielectric strength ONO films being substituted for single layer Si0 2 without degrading the transconductance or drift of CdSe thin film transistors.
  • the subthreshold swing is in fact improved with the ONO films of the present invention.
  • ONO gate dielectrics as deposited by PECVD have been found to exhibit lower stress and greater dielectric strength than single layer Si0 2 . These improvements were obtained without sacrificing the transconductance of the switching device.
  • the ONO films permit higher voltage operation and provide greater versatility in the choice of display media than is possible with single layer Si0 2 gate insulation.
  • the TFT with triple-layer dielectric of the present invention may be used in various types of display media other than AMLCDs, such as
  • TFT of the present invention may be of any suitable structure (eg. non inverted design, or provided with bottom contacts) . All such variations and modifications are believed to be within the sphere and scope of the claims appended hereto.

Abstract

Affichage à matrice active possédant une pluralité de transistors à couches minces servant à valider et invalider sélectivement les pixels de l'affichage. L'amélioration vient du fait que chacun desdits transistors à couches minces possèdant un diélectrique à trois couches est doté d'un isolant de grille.
PCT/CA1992/000519 1992-12-01 1992-12-01 Transistor a couches minces possedant un dielectrique de grille a trois couches, son procede de fabrication, et affichage a matrice active muni d'une pluralite de transistors de ce type WO1994013018A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP92923642A EP0672301A1 (fr) 1992-12-01 1992-12-01 Transistor a couches minces possedant un dielectrique de grille a trois couches, son procede de fabrication, et affichage a matrice active muni d'une pluralite de transistors de ce type
CA002150573A CA2150573A1 (fr) 1992-12-01 1992-12-01 Transistor en couches minces a isolateur de gachette dielectrique a trois couches, methode de fabrication de ce transistor et afficheur a matrice active comportant une multiplicite de ces transistors
PCT/CA1992/000519 WO1994013018A1 (fr) 1992-12-01 1992-12-01 Transistor a couches minces possedant un dielectrique de grille a trois couches, son procede de fabrication, et affichage a matrice active muni d'une pluralite de transistors de ce type
JP6512598A JPH08503815A (ja) 1992-12-01 1992-12-01 三層誘電体のゲート絶縁体を有する薄膜トランジスタ、このような薄膜トランジスタの製造方法、及び複数のこのような薄膜トランジスタを有するアクティブなマトリクスディスプレイ

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA002150573A CA2150573A1 (fr) 1992-12-01 1992-12-01 Transistor en couches minces a isolateur de gachette dielectrique a trois couches, methode de fabrication de ce transistor et afficheur a matrice active comportant une multiplicite de ces transistors
PCT/CA1992/000519 WO1994013018A1 (fr) 1992-12-01 1992-12-01 Transistor a couches minces possedant un dielectrique de grille a trois couches, son procede de fabrication, et affichage a matrice active muni d'une pluralite de transistors de ce type

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Publication Number Publication Date
WO1994013018A1 true WO1994013018A1 (fr) 1994-06-09

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WO (1) WO1994013018A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8835909B2 (en) 2008-08-04 2014-09-16 The Trustees Of Princeton University Hybrid dielectric material for thin film transistors
CN106292151A (zh) * 2015-06-10 2017-01-04 钱鸿斌 采用有机反射镜管的微型投影装置
CN110797413A (zh) * 2019-11-11 2020-02-14 云谷（固安）科技有限公司 薄膜晶体管、像素驱动电路和显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3671820A (en) * 1970-04-27 1972-06-20 Rudolph R Haering High voltage thin-film transistor
US4905066A (en) * 1988-05-19 1990-02-27 Kabushiki Kaisha Toshiba Thin-film transistor
US5054887A (en) * 1988-08-10 1991-10-08 Sharp Kabushiki Kaisha Active matrix type liquid crystal display
US5068699A (en) * 1989-12-12 1991-11-26 Samsung Electronics Co., Ltd. Thin film transistor for a plate display

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3671820A (en) * 1970-04-27 1972-06-20 Rudolph R Haering High voltage thin-film transistor
US4905066A (en) * 1988-05-19 1990-02-27 Kabushiki Kaisha Toshiba Thin-film transistor
US5054887A (en) * 1988-08-10 1991-10-08 Sharp Kabushiki Kaisha Active matrix type liquid crystal display
US5068699A (en) * 1989-12-12 1991-11-26 Samsung Electronics Co., Ltd. Thin film transistor for a plate display

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8835909B2 (en) 2008-08-04 2014-09-16 The Trustees Of Princeton University Hybrid dielectric material for thin film transistors
CN106292151A (zh) * 2015-06-10 2017-01-04 钱鸿斌 采用有机反射镜管的微型投影装置
CN106292151B (zh) * 2015-06-10 2017-12-26 钱鸿斌 采用有机反射镜管的微型投影装置
CN110797413A (zh) * 2019-11-11 2020-02-14 云谷（固安）科技有限公司 薄膜晶体管、像素驱动电路和显示面板

Also Published As

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