EP0672302A1 - Structure amelioree pour transistor a couches minces au seleniure de cadmium - Google Patents

Structure amelioree pour transistor a couches minces au seleniure de cadmium

Info

Publication number
EP0672302A1
EP0672302A1 EP92923643A EP92923643A EP0672302A1 EP 0672302 A1 EP0672302 A1 EP 0672302A1 EP 92923643 A EP92923643 A EP 92923643A EP 92923643 A EP92923643 A EP 92923643A EP 0672302 A1 EP0672302 A1 EP 0672302A1
Authority
EP
European Patent Office
Prior art keywords
layer
thin film
deposited
semiconductor channel
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP92923643A
Other languages
German (de)
English (en)
Inventor
James F. Farrell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
L3 Technologies ESS Inc
Original Assignee
Litton Systems Canada Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Litton Systems Canada Ltd filed Critical Litton Systems Canada Ltd
Priority claimed from PCT/CA1992/000520 external-priority patent/WO1994013019A1/fr
Publication of EP0672302A1 publication Critical patent/EP0672302A1/fr
Withdrawn legal-status Critical Current

Links

Definitions

  • This invention relates in general to thin film transistors (TFTs) , and more particularly to an improved structure for CdSe thin film transistors for use in an active matrix liquid crystal display.
  • Thin film transistor-based active matrix liquid crystal displays are now in production at a number of large electronics companies. These displays, used for personal television and lap-top computer screens, use amorphous silicon as the semiconductor.
  • AMLCD acts as an analog sample and hold circuit, for sampling the video data and holding it until the next data refresh cycle.
  • AMLCD acts as an analog sample and hold circuit, for sampling the video data and holding it until the next data refresh cycle.
  • the ability of an AMLCD to present good video pictures is directly related to the accuracy of the sample and hold circuits at each dot or pixel.
  • the TFT must have sufficiently high on-conductance to fully charge the pixel capacitance during the line address time, while having sufficiently low off- conductance to hold the charge accurately for the refresh period of the display.
  • Amorphous silicon TFTs used in early displays were known for their low leakage current in the "off” state while exhibiting enough "on” current to fully charge the pixel capacitance and activate the liquid crystal.
  • Amorphous silicon is rather a low mobility semiconductor however, so as the number of addressable lines in AMLCD ⁇ has increased, and the line address time has decreased, methods to increase the "on" current of the TFTs have been investigated.
  • amorphous silicon TFTs can be increased by simply increasing the gate voltage swings, increasing the channel width to length ratio, or by using a high dielectric constant gate insulator to decrease the channel capacitance.
  • One prior art TFT design is disclosed in U.K. Patent GB 2087147 (National Research Development Corporation) . As will be discussed in greater detail below, this prior art design suffers from the disadvantage that the thin metal source and drain layers can be contaminated prior to deposition of the semiconductor channel layer. Furthermore, once the semiconductor channel layer is deposited and patterned, it must be crystallized since it is formed of polycrystaline material. During crystallizing, the semiconductor material is subjected to high temperatures so that the source and drain contact material tends to diffuse into the semiconductor channel material and shortens the channel length.
  • an AMLCD design is provided in which the source and drain electrodes are deposited for connection to the semiconductor channel layer as the last step of the fabrication process. This avoids unwanted diffusion of the source and drain metallic contacts into the semiconductor material. Furthermore, according to the invention, the source and drain electrodes may be made of a desired thickness for increased current conduction, and no extra lithography step is required. In addition, the problem of organic contamination from residual lift-off photoresist, which arises in the prior art system disclosed in the UK Patent, does not occur.
  • a thin film transistor comprising: a) a glass substrate; b) a gate electrode deposited on said substrate; c) a gate insulator layer deposited on said
  • SUBSTITUTESHEET substrate so as to overly said gate electrode; d) a thin film semiconductor channel layer deposited on said gate insulator layer and substantially aligned with said gate electrode; e) a passivation layer deposited on said gate insulator layer so as to overly said thin film semiconductor channel layer; and f) a pair of source and drain electrodes deposited on said passivation layer and extending through a portion of said passivation layer for contacting said semiconductor channel layer.
  • a method of fabricating a thin film transistor comprising the steps of: a) providing a substrate; b) depositing a gate electrode on said substrate; c) depositing a gate insulator layer on said substrate so as to overly said gate electrode; d) depositing a thin film semiconductor channel layer on said gate insulator layer so as to be substantially aligned with said gate electrode; e) depositing a passivation layer on said gate insulator layer so as to overly said thin film semiconductor channel layer; f) etching a pair of via holes though said passivation layer to said semiconductor channel layer; and g) depositing a pair of source and drain electrodes on said passivation layer so as to extend through said via holes for contacting said semiconductor channel layer.
  • An active matrix liquid crystal display comprising: a) a first polarizing layer; b) a first glass substrate deposited on said first polarizing layer; c) a plurality of gate electrodes deposited on
  • SUBSTITUTESHEET p) a light shielding/contrast enhancement layer deposited on said second glass substrate; q) a plurality of colour filters spun on to said light shielding/contrast enhancement layer, said plurality of colour filters being thereafter patterned to align with respective ones of said rectangular pixel output pads and then cured; r) a planarization layer deposited on said plurality of colour filters; s) a conductive backplane electrode deposited on said planarization layer; and t) a second alignment layer intermediate said backplane electrode and said layer of liquid crystal material.
  • Figure 1 is a plan view showing a prior art TFT array for AMLCD
  • Figure 2 is a sectional view showing the prior art in Figure l taken along the line II-II thereof;
  • FIG. 3 is a simplified schematic diagram of the sample and hold structure of the TFT shown in Figures l and 2;
  • Figures 4a, 4b and 4c show successive steps in the fabrication process of a TFT according to the preferred embodiment of the present invention
  • Figure 5 is a graph showing current-voltage characteristics of the TFT according to the preferred embodiment of the present invention.
  • FIG. 6 is a cross sectional view of an AMLCD incorporating the TFTs of the present invention. Detailed Description of the
  • Figures 1 and 2 show structures of an inverted TFT ( Figure 2) and a TFT array ( Figure 1) obtained by arranging a plurality of such inverted TFTs on an insulating substrate.
  • the plurality of TFTs 1 are arranged on a transparent insulating substrate 2, such as glass, in the form of a matrix.
  • Gate electrodes 3 of each TFT 1 are commonly connected though gate line 4 so as to form select lines of the array.
  • Source electrodes 5 of each TFT 1 are commonly connected to source lines 6 to form data lines of the array.
  • Drain electrode 7 of each TFT 1 is connected to a transparent electrode 8 which is formed as a rectangular pixel output pad between the gate lines 4 and source lines 6 of the array.
  • the profile of a TFT 1 is shown comprising a series of overlapping layers.
  • the metallic gate electrode 3 is deposited on transparent glass substrate 2.
  • a gate insulator layer 9 is then deposited on the glass substrate 2 so as to overly the gate electrode 3.
  • the gate insulating layer 9 may consist of silicon oxide or silicon nitride, or other suitable insulating material.
  • the source and drain electrodes 5 and 7 are deposited on the gate insulating layer 9, and a layer of semiconductor material 10 is then deposited so as to overlap the source and drain electrodes 5 and 7, forming a thin-film semiconductor channel therebetween.
  • the prior art pixel cell design shown in Figure 3 corresponds to the structure of Figure 1, and includes a storage capacitor 12 which is formed by the overlap of the output pad 8 with a previously scanned gate. Finally, a passivation layer 11 is deposited over the entire structure.
  • the semiconductor layer 10 In order to cause the semiconductor layer 10 to overlap the source and drain electrodes, the semiconductor layer must be thicker than the thickness of the metallic source and drain electrodes 5 and 7. In order to avoid the deposition of an excessively thick semiconductor layer which would be inappropriate for thin
  • the TFT design of the present invention avoids the extra metal lithography step required during fabrication of the illustrated prior art TFT.
  • the TFT design of the present invention also minimizes any contamination of the source and drain contacts, thereby alleviating the necessity to conduct ion beam etching or sputter etching for cleaning the contacts.
  • the TFT design according to the present invention avoids unwanted diffusion of the metallic source and drain contact material into the semiconductor.
  • SUBSTITUTESHEET a layer of chromium (Cr) is deposited on a Corning 7059 glass substrate 13, and patterned to form gate electrode 14.
  • a 5000 ⁇ film of PECVD SiO x serving as the gate insulator 15, is then deposited, followed by a 500 A layer of the evaporated CdSe semiconductor.
  • the semiconductor layer 16 is patterned and then passivated with a SiO x layer 17.
  • ITO indium tin oxide
  • the final two steps in the process of the present invention are to open up contact vias 19a and 20a in the passivation oxide, deposit the source/drain metal, and pattern the metal to form the source and drain electrodes 19 and 20.
  • the contact vias are formed by a dry etch process using reactive gases. Since conductivity properties of the semiconductor are disturbed when the semiconductor is uncovered as a result of the reactive ion etch, a sputter etch is performed, according to the present invention, to etch away contaminated areas. A final anneal is then performed to ensure good ohmic contact between the semiconductor 16 and the source and drain electrodes 19 and 20.
  • the source and drain electrodes 19 and 20 are contacted to the semiconductor layer 16 as the last step of the process according to the present invention, unwanted diffusion of the source and drain metal into the semiconductor layer is eliminated.
  • the source and drain electrodes 19 and 20 can easily be made as thick as required for achieving proper current carrying capabilities, since the prior art problem of step coverage of the semiconductor over the source and drain electrodes does not arise in the TFT design according to the present invention. Furthermore, the problem of organic contamination of the source and drain contacts which results from residual lift-off photoresist in the fabrication process according to the prior art, does not occur in the process according to the present invention
  • Typical I-V characteristics for the TFT of the present invention are shown in Figure 5.
  • the highest temperature used in the process according to the present invention is 400°C. , allowing for the use of readily available low cost substrates.
  • Proximity printing is effected using lithographic exposure to pattern each layer, resulting in the creation of features with as little as 12 micron resolution.
  • the active matrix LCD comprises a plurality of TFT devices as shown in Figure 4c arranged on a polarizer 21.
  • Liquid crystal material 23 i.e. nematic liquid
  • alignment layers 22 and 24 are confined between alignment layers 22 and 24.
  • a glass substrate 31 and top polarizer 32 are provided, onto which a black chromium (CrO x ) grid 27 is deposited and patterned to form a light shielding/contrast enhancement layer.
  • the first colour filter e.g. red filter 28
  • the next two colours e.g. green filter 29 and blue filter 30
  • the colour filters 28-30 are fabricated using dyed polyimide material.
  • the filter is planarized with clear polyimide to form planarization layer 26 and then deposited with ITO layer 25 which forms the back plane electrode.
  • the colour AMLCD of Figure 6, using CdSe TFTs according to the present invention has applications in military land vehicles and avionics. However, it is contemplated that commercial applications of the invention are, in fact, extremely broad, including displays for lap top and desk top computers, and other applications in which an active matrix display may be used to replace a CRT.
  • the drive electronics not shown
  • EE used to control the display can be identical to those used in prior art amorphous silicon AMLCDs.
  • the TFT fabrication process according to the present invention utilizes equipment and methods common to the amorphous silicon process, the main exceptions being that CdSe is evaporated instead of plasma deposited as in the prior art amorphous silicon technology, and that proximity printing is used due to the larger features possible with the CdSe design. It is believed that this compatibility with existing amorphous silicon fabrication techniques and driver chip technology, coupled with the increasingly apparent limitations of prior art amorphous silicon TFTs, will speed the development of new applications for CdSe based AMLCDs such as discussed herein throughout avionics and other industries requiring thin film AMLCDs.

Landscapes

  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

Transistor à couches minces comportant un substrat en verre; une électrode de grille déposée sur le substrat; une couche d'isolant de grille déposée sur le substrat et par-dessus l'électrode de grille; une couche canal semi-conductrice en couche mince déposée sur la couche d'isolant de grille et sensiblement alignée sur l'électrode de grille; une couche de passivation déposée sur la couche d'isolant de grille et par-dessus la couche canal semi-conductrice en couche mince; une paire de trous traversants formés par gravure dans la couche de passivation et s'étendant jusqu'à la couche canal semi-conductrice; et une paire d'électrodes source et drain déposées sur la couche de passivation et s'étendant dans les trous traversants de manière qu'elles soient au contact de la couche canal semi-conductrice.
EP92923643A 1992-12-01 1992-12-01 Structure amelioree pour transistor a couches minces au seleniure de cadmium Withdrawn EP0672302A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/CA1992/000520 WO1994013019A1 (fr) 1992-12-01 1992-12-01 Structure amelioree pour transistor a couches minces au seleniure de cadmium
CA002150679A CA2150679C (fr) 1992-12-01 1992-12-01 Structure amelioree d'element thermoelectrique a couche mince cdse

Publications (1)

Publication Number Publication Date
EP0672302A1 true EP0672302A1 (fr) 1995-09-20

Family

ID=4155964

Family Applications (1)

Application Number Title Priority Date Filing Date
EP92923643A Withdrawn EP0672302A1 (fr) 1992-12-01 1992-12-01 Structure amelioree pour transistor a couches minces au seleniure de cadmium

Country Status (2)

Country Link
EP (1) EP0672302A1 (fr)
JP (1) JPH08511130A (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI656022B (zh) 2013-11-13 2019-04-11 美商康寧公司 疊層玻璃物件及其製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9413019A1 *

Also Published As

Publication number Publication date
JPH08511130A (ja) 1996-11-19

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