Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/0203—Particular design considerations for integrated circuits
  • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B10/00—Static random access memory [SRAM] devices
  • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

Definitions

• the present invention relates to a substrate structure of a semiconductor device, and more particularly to a structure of a substrate portion on which an input circuit is formed in a semiconductor memory device.
• the semiconductor storage device is provided with input circuits such as an address buffer circuit and a data-in buffer circuit.
• An address pin is used for the input node of the address buffer circuit, and a data pin is connected to the input node of the data buffer circuit to input an address and data.
• These input circuits compare the external input voltage (hereinafter abbreviated as Vin), which is TTL level data, with a reference potential (hereinafter abbreviated as V rei) to compare the data “H igh” and “L”. ow “,” 1 ", and” 0 "are detected, and the detected signal is amplified and converted to an M0S level signal used inside the storage device.
• Vin external input voltage
• V rei reference potential
• FIG. 1 is an equivalent circuit diagram of the address buffer circuit.
• This address buffer circuit includes p-channel type MOS transistors Ql, Q2, n-channel type MOS transistors Q3 to Q10, and MOS capacitors C1, C2. It is configured.
• This circuit uses a control signal (DRAM The operation is controlled by the internal control signals 01, ⁇ 2, and ⁇ 3 generated based on the RAS, CAS, etc.), and the input address is responded to by the timing of these internal control signals. Latch. Then, "High” or “Low” of the two Vins is detected depending on whether or not the potential is higher than Vii ⁇ Vrei, and is output as address signals AQ and Aout.
• V rei is a potential that is a reference for the circuit operation of the semiconductor memory device and is generated inside the memory device.
• V ref is normally a positive potential, but preventing fluctuations in this potential is particularly important for circuit operation.
• a test is performed to test the operating characteristics of the semiconductor memory device by applying a negative potential (for example, up to about ⁇ 2.0 V) to Vin.
• a negative potential for example, up to about ⁇ 2.0 V
• FIG. 2 is a diagram showing a semiconductor in which the n-channel type MOS transistor Q3 to Q10 and the M0S capacitors C1 and C2 in the address buffer circuit shown in FIG. 1 are formed.
• FIG. 3 is a cross-sectional view illustrating a structure of a substrate.
• a p-well region 26 is formed in the main surface region of n-type semiconductor substrate 21. This! In the surface region of the cell region 26, n + -type impurity diffusion layers 22 and 23 and ap + -type impurity diffusion layer 28 are formed separately.
• the impurity diffusion layer 22 functions as a drain region of the MOS transistor Q9, and Vin is applied to the diffusion layer 22 via the wiring 24. Above impure
• the material diffusion layer 23 functions as a drain region of the M0S transistor Q10, and Vref is applied to the diffusion layer 23 via the wiring 25.
• a ground potential (hereinafter abbreviated as V ss) is applied to the impurity diffusion layer 28 via a wiring 27. As a result, the ground potential is applied to p-type region 26.
• the source region of the n-channel MOS transistors Q9 and Q10 and the sources and drains of the n-channel MOS transistors Q3 to Q8 are included in the p-channel region 26. Region, and M0S capacitors C], C2, etc.
• the channel type MOS transistors Q 1 and Q 2 are formed in the main surface area of the substrate 21.
• the present invention is to provide a substrate structure of a semiconductor device which can eliminate the above-mentioned disadvantages of the prior art and can improve reliability. It is intended for. Disclosure of the invention
• a substrate structure of a first semiconductor device includes a semiconductor substrate of a first conductivity type and a second conductivity type cell region formed in the semiconductor substrate and applied with a potential lower than an external input potential.
• a first impurity diffusion layer of a first conductivity type formed in the well region and to which the external input potential is applied; and a first conductive layer formed in the well region and to which a reference potential is applied.
• the first impurity diffusion layer and the second impurity diffusion layer are formed in the cell region, and the cell region has a potential lower than Vin (that is, its absolute value is larger than Vin). Is applied. Therefore, the minority carrier generated when a negative potential is applied as Vin does not move to the cell region having a high energy potential, and therefore does not move into the second impurity diffusion layer. It does not change V re ⁇ .
• a substrate structure of a second semiconductor device includes a first conductive type semiconductor substrate, a second conductive type first cell region formed in the semiconductor substrate, and to which a first potential is applied.
• a first conductivity type first impurity diffusion layer formed in the first plug region and to which an external input potential is applied; and a second impurity diffusion layer formed in the semiconductor substrate and to which a second potential is applied.
• a reference potential is formed in the second conductive region and the second conductive region.
• a third well region having a lower potential energy than the first and second well regions is provided between the first well region and the second well region. Therefore, the minority carriers generated from the first shell region are absorbed by the third shell region and do not reach the second shell region. Therefore, the minority carrier cannot reach the second impurity diffusion layer formed in the second rule region, and Vref does not fluctuate.
• the substrate structure of the third semiconductor device includes a semiconductor substrate of the first conductivity type, a first well region of the second conductivity type formed in the semiconductor substrate and to which a ground potential is applied.
• a third conductive-type third conductive region formed in the semiconductor substrate between the active region and the semiconductor substrate, to which a power supply potential is applied.
• This substrate structure has a ground potential as the first potential and the second potential in the above-described substrate structure of the second semiconductor device according to the present invention.
• a power supply potential is applied to the third module region. That is, since the power supply potential is higher than the ground potential (potential energy is low), the minority carrier generated in the first module region is absorbed by the third cell region, and reaches the second cell region. I will not do it.
• the power supply potential here is usually a positive potential, and includes a potential obtained by stepping down a power supply voltage in a semiconductor device having a power supply voltage step-down circuit.
• FIG. 1 is an equivalent circuit diagram of an address buffer circuit
• FIG. 2 is a sectional view showing a substrate structure of a conventional semiconductor device
• FIG. 3 is a diagram showing potential energy in the substrate structure shown in FIG.
• FIG. 4 is a sectional view showing the substrate structure of the semiconductor device according to the first embodiment of the present invention
• FIG. 5 is a diagram showing the potential energy of the substrate structure shown in FIG. 4
• FIG. 7 is a cross-sectional view showing the substrate structure of the semiconductor device according to the second embodiment
• FIG. 7 is a diagram showing the potential energy of the substrate structure shown in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
• FIG. BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail with reference to the accompanying drawings.
• FIG. 4 is a sectional view showing a substrate structure of the semiconductor device according to the first embodiment of the present invention.
• input circuits such as the address buffer circuit and the data buffer circuit shown in FIG. 1 are formed.
• the above The case where the address buffer circuit shown in the figure is formed will be described as an example.
• a p-type region 16 is formed in the main surface region of n-type semiconductor substrate 11.
• n + -type impurity diffusion layers 12 and 13 s and p + -type impurity diffusion layer 18 are formed separately.
• the impurity diffusion layer 12 serves as a drain region of the MOS transistor Q 9 in the circuit shown in FIG. 1, and Vin is connected to the diffusion layer 12 via the wiring 14.
• the impurity diffusion layer 13 serves as a drain region of the MOS transistor Q10 in the circuit shown in FIG. 1, and V ref is applied to this diffusion layer 13 via the wiring 15.
• the substrate potential (hereinafter abbreviated as v BB ) of the semiconductor substrate 11 is applied to the impurity diffusion layer 18 via the wiring 17. As a result, V Bn force is applied to the p-well region 16.
• the potential applied to the ⁇ ⁇ region 16 is changed from the conventional V ss (ground potential) to ⁇ ⁇ (for example, ⁇ 3.0 Therefore, as long as V is a negative potential and does not fall below V ⁇ (that is, unless IV i ⁇ I> IVI), the generated minority carrier remains in the diffusion layer 13. Since it does not move, the potential of V re ⁇ does not decrease due to a small number of carriers.
• FIG. 6 is a sectional view showing a substrate structure of a semiconductor device according to a second embodiment of the present invention.
• input circuits such as the address buffer circuit and the data buffer circuit shown in FIG. 1 are formed.
• the above The case where the address buffer circuit shown in FIG. 1 is formed will be described as an example, similarly to the embodiment.
• a first p-type region 4 and a second p-type region 9 are formed apart from each other. Further, an n-pole region 14 is formed in the substrate 1 between the first and second p-well regions 4 and 9.
• a P + -type impurity diffusion layer 3 and an n + -type impurity diffusion layer 6 are formed apart from each other in the surface region of the cell region 4.
• V ss is applied to the well region 4.
• the impurity diffusion layer 6 is shown in FIG.
• V iu (external input potential) is applied to the diffusion layer 6 via the wiring 5 to serve as a drain region of the MOS transistor Q 9 in the circuit.
• a P + -type impurity diffusion layer 8 and an n + -type impurity diffusion layer 20 are formed apart from each other in the surface region of the cell region 9.
• V ss is applied to the impurity diffusion layer 8 via the wiring 7
• V ss is applied to the well region 9.
• the impurity diffusion layer 20 functions as a drain region of the M 0 S transistor Q 10 in the circuit shown in FIG. 1, and the diffusion layer 20 is connected to the diffusion layer 20 through the wiring 10.
• V re ⁇ is applied.
• An ⁇ + -type impurity diffusion layer 13 is formed in the surface region of the above-mentioned cell region 14, and a power supply potential (V cc> 0) is applied to this diffusion layer 13 via the wiring 12. Is done.
• the source region of the n-channel MOS transistor Q 9 is in the first p-type region 4, and the n-channel type MOS transistor is in the second p-type region 9.
• Source regions of the transistors Q10 are formed.
• the source, drain region, MOS capacity C 1, C 2, etc. of the n-channel type MOS transistor Q 3 to Q 8 may be formed in the well region 9 or the first and second regions.
• a third p-type region may be formed separately from the second p-type regions 4 and 9, and may be formed in the third p-type region.
• the source and drain regions of the M 0 S transistors Q 3, Q 5, Q 7, and Q 9 and the M 0 S capacitor C 1 are placed in the first well region 4 so that the M 0 S transistors Q 4, Q 6, Q8, Q10 source and drain regions and the MS capacitor C2 can also be formed in the second module region 9. What is important is that the source and drain regions of the M0S transistor Q9 surrounded by a broken line are formed in the first 1) module region 4), and the sources and drains of the M0S transistor Q10 surrounded by a broken line. In the second p-well region 9.
• the p-channel type MOS transistors Q 1 and Q 2 are formed in the main surface region of the substrate 1.
• the first p-well region 4, the second p-well region 9, and the n-well region 14 are in contact with each other, but are not limited thereto. The same effect can be obtained even if there is a certain interval. Also, the first p-cell region 4 and the second p-cell region 9 have i 1
• V ss is applied, the same effect can be obtained by applying the substrate potential of the semiconductor substrate 1 (for example, about ⁇ 3.0 V).
• the semiconductor device according to the present invention has a substrate structure in which a minority carrier generated when a negative potential is applied as an external input potential fluctuates the reference potential. Malfunction can be effectively prevented. Therefore, it is effective for improving the reliability of the semiconductor device.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Semiconductor Memories (AREA)
• Semiconductor Integrated Circuits (AREA)
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• 1991
  • 1991-04-12 DE DE69131441T patent/DE69131441T2/de not_active Expired - Lifetime
  • 1991-04-12 KR KR1019910005830A patent/KR940005725B1/ko not_active IP Right Cessation
  • 1991-04-12 WO PCT/JP1991/000482 patent/WO1991016728A1/ja active IP Right Grant
  • 1991-04-12 EP EP91906985A patent/EP0478793B1/en not_active Expired - Lifetime
• 1994
  • 1994-01-10 US US08/180,770 patent/US6104233A/en not_active Expired - Lifetime

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