USRE49285E1 - Semiconductor device structure and methods of its production - Google Patents

Semiconductor device structure and methods of its production Download PDF

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USRE49285E1
USRE49285E1 US17/135,821 US201517135821A USRE49285E US RE49285 E1 USRE49285 E1 US RE49285E1 US 201517135821 A US201517135821 A US 201517135821A US RE49285 E USRE49285 E US RE49285E
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nucleation layer
semiconductor device
mbar
device structure
layer
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Erik Janzén
Jr-Tai Chen
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Swegan AB
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present disclosure relates to a semiconductor device structure for semiconductor devices and to methods for producing the same.
  • HEMTs high electron mobility transistors
  • High thermal conductivity substrates typically silicon carbide (SiC) are used in such devices in order to efficiently extract the heat and to minimize temperature rise of the device.
  • SiC silicon carbide
  • AlN aluminum nitride
  • TBR thermal boundary resistance
  • An object of the present disclosure is to provide an improved semiconductor structure, and in particular, a semiconductor structure that is improved in terms of one or more of the above mentioned properties.
  • the buffer layer presents a rocking curve with a (102) peak having a FWHM below 250 arcsec
  • the nucleation layer presents a rocking curve with a (105) peak having a FWHM below 200 arcsec, as determined by X-ray Diffraction (XRD).
  • a semiconductor device structure may be defined as stack of material layers which may be used for making a semiconductor device, or which may form part of a semiconductor device.
  • An example of such a semiconductor device may be a high electron mobility transistor (HEMT).
  • HEMT high electron mobility transistor
  • the buffer layer is herein defined as the layer placed on top of, and preferably in direct contact with, the nucleation layer.
  • the nucleation layer may be defined as a layer for wetting the substrate surface and accommodating the lattice mismatch between a substrate and the buffer layer, enabling high quality buffer layer growth.
  • a rocking curve may be defined as a plot of the X-ray diffracted intensity versus the angle of the sample independently rotated (or “rocked”) around the expected Bragg reflection.
  • a lower limit of the (102) peak FWHM of the buffer layer may be 100, 150 or 200 arcsec.
  • the upper limit may be 200 or 250.
  • a lower limit of the (105) peak FWHM of the nucleation layer may be 50, 100 or 150.
  • the upper limit may be 175 or 200.
  • x1 and x2 values may be the same or different.
  • y1 and y2 values may be the same or different.
  • y2 >y1.
  • the above semiconductor device structure provides enhanced crystallinity of the buffer layer and the nucleation layer as compared to what has been shown by prior art. Moreover, leakage currents may be reduced due to better crystalline quality in terms of a reduced threading dislocation density. Further, the semiconductor device structure may present a reduced thermal boundary resistance as compared with prior art semiconductor device structures.
  • the buffer layer may be GaN. Further examples of buffer layers are discussed in the detailed description.
  • the nucleation layer may be AlN. Further examples of nucleation layers are discussed in the detailed description.
  • the SiC polytype may be e.g. 4H, 6H, or 3C.
  • SiC polytype is meant the different structures SiC may exist in.
  • the surface of the SiC may have less than 5% oxygen monolayer, as determined by X-ray Photoelectron Spectroscopy.
  • monolayer By monolayer is meant a full surface coverage by an unit-cell-height material. Hence, “less than 5% oxygen monolayer” means that the surface coverage is not complete, and hence that less than 5% of the surface area is covered by oxygen.
  • the buffer layer may have a thickness of 1 to 4 ⁇ m, preferably 1.3 to 3 ⁇ m and most preferably 1.5 to 2 ⁇ m.
  • the nucleation layer may have a thickness of 10-100 nm, preferably 10-50 nm and most preferably 10-40 nm.
  • the morphology of the nucleation layer with thickness less than 100 nm may have 0 to 10 pits per ⁇ m 2 , preferably 0 to 8 pits per ⁇ m 2 , most preferably 0 to 5 pits per ⁇ m 2 , due to an enhanced coalescence process
  • coalescence is meant the process by which two or more particles/islands merge during contact to form a single bigger particle/island or film.
  • Plate per ⁇ m 2 may be defined as the number of holes or recesses per ⁇ m 2 .
  • HEMT high electron mobility transistor
  • a semiconductor device formed from the semiconductor device structure.
  • the temperature upon growth of the nucleation layer is ramped up by 5-25° C./min, preferably by 7-20° C./min and most preferably by 10-15° C./min, for a time period of 2 min to 20 min.
  • the temperature may be measured from a hole located at the upstream side, the upper part (ceiling) of the susceptor by a pyrometer.
  • the determination of the temperature value might be different depending on the techniques used and the location of the measurement.
  • Ring up is defined as an increase of the temperature. Such increase may e.g. be stepwise or continuous, linear, progressive or degressive.
  • the buffer layer presents a rocking curve with a (102) peak having a FWHM below 250 arcsec
  • the nucleation layer presents a rocking curve with a (105) peak having a FWHM below 200 arcsec, as determined by X-ray Diffraction (XRD).
  • the substrate may be pretreated in situ or ex situ by an etching gas, such as H 2 , HCl, HF, HBr or SiF 4 , Cl 2 , or a combination of these, such as H 2 and any one of the other.
  • an etching gas such as H 2 , HCl, HF, HBr or SiF 4 , Cl 2 , or a combination of these, such as H 2 and any one of the other.
  • the amount of e.g. oxygen and carbon contamination onto the substrate surface may be reduced.
  • the pressure may be 100 mbar to 10 mbar, preferably 60 mbar to 10 mbar, and most preferably 30 mbar to 10 mbar upon pretreatment at a temperature of at least 1250° C.
  • the pressure may be 1000 mbar to 10 mbar, preferably 500 mbar to 10 mbar, most preferably 200 mbar to 10 mbar upon pretreatment at a temperature of at least 1400° C.
  • the etching gas preferably H 2
  • HCl may be provided at a flow rate of 100 to 200 ml/min.
  • At least one of the nucleation layer and the buffer layer may be grown by Metal Organic Chemical Vapor Deposition (MOCVD) or Metal Organic Vapor Phase Epitaxy (MOVPE), Hydride Vapor Phase Epitaxy (HVPE), or Molecular Beam Epitaxy (MBE).
  • MOCVD Metal Organic Chemical Vapor Deposition
  • MOVPE Metal Organic Vapor Phase Epitaxy
  • HVPE Hydride Vapor Phase Epitaxy
  • MBE Molecular Beam Epitaxy
  • At least one of the precursors for nucleation growth by MOCVD or MOVPE may be metal-organic, such as Al 2 (CH 3 ) 6 , and the other one may be NH 3 .
  • a precursor may be defined as a source material and may be allowed to react with at least another precursor.
  • the precursors may be provided by at least one carrier gas, such as H 2 , Ar or N 2 or a combination thereof.
  • a carrier gas may be used for transporting the at least one precursor, e.g. to a reactor.
  • the pressure upon growth of the nucleation layer may be 200 mbar to 10 mbar, preferably 100 mbar to 20 mbar, most preferably 60 mbar to 40 mbar for MOCVD or MOVPE.
  • the starting temperature upon growth of the nucleation layer may be 800° C. to 1150° C., preferably 900° C.-1100° C., most preferably 950° C.-1050° C. for MOCVD or MOVPE.
  • the growth rate of the nucleation layer may be 100 nm/h to 1000 nm/h, preferably 150 nm/h to 600 nm/h, most preferably 200 nm/h to 400 nm/h for MOCVD or MOVPE.
  • the pressure upon growth of the nucleation layer may be 200 mbar to 10 mbar, preferably 100 mbar to 20 mbar, most preferably 60 mbar to 40 mbar, for HVPE.
  • the starting temperature upon growth of the nucleation layer may be 800° C. to 1200° C., preferably 900° C. to 1150° C., most preferably 950° C. to 1100° C. for HVPE.
  • the growth rate of the nucleation layer may be 1 ⁇ m/h to 100 ⁇ m/h, preferably 5 ⁇ m/h to 50 ⁇ m/h, most preferably 10 ⁇ m/h to 20 ⁇ m/h for HVPE.
  • the pressure upon growth of the nucleation layer may be 1 ⁇ 10 ⁇ 3 mbar to 1 ⁇ 10 ⁇ 7 mbar, preferably 5 ⁇ 10 ⁇ 3 mbar to 1 ⁇ 10 ⁇ 6 mbar, most preferably 1 ⁇ 10 ⁇ 4 mbar to 1 ⁇ 10 ⁇ 5 mbar for MBE.
  • the starting temperature upon growth of the nucleation layer may be 500° C. to 1000° C. preferably 550° C. to 900° C., most preferably 600° C. to 800° C. for MBE.
  • the growth rate of the nucleation layer may be 100 nm/h to 1000 nm/h, preferably 200 nm/h to 800 nm/h, most preferably 400 nm/h to 600 nm/h for MBE.
  • FIG. 1 schematically illustrates a semiconductor device structure.
  • FIG. 2 shows XPS spectra of SiC substrates, pretreated by H 2 in a MOCVD reactor at 1200° C. and 1320° C., respectively.
  • FIGS. 3a and 3b show rocking curves of AlN (105) and AlN (002) peaks, respectively, measured by XRD.
  • FIGS. 4a and 4b show rocking curves of GaN (102) and GaN (002) peaks, respectively, measured by XRD.
  • FIGS. 5a and 5b show reciprocal space maps of relaxed AlN and fully strained AlN, respectively, of a high electron mobility transistor (HEMT) device structure, measured by XRD.
  • HEMT high electron mobility transistor
  • FIGS. 6a and 6b show AFM pictures of an AlN surface produced according to prior art and according to the method disclosed herein, respectively.
  • SiC silicon carbide
  • the boundaries may be as set forth above.
  • the nucleation layer and the buffer layer may be made of the same or different materials.
  • the nucleation layer is to compensate for the lattice mismatch between the SiC substrate and the buffer layer, and to obtain high quality epitaxial growth of the buffer layer on SiC.
  • Another purpose of the nucleation layer is to enable growth of e.g. GaN on it. GaN does not nucleate two-dimensionally on some substrates, such as SiC, so there may be a need for an AlN nucleation layer to change the surface potential, such that GaN can be grown.
  • the nucleation layer may be added, directly on the SiC substrate, i.e. no additional layers may be placed between.
  • nucleation layers produced according to prior art methods having a thickness of above 8-12 nm starts to relax due to a lattice mismatch of about 1% between the SiC substrate and the nucleation layer.
  • a fully strained nucleation layer as shown herein may improve the crystalline quality of the buffer layer.
  • the nucleation layer grown by the method disclosed herein may be fully strained at a thickness of up to at least 100 nm. However, once the nucleation layer exceeds this thickness, the nucleation layer will start to relax due to lattice mismatch.
  • the in-plane lattice constant of the nucleation layer is exactly the same, or exactly the same +/ ⁇ 0.15%, preferably +/ ⁇ 0.05% or +/ ⁇ 0.02%, as the in-plane lattice constant of the SiC substrate.
  • its asymmetric X-ray reflex like (105)
  • the purpose of the buffer layer is to develop the structure quality by a thick layer growth and is supposed to be fully relaxed when the desired thickness is reached, in contrast to the nucleation layer which, if grown at a certain thickness by the method disclosed herein, may be fully strained as discussed, above.
  • the nucleation layer 12 may be aluminum nitride (AlN) and the buffer layer 13 may be gallium nitride (GaN). Characterization results of such a SiC/AlN/GaN structure will be discussed in more detail in this disclosure.
  • the SiC substrate is used due to its high thermal conductivity properties in order to efficiently extract generated heat and to minimize temperature rise in a semiconductor device.
  • the polytype of the SiC substrate may be for example 4H, 6H or 3C.
  • the orientation of the SiC substrate may be represented by c-plane, a-plane and m-plane.
  • Si face and C face respectively.
  • the substrate may preferably be an on-axis substrate. However as an alternative a low angle off cut substrate, such as below 2 degrees off, may be used.
  • the SiC substrate is pretreated in order to remove surface contamination that mainly may be composed of oxygen but also of carbon.
  • the pretreatment may be performed in situ, i.e. in the same chamber/reactor as the growth of the nucleation, buffer and optionally additional layers will take place.
  • the pretreatment may be performed ex situ, for example in a furnace.
  • the substrate is moved after pretreatment to the reactor in which the layers are grown.
  • moving the substrate does not give rise to new surface contamination.
  • the SiC substrate Before the in situ pretreatment, the SiC substrate may, but need not, be cleaned and optionally rinsed and further optionally purged.
  • the SiC substrate may be cleaned in acetone, methanol, and a solution of NH 4 OH+H 2 O 2 +H 2 O (1:1:5) at 80° C., and HCl+H 2 O 2 +H 2 O (1:1:5) at 80° C., each solution for 5 min, and finished with deionized water rinsing and N 2 purging and clip in HF solution.
  • gases providing an etching effect on the substrate e.g. H 2 , HCl, or a combination thereof
  • gases providing an etching effect on the substrate e.g. H 2 , HCl, or a combination thereof
  • gases providing an etching effect on the substrate e.g. H 2 , HCl, or a combination thereof
  • HF, HBr or SiF 4 , or a combination of any one of these and H 2 may be used.
  • the flow rate of H 2 may be about 20-30 l/min and/or the flow rate of HCl about 100-200 ml/min.
  • the temperature may be ramped up to a pretreatment temperature and then ramped down immediately without keeping at the maximum temperature.
  • Pressure and temperature of the reactor as well as time sufficient to provide an oxygen free SiC substrate as detected by XPS may be determined by routine experimentation.
  • the pressure in the reactor upon pretreatment may be in the range of atmospheric pressure to 10 mbar, preferably about 50 mbar.
  • the background pressure in the reactor may be below 1 ⁇ 10 ⁇ 3 mbar. Preferable the background pressure should be as low as possible.
  • the reactor may be heated to about 1250-1500° C. by e.g. inductive or resistive heating for pretreatment at a pressure in the reactor of 50 mbar.
  • the pretreatment also is dependent on the pressure, i.e. if the pretreatment is performed at a lower temperature, the pressure may be lower in order to remove the surface contamination, mainly comprising oxygen but also carbon, as compared to if it is performed in a higher temperature where a wider range of pressures may be used in order to remove the same amount of contamination.
  • the SiC substrate may be pretreated by H 2 in 1250° C. at 50 mbar during a total pretreatment time (i.e. temperature ramp up and ramp down) of at least 30 min, which may result in a SiC substrate with less than 5% monolayer oxygen (i.e. less than 5% of the surface area is covered by oxygen) as detected by XPS.
  • a total pretreatment time i.e. temperature ramp up and ramp down
  • monolayer oxygen i.e. less than 5% of the surface area is covered by oxygen
  • XPS X-ray Photoelectron Spectroscopy
  • the bottom spectrum SiC substrate pretreated at 1200° C. in 50 mbar for 30 minutes
  • Those features can be derived from oxygen and carbon surface contamination present for non-pretreated and not sufficiently pretreated substrates.
  • the substrate pretreated at 1320° C. substantially lacks both the oxygen-related peak and the higher binding energy carbon feature.
  • the level of oxygen may not be detectable by XPS for substrates pretreated at temperatures above 1250° C. according to the process described above.
  • the pretreatment process of the SiC substrate may be the same, regardless of the method, i.e. MOCVD, HVPE or MBE, which will be used for growing the AlN nucleation layer and the subsequent layers. However, if performing the pretreatment in a MBE reactor, in which the pressure is lower as compared to e.g. a MOCVD reactor, both the pressure and temperature may be lower upon pretreatment as discussed above.
  • the In x Al y Ga 1-x-y N nucleation layer, e.g. Al y Ga 1-y N or AlN, and the In x Al y Ga 1-x-y N buffer layer, e.g. Al y Ga 1-y N or GaN, may be deposited by Metal Organic Chemical Vapor Deposition (MOCVD), which also is known as Metal Organic Vapor Phase Epitaxy (MOVPE).
  • MOCVD Metal Organic Chemical Vapor Deposition
  • MOVPE Metal Organic Vapor Phase Epitaxy
  • MOCVD or MOVPE, is a chemical vapor deposition method in which a solid material is deposited onto a substrate by chemical reactions of vapor phase precursors. The method is mainly used for growing complex semiconductor multilayer structures.
  • the precursors are metal-organic compounds, typically in combination with a hydride gas such as NH 3 .
  • Precursors used for the AlN nucleation growth may be trimethylaluminum (TMAl), i.e. Al 2 (CH 3 ) 6 , and ammonia, NH 3 .
  • TMAl trimethylaluminum
  • the flow rate of the precursors may be 2 l/min for NH 3 and 0.7 ml/min for TMAl.
  • the flow rate of the carrier gas flowing through the TMAl bubbler, e.g. H 2 may be 70 ml/min.
  • the precursor flow merges with a main carrier gas flow, which may be on the order of 50 l/min for further transport to the reactor.
  • the precursors are transported, often by means of a carrier gas, into a reactor chamber in which at least one substrate is placed. Reactions of the precursors forming reactive intermediates and by-products take place on the substrate or in near vicinity of the substrate. The reactants are adsorbed on the substrate, forming, a thin film layer and finally by-products are transported away from the substrate.
  • the pressure in a MOCVD system upon thin film growth normally ranges from a few mbars up to atmospheric pressure.
  • the reactor chamber may be of either cold-wall or hot-wall type.
  • a cold-wall reactor the substrate is typically heated while the reactor walls are kept cooler than the substrate.
  • a hot-wall reactor the entire reactor chamber is heated, i.e. both the substrate and the reactor.
  • the nucleation layer and the buffer layer may be grown by Hydride Vapor Phase Epitaxy (HVPE).
  • HVPE Hydride Vapor Phase Epitaxy
  • the HVPE process does not involve metal-organic precursors, instead gaseous metal chlorides, e.g. AlCl 3 are allowed to react with NH 3 upon AlN nucleation growth.
  • gaseous metal chlorides e.g. AlCl 3 are allowed to react with NH 3 upon AlN nucleation growth.
  • the same reactor may be used upon preparation of the nucleation and buffer layers as for the MOCVD.
  • the temperature and pressure upon growth may be the same as for growth by MOCVD.
  • the growth rate of an AlN nucleation layer may be 50 to 100 times higher, i.e. about 100 ⁇ m/h, by HVPE. If increasing the temperatures of the precursors, the growth rate may be even faster.
  • MBE Molecular Beam Epitaxy
  • MOCVD Metal Organic Chemical Vapor Deposition
  • precursors used upon preparation of AlN layers may be plasma-N 2 and Al 2 (CH 3 ) 6 .
  • the pressure may be in the range of 10 ⁇ 3 to 10 ⁇ 4 mbar resulting in a growth rate of below 1 ⁇ m/h, i.e. much lower than for MOCVD and HVPE.
  • MOCVD MOCVD
  • HVPE Hydride Vapor Phase Epitaxy
  • MBE Molecular Beam Epitaxy
  • the flow of the pretreatment gases e.g. HCl and/or H 2
  • the pretreatment gases e.g. HCl and/or H 2
  • the pretreated SiC substrate is transferred to the reactor in which the AlN nucleation layer growth should take place.
  • the transfer of the substrate may take place in ambient conditions, i.e. air.
  • the temperature and pressure of the reactor may be set, when the SiC substrate has been transferred into the reactor chamber, in the same way as discussed below.
  • the temperature of the reactor may be lowered while the pressure in the reactor may be maintained.
  • the lowering of the temperature may be performed in one step, i.e. the heating may be turned off or set at a lower temperature value.
  • the pressure may be increased as compared to the pressure used during the pretreatment.
  • the pressure may be controlled by the use of a valve, such as a throttle valve, which may be situated between the reactor and a pump, such as a roots pump, dry process vacuum pump, or screw pump.
  • a valve such as a throttle valve
  • a pump such as a roots pump, dry process vacuum pump, or screw pump.
  • Both the temperature and the pressure may be allowed to stabilize and after stabilization, if using HCl as pretreatment gas, the inlet of HCl to the reactor may be switched off (e.g. by closing a valve between the HCl source and the reactor). If using H 2 as pretreatment gas the flow may be maintained as it may be used as carrier gas for transportation of at least one of the precursors upon AlN nucleation layer growth.
  • the carrier gas may be an inert gas such as H 2 or N 2 .
  • H 2 or N 2 may be used for transportation of the precursors to the reactor and H 2 and N 2 are used as carrier gas in the growth zone of the reactor.
  • the carrier gas(es) are allowed to flow and optionally let into the reactor before the precursors are allowed to flow into the reactor (e.g. by opening a valve between the respective precursor and the reactor).
  • the containers storing the precursors may be temperature controlled, and the precursors may preferably be kept at room temperature.
  • at least one of the precursors may be heated, which may increase the vapor pressure of the heated precursor such that the growth rate of the layer may be increased.
  • heating is not always optimal.
  • At least one mass flow controller may be placed between each precursor container and the reactor in order to control the flow rate of each precursor into the reactor.
  • the precursors e.g. Al 2 (CH 3 ) 6 , and NH 3 , are then simultaneously transported in gaseous form by the carrier gas into the reactor, hence the AlN nucleation layer growth on the SiC substrate may begin.
  • the temperature inside the reactor is ramped up by a ramping rate of 5-25° C./min as measured inside the reactor for a time period of 2 min to 20 min. Under such conditions, 7 min growth may result in an AlN thickness of about 30-40 nm.
  • the thickness of the AlN nucleation layer should preferably be below 100 nm in the semiconductor device structure disclosed herein.
  • the temperature ramping may be incremental in small steps of e.g. 1/100 to 1 ⁇ 2 of the ramp rate.
  • the ramping may be continuously linear, progressive or degressive.
  • the ramping is continuously linear.
  • the starting temperature of the reactor may be the same, as for MOCVD growth. Also the pressure upon growth may be the same for HVPE as for MOCVD.
  • the starting temperature of the reactor may be in the range of 500-1000° C., i.e. lower as compared to growth by MOCVD and HVPE.
  • the lower starting temperature may be due to lower pressure during growth using MBE.
  • a buffer layer onto a nucleation layer (e.g. the AlN nucleation layer described above) will now be described with regard to a GaN buffer layer grown by the MOCVD (or MOVPE) method.
  • MOCVD MOCVD
  • the buffer layer may be deposited by HVPE or MBE as well.
  • the buffer layer may preferably, but need not, be grown in the same reactor as the nucleation layer.
  • the precursors used for GaN buffer layer growth may be trimethyl gallium, TMG, Ga(CH 3 ) 3 , and ammonia, NH 3 .
  • the flow rates of the precursors may be 2 l/min for NH 3 and 0.62 ml/min for TMGa.
  • the flow rate of the carrier gas flowing through the TMGa bubbler, e.g. H 2 may be 42 ml/min.
  • the precursors may be provided at room temperature. As an alternative at least one of the precursors may be heated in order to increase the flow rate and hence the growth rate of the GaN buffer layer.
  • each of the precursors may be controlled by at least one mass flow controller that may be situated between the precursor container and the reactor.
  • Each or both of the precursors may be transported by a carrier gas, such as H 2 , N 2 or Ar, into the reactor.
  • the temperature of the reactor may be about 1050° C. upon growth of the GaN layer.
  • the pressure in the reactor upon GaN growth may be about 50 mbar.
  • the growth of the GaN buffer layer may then be started when the temperature and pressure are stabilized. Under those conditions, the growth rate of the GaN layer may be about 700 to 2000 nm per hour. Preferably, the thickness of the GaN buffer layer may be about 1 to 4 ⁇ m in a SiC/AlN/GaN structure for e.g. a HEMT device.
  • the structure according to the prior art method was produced without pretreatment of the SiC substrate and without temperature ramping upon AlN nucleation layer growth.
  • the other parameters, such as temperature of the reactor and pressure upon growth, were the same for both AlN nucleation layer and GaN buffer layer growth. Both structures were produced by MOCVD and in the same reactor.
  • the thickness of the AlN nucleation layer grown according to the method disclosed herein was 38 nm and the thickness of the AlN nucleation layer grown according to the prior art method was 35 nm.
  • the thickness of both the GaN buffer layer grown onto the AlN nucleation layer grown according to the method disclosed herein and the thickness of the GaN buffer layer grown onto a AlN nucleation layer grown according to prior art was 1.8 ⁇ m.
  • the (002) plane gives information of screw-type dislocations and the (102), (103), (104), (105) planes give information of edge- and mixed-type dislocations for different extent.
  • the (105) plane usually gives more narrow peak width than the (102), (103), (104) planes.
  • a narrow rocking curve indicates a lower dislocation density and hence improved crystallinity as compared to a wide rocking curve.
  • the AlN nucleation layer grown according to the method disclosed herein presents a rocking curve with an AlN (105) peak having a Full Width Half Maximum (FWHM) of 105 arcsec.
  • FWHM Full Width Half Maximum
  • the reference AlN nucleation layer grown by the prior art method has a wider rocking curve of the AlN (105) peak with a FWHM of 703 arcsec.
  • the FWHM for AlN (105) peaks are of 30-200 arcsec for AlN nucleation layers produced by the method disclosed herein.
  • FIG. 3b shows rocking curves of the AlN (002) peak of AlN nucleation layers grown by the method disclosed herein using temperature ramp up and by the prior art method, respectively.
  • the AlN (002) peak of the AlN nucleation layer grown by the present method has a FWHM of 42 arcsec while the AlN (002) peak of the reference AlN nucleation layer grown by the prior art method is wider and has a FWHM of 99 arcsec.
  • the dislocation density of the AlN nucleation layer may be below 10 9 per cm 2 , and for the nucleation layer shown in FIG. 5b it is about 5 ⁇ 10 8 per cm 2 , as measured by XRD.
  • the impurity level may be less than 5 ⁇ 10 19 per cm 3 for AlN.
  • FIG. 4a Rocking curves of the GaN (102) peak of a GaN buffer layer in a SiC/AlN/GaN device structure grown by the method disclosed herein and of reference GaN buffer layer in a SiC/AlN/GaN device structure grown by a prior art method, respectively, are shown in FIG. 4a .
  • the reference GaN buffer layer has a GaN (102) peak with a FWHM of 491 arcsec while the corresponding peak of the GaN buffer layer grown by the method disclosed herein is narrower and has a FWHM of 205 arcsec indicating improved crystallinity as compared to the reference GaN buffer layer.
  • the rocking curve of the GaN (102) peak has a FWHM of 100-250 arcsec for GaN buffer layers in a SiC/AlN/GaN device structure grown by the method disclosed herein.
  • FIG. 4b the rocking curves of the GaN (002) peak of a GaN layer in a SiC/AlN/GaN device structure grown by the prior art method and by the method disclosed herein is shown.
  • the GaN (002) peak of the reference GaN layer has a FWHM of 207 arcsec
  • the GaN (002) peak of the GaN layer produced according to the method described herein has a narrower FWHM of 62 arcsec.
  • the GaN buffer layer indicates improved crystallinity.
  • the dislocation density of the GaN buffer layer may be 1 ⁇ 10 8 to 7 ⁇ 10 8 per cm 2 , as measured by XRD.
  • the impurity level for GaN may be less than 1 ⁇ 10 19 per cm 3 .
  • the thickness of the AlN nucleation layer (and the GaN buffer layer) is the same as for the layers shown in FIGS. 3a and 3b .
  • the AlN nucleation layer is slightly displaced as compared to SiC as in the x direction.
  • the SiC is located at the same position in FIGS. 5a and 5b due to its relative thick thickness as compared to the AlN nucleation layer.
  • By the use of the method disclosed herein fully strained high crystalline quality AlN nucleation layers may be produced.
  • the AlN should be aligned straight over SiC as seen in FIG. 5b .
  • the other features in FIGS. 5a and 5b illustrate subsequent layers of AlGaN and GaN.
  • FIGS. 6a and 6b AFM pictures of AlN nucleation layers produced according to a prior art method and according to the process disclosed herein respectively, are shown. The thicknesses of those layers are the same as for the AlN nucleation layers discussed in connection with FIGS. 3a, 3b, 5a , and 5 b.
  • such AlN nucleation layer may have about 80 to 100 pits per ⁇ m.
  • the maximum height of such a pit is the thickness of the AlN nucleation layer and the minimum height is 1 nm.
  • the AlN nucleation layer produced according to the process above has much fewer pits and exhibits full coalescence with 0-10 pits per ⁇ m 2 , preferably about 0-5 pits per ⁇ m 2 .
  • X-ray photoelectron spectroscopy (XPS) characterization of pretreated SiC substrates were performed at beamline I311 at the MAX national synchrotron laboratory. High energy resolution of less than 100 and 300 meV at photon energy of 140 and 750 eV, respectively, were utilized to collect the surface core levels spectra.
  • the HR-XRD system is equipped with a hybrid mirror and a triple-axis crystal as the primary and secondary optics, respectively, in which a resolution of ⁇ 0.003° ( ⁇ 11 arcsec) can be achieved.
  • the full width half maximum (FWHM) of the rocking curves of the AlN (002) and (105) peaks were measured in the symmetric and the asymmetric diffraction geometry.
  • the FWHM of the rocking curves of the GaN (002) and (102) peaks were measured in the symmetric and the skew diffraction geometry.
  • the surface morphology of AlN epilayers on SiC substrates was characterized by Atomic Force Microscopy (AFM).
  • AFM Atomic Force Microscopy
  • An AFM system (Vecco Dimension 3100) was employed at tapping mode. The system permits the spatial resolution 0.3 ⁇ 1 ⁇ along the vertical direction and 1 ⁇ 5 nm along the lateral direction, the resolutions of which are limited by the system background noise and the tip radius of curvature of 5 ⁇ 10 nm used in this study, respectively.

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Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020106842A1 (en) 2001-02-07 2002-08-08 Neudeck Philip G. Methods for growth of relatively large step-free sic crystal surfaces
JP2006066834A (ja) 2004-08-30 2006-03-09 Sumitomo Electric Ind Ltd 窒化ガリウム系化合物半導体トランジスタおよびその製造方法
US20070141823A1 (en) 2005-12-12 2007-06-21 Kyma Technologies, Inc. Inclusion-free uniform semi-insulating group III nitride substrates and methods for making same
KR20080088993A (ko) 2007-03-30 2008-10-06 주식회사 하이닉스반도체 다층 ＳｉＣ 웨이퍼 및 그의 제조방법
WO2009001888A1 (ja) 2007-06-27 2008-12-31 Nec Corporation 電界効果トランジスタ、ならびに、該電界効果トランジスタの作製に供される多層エピタキシャル膜
US20090045438A1 (en) * 2005-12-28 2009-02-19 Takashi Inoue Field effect transistor, and multilayered epitaxial film for use in preparation of field effect transistor
US20090189192A1 (en) * 2006-07-27 2009-07-30 Ruben Lieten DEPOSITION OF GROUP III-NITRIDES ON Ge
US20100032716A1 (en) * 2007-02-20 2010-02-11 Yoshihiro Sato Semiconductor device
US20100051961A1 (en) * 2008-09-04 2010-03-04 Ngk Insulators, Ltd. Epitaxial substrate, semiconductor device substrate, and hemt device
US20130200495A1 (en) * 2012-02-03 2013-08-08 Transphorm Inc. Buffer layer structures suited for iii-nitride devices with foreign substrates
US20140151748A1 (en) 2012-12-04 2014-06-05 Fujitsu Limited Compound semiconductor device and manufacturing method of the same
US20140264363A1 (en) 2013-03-14 2014-09-18 Mingwei Zhu Oxygen Controlled PVD Aluminum Nitride Buffer for Gallium Nitride-Based Optoelectronic and Electronic Devices
US20140346441A1 (en) * 2013-05-23 2014-11-27 Sensor Electronic Technology, Inc. Semiconductor Layer Including Compositional Inhomogeneities
JP2014241387A (ja) 2013-06-12 2014-12-25 住友電気工業株式会社 基板、基板の製造方法、及び電子装置
US20150076507A1 (en) * 2012-04-26 2015-03-19 Osram Opto Semiconductors Gmbh Epitaxy substrate, method for producing an epitaxy substrate and optoelectronic semiconductor chip comprising an epitaxy substrate

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009001888A (ja) * 2007-06-25 2009-01-08 Fuji Electronics Industry Co Ltd 誘導加熱装置の焼入条件監視装置及び焼入条件監視方法
CN102130223B (zh) * 2010-12-06 2012-07-25 山东华光光电子有限公司 一种GaN基LED外延片表面粗化方法
CN102593291B (zh) * 2011-01-07 2014-12-03 山东华光光电子有限公司 一种氮化物分布式布拉格反射镜及制备方法与应用
CN102522502B (zh) * 2012-01-10 2013-12-25 西安电子科技大学 基于SiC衬底的太赫兹GaN耿氏二极管及其制作方法

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020106842A1 (en) 2001-02-07 2002-08-08 Neudeck Philip G. Methods for growth of relatively large step-free sic crystal surfaces
JP2006066834A (ja) 2004-08-30 2006-03-09 Sumitomo Electric Ind Ltd 窒化ガリウム系化合物半導体トランジスタおよびその製造方法
US7777217B2 (en) * 2005-12-12 2010-08-17 Kyma Technologies, Inc. Inclusion-free uniform semi-insulating group III nitride substrate and methods for making same
US20070141823A1 (en) 2005-12-12 2007-06-21 Kyma Technologies, Inc. Inclusion-free uniform semi-insulating group III nitride substrates and methods for making same
US20090045438A1 (en) * 2005-12-28 2009-02-19 Takashi Inoue Field effect transistor, and multilayered epitaxial film for use in preparation of field effect transistor
US20090189192A1 (en) * 2006-07-27 2009-07-30 Ruben Lieten DEPOSITION OF GROUP III-NITRIDES ON Ge
US20100032716A1 (en) * 2007-02-20 2010-02-11 Yoshihiro Sato Semiconductor device
KR20080088993A (ko) 2007-03-30 2008-10-06 주식회사 하이닉스반도체 다층 ＳｉＣ 웨이퍼 및 그의 제조방법
WO2009001888A1 (ja) 2007-06-27 2008-12-31 Nec Corporation 電界効果トランジスタ、ならびに、該電界効果トランジスタの作製に供される多層エピタキシャル膜
US20100051961A1 (en) * 2008-09-04 2010-03-04 Ngk Insulators, Ltd. Epitaxial substrate, semiconductor device substrate, and hemt device
US20130200495A1 (en) * 2012-02-03 2013-08-08 Transphorm Inc. Buffer layer structures suited for iii-nitride devices with foreign substrates
US20150076507A1 (en) * 2012-04-26 2015-03-19 Osram Opto Semiconductors Gmbh Epitaxy substrate, method for producing an epitaxy substrate and optoelectronic semiconductor chip comprising an epitaxy substrate
US20140151748A1 (en) 2012-12-04 2014-06-05 Fujitsu Limited Compound semiconductor device and manufacturing method of the same
JP2014110393A (ja) 2012-12-04 2014-06-12 Fujitsu Ltd 化合物半導体装置及びその製造方法
US20140264363A1 (en) 2013-03-14 2014-09-18 Mingwei Zhu Oxygen Controlled PVD Aluminum Nitride Buffer for Gallium Nitride-Based Optoelectronic and Electronic Devices
US20140346441A1 (en) * 2013-05-23 2014-11-27 Sensor Electronic Technology, Inc. Semiconductor Layer Including Compositional Inhomogeneities
JP2014241387A (ja) 2013-06-12 2014-12-25 住友電気工業株式会社 基板、基板の製造方法、及び電子装置

Non-Patent Citations (25)

* Cited by examiner, † Cited by third party
Title
Amano, H., et al., "Metalorganic vapor phase epitaxial growth of a high quality GaN film using an AIN buffer layer", "Appl. Phys. Lett.", Feb. 3, 1986, pp. 353-355, vol. 48, No. 5.
Chen, JT, et al., "Impact of residual carbon on two-dimensional electron gas properties in AlxGa1-xN/GaN heteostructure", "Applied Physics Letters", 2013, p. 193506.1-193506.5, vol. 102, Publisher: AIP Publishing LLC.
Forsberg, U., et al., "Growth of High Quality AIN Epitaxial Films by Hot-Wall Chemical Vapour Deposition", "Materials Science Forum", 1998, pp. 1133-1136, vol. 264-268, Publisher: Trans Tech Publications, Switzerland.
International Search Report and Written Opinion in Counterpart International Patent Application PCT/EP2015/050353, dated Dec. 11, 2015.
Mathis, S.K., et al., "Modeling of Threading Dislocation Reduction in Growing GaN Layers", "phys stat, sol.", 2000, pp. 125-145, vol. 179.
Moram, M.A et al., "X-ray diffraction of III-nitrides", "Rep. Prog. Phys.", 2009, p. 036502 (40 pgs), vol. 72, Publisher: IOP Publishing.
Nakajima, A., et al., "Growth of High-Quality A1N With Low Pit Density on SiC Substrates", Journal of Crystal Growth, Feb. 10, 2004, pp. 351-356, vol. 265.
Nakajima, A., et al., "Step Control of Vicinal 6H-SIC(0001) Surface by H2 Etching", Journal of Applied Physics, May 13, 2005, p. 104919-1-104919-5, vol. 97.
Office Action in JPO in Japanese Patent Application 2017-554640, dated Nov. 27, 2018, English Summary.
Office Action of CNIPA in Chinese Patent Application 2015800754425, dated Mar. 26, 2020, English Summary.
Office Action of CNIPA in Chinese Patent Application 2015800754425, dated Mar. 26, 2020.
Office Action of EPO in European Patent Application 15700543.0, dated Dec. 13, 2019.
Office Action of Indian Patent Office in Indian Patent Application 201717028209, dated Aug. 14, 2020.
Office Action of JPO in Japanese Patent Application 2017-554640, dated Apr. 2, 2019, English Summary.
Office Action of JPO in Japanese Patent Application 2017-554640, dated Apr. 2, 2019.
Office Action of JPO in Japanese Patent Application 2017-554640, dated Nov. 27, 2018.
Office Action of KIPO in Korean Patent Application 10-2017-7021756, dated Dec. 28, 2020, English Summary.
Office Action of KIPO in Korean Patent Application 10-2017-7021756, dated Dec. 28, 2020.
Official Letter and Search Report for Taiwan Patent Application 105100569, dated Sep. 4, 2019, English Summary.
Official Letter and Search Report for Taiwan Patent Application 105100569, dated Sep. 4, 2019.
Qu, S., et al., "Influence of the Growth Temperature of A1N Buffer on the Quality and Stress of GaN Films Grown on 6H-SIC Substrate by MOVPE", Journal of Alloys and Compounds, May 4, 2010, pp. 417-422, vol. 502.
Result of consultation in European Patent Application 15700543.0, dated Dec. 1, 2020.
Soubatch, S., et al., "Structure and Morphology of 4H-SiC wafter Surfaces After H2-Etching", Materials Science Forum, May 15, 2005, pp. 761-764, vol. 483-485.
Summons to attend oral proceedings in European Patent Application 15700543.0, Sep. 11, 2020.
Yu, H., et al., "Experimental study of two-step growth of thin AIN film on 4H-SIC substrate by Metalorganic Chemical Vapor Deposition", "Journal of Optoelectronics and Advanced Materials", Dec. 2010, pp. 2406-2412, vol. 12, No. 12.

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