US8581323B2 - Nonvolatile semiconductor memory device and method of manufacturing same - Google Patents

Nonvolatile semiconductor memory device and method of manufacturing same Download PDF

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US8581323B2
US8581323B2 US12/727,708 US72770810A US8581323B2 US 8581323 B2 US8581323 B2 US 8581323B2 US 72770810 A US72770810 A US 72770810A US 8581323 B2 US8581323 B2 US 8581323B2
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protecting
memory device
conductive
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US20110169071A1 (en
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Tsuneo Uenaka
Kazuyuki Higashi
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Toshiba Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Definitions

  • JP2007-266143A In recent years, many semiconductor memory devices that include memory cells three-dimensionally in order to increase the degree of memory integration have been proposed (JP2007-266143A).
  • one conventional semiconductor memory device that includes memory cells three-dimensionally uses transistors having a columnar structure (see JP2007-266143A).
  • the transistors having a columnar structure include a columnar semiconductor layer having a columnar shape, a memory gate insulating layer, and multi-stacked conductive layers functioning as gate electrodes.
  • the columnar semiconductor layer functions as a channel (body) of the transistors.
  • the memory gate insulating layer is formed around the columnar semiconductor layer, and can store charges.
  • the conductive layers are formed to surround the columnar semiconductor layer via the memory gate insulating layer.
  • Such a three-dimensional structure can increase the memory capacity not by fine patterning but by multi-stacking, allowing process construction with techniques that are extended from conventional techniques.
  • contact layers which are formed to contact the multi-stacked conductive layers (gate electrodes) respectively.
  • it is not easy to form the contact layers because they need to be formed to adjust to the height of the respective conductive layers. If the contact layers cannot be formed correctly, it is impossible to control the gates of the transistors accurately, spoiling the stability of the operation of the nonvolatile semiconductor memory device.
  • a nonvolatile semiconductor memory device includes a plurality of memory strings including a plurality of memory transistors connected in series, the memory transistors being electrically rewritable, the memory strings including: a first semiconductor layer including a columnar portion extending in a perpendicular direction relative to a substrate, the first semiconductor layer being configured to function as a body of the memory transistors; a charge storing layer formed to surround a side surface of the columnar portion and configured to store a charge; a plurality of first conductive layers formed to surround the side surface of the columnar portion and the charge storing layer and configured to function as gates of the memory transistors; and a first protecting layer stacked to protect a top portion of the plurality of first conductive layers, the plurality of first conductive layers constituting a first stairway portion formed stepwise such that ends of the first conductive layers are located at different positions, each of the first conductive layers constituting a step of the first stairway portion, a top surface of a first portion of the
  • a method of manufacturing a nonvolatile semiconductor memory device is a method of manufacturing a nonvolatile semiconductor memory device including a plurality of memory strings including a plurality of memory transistors connected in series, the memory transistors being electrically rewritable, the method including; stacking a plurality of conductive layers; forming a through hole to penetrate the plurality of conductive layers; forming a charge storing layer on a side surface of the through hole; forming a semiconductor layer to fill the through hole; forming a first stairway portion by processing those of the conductive layers between a topmost conductive layer and a fifth conductive layer as one of the conductive layers below the topmost conductive layer by a first number, such that ends of the plurality of conductive layers are located at different positions; forming a first protecting layer to cover the first stairway portion; dividing the first protecting layer, and forming a second stairway portion by processing those of the conductive layers below the fifth conductive layer, such that the ends of the
  • FIG. 1 is a block diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.
  • FIG. 2 is a schematic perspective diagram of the nonvolatile semiconductor memory device according to the first embodiment.
  • FIG. 3 is a circuit diagram of a memory cell array 11 shown in FIG. 2 .
  • FIGS. 4 , 6 - 20 are cross sections of the nonvolatile semiconductor memory device according to the first embodiment.
  • FIG. 5 is an expanded diagram of FIG. 4 .
  • FIG. 21 shows schematic diagrams of nonvolatile semiconductor memory devices according to the first embodiment and a comparative example.
  • FIGS. 22-28 show schematic perspective diagrams showing a nonvolatile semiconductor memory device according to a second embodiment of the present invention.
  • FIG. 29 is a cross section of a nonvolatile semiconductor memory device according to a third embodiment of the present invention.
  • FIG. 30 is across section of a nonvolatile semiconductor memory device according to another embodiment of the present invention.
  • FIG. 31 is a diagram showing a row-direction length L 0 of a step ST 3 of the first embodiment.
  • FIG. 1 is a block diagram of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.
  • FIG. 2 is a schematic perspective diagram of the nonvolatile semiconductor memory device.
  • the nonvolatile semiconductor memory device includes a memory cell array 11 , row decoders 12 and 13 , a sense amplifier 14 , a column decoder 15 , and a control signal generating unit (high voltage generating unit) 16 .
  • the memory cell array 11 is constituted by memory transistors MTr, which store data electrically, and which are arranged in a three-dimensional matrix formation. That is, the memory transistors MTr are arranged in a matrix formation horizontally, and also arranged in the stacking direction.
  • a plurality of memory transistors MTr which are arranged side by side in the stacking direction are connected in series and form a well-known NAND string (memory string) MS.
  • the memory string MS has its both ends connected respectively to a drain-side selector transistor SDTr and a source-side selector transistor SSTr, which come into electrical conduction when selected.
  • the NAND string MS is disposed such that its longer side extends in the stacking direction.
  • the row decoders 12 and 13 decode a received block address signal, etc. and control the memory cell array 11 .
  • the sense amplifier 14 reads out data from the memory cell array 11 .
  • the column decoder 15 decodes a column address signal and controls the sense amplifier 14 .
  • the control signal generating unit 16 generates a high voltage necessary for writing and erasing by stepping up a base voltage, and also generates a control signal and controls the row decoders 12 and 13 , the sense amplifier 14 , and the column decoder 15 .
  • the memory cell array 11 includes a plurality of memory blocks MB.
  • a memory block MB includes a plurality of memory strings MS, source-side selector transistors SSTr, and drain-side selector transistors SDTr.
  • a memory string MS includes memory transistors MTr 1 to MTr 4 , which are connected in series.
  • the drain-side selector transistor SDTr is connected to one end (the memory transistor MTr 4 ) of the memory string MS.
  • the source-side selector transistor SSTr is connected to the other end (the memory transistor MTr 1 ) of the memory string MS.
  • such memory strings MS are provided in each memory block MB along plural row and plural columns in a matrix formation.
  • the memory string MS may include more than four memory transistors.
  • the control gates of the memory transistors MTr 1 that are arranged in the matrix formation are connected in common to a word line WL 1 .
  • the control gates of the memory transistors MTr 2 to MTr 4 are connected in common to word lines WL 2 to WL 4 respectively.
  • the control gates of the drain-side selector transistors SDTr which are arranged in line in the row direction are connected in common to a drain-side selector gate line SGD.
  • the drain-side selector gate line SGD is formed to extend over a plurality of memory blocks MB in the row direction.
  • One memory block MB includes a plurality of drain-side selector gate lines SGD, which are provided at a predetermined pitch in the column direction.
  • the drain-side selector transistors SDTr which are arranged in line in the column direction have their other end connected to a bit line BL in common.
  • the bit line BL is formed to extend over a plurality of memory blocks MB in the column direction.
  • a plurality of bit lines BL are provided in the row direction.
  • all the source-side selector transistors included therein have their control gates connected in common to a source-side selector gate line SGS.
  • the source-side selector transistors SSTr have their other end connected in common to a source line SL.
  • FIG. 4 is a cross section of the nonvolatile semiconductor memory device according to the first embodiment.
  • the nonvolatile semiconductor memory device is stacked within a memory region AR 1 and a peripheral region AR 2 of a semiconductor substrate Ba.
  • the memory region AR 1 functions as the memory cell array 11 .
  • the peripheral region AR 2 is provided on the periphery of the memory region AR 1 and functions as various control circuits ( 12 to 16 ).
  • the memory region AR 1 includes a source-side selector transistor layer 20 , a memory transistor layer 30 , a drain-side selector transistor layer 40 , and a wiring layer 50 , which are sequentially stacked on the semiconductor substrate Ba.
  • the semiconductor substrate Ba within the memory region AR 1 functions as a source line SL.
  • the source-side selector transistor layer 20 functions as the source-side selector transistors SSTr.
  • the memory transistor layer 30 functions as the memory strings MS (memory transistors MTr 1 to MTr 4 ).
  • the drain-side selector transistor layer 40 functions as the drain-side selector transistors SDTr.
  • the wiring layer 50 functions as the bit lines BL and various other wires.
  • the semiconductor substrate Ba includes a diffused layer Ba 1 in its top surface.
  • the diffused layer Ba 1 functions as the source line SL.
  • the source-side selector transistor layer 20 includes an insulating layer 21 , a source-side conductive layer 22 , and an insulating layer 23 , which are sequentially stacked above the semiconductor substrate Ba.
  • the source-side conductive layer 22 functions as the gates of the source-side selector transistors SSTr and as the source-side selector gate line SGS.
  • the source-side conductive layer 22 is formed to spread two-dimensionally (like a plate) in the row and column directions to cover one memory block MB.
  • the insulating layers 21 and 23 are made of silicon oxide (SiO 2 ).
  • the source-side conductive layer 22 is made of polysilicon (poly-Si).
  • the source-side selector transistor layer 20 has source-side holes 24 .
  • the source-side holes 24 are formed to penetrate the insulating layer 21 , the source-side conductive layer 22 , and the insulating layer 23 .
  • the source-side holes 24 are provided in a matrix formation in the row and column directions.
  • the source-side selector transistor layer 20 includes a source-side gate insulating layer 25 and a source-side columnar semiconductor layer 26 .
  • the source-side columnar semiconductor layer 26 functions as a body (channel) of the source-side selector transistor SSTr.
  • the source-side gate insulating layer 25 is formed on a side wall of the source-side hole 24 to have a predetermined thickness.
  • the source-side columnar semiconductor layer 26 is formed to contact the side surface of the source-side gate insulating layer 25 and fill the source-side hole 24 .
  • the source-side columnar semiconductor layer 26 is formed in a columnar shape that extends in the stacking direction.
  • the source-side columnar semiconductor layer 26 is formed on the diffused layer Ba 1 of the semiconductor substrate Ba.
  • the source-side gate insulating layer 25 is made of silicon oxide (SiO 2 ).
  • the source-side columnar semiconductor layer 26 is made of polysilicon (poly-Si).
  • the source-side gate insulating layer 25 is formed to surround the source-side columnar semiconductor layer 26 .
  • the source-side conductive layer 22 is formed to surround the source-side columnar semiconductor layer 26 via the source-side gate insulating layer 25 .
  • the memory transistor layer 30 includes word line conductive layers 31 a to 31 d , insulating layers 32 a to 32 d , and protecting layers 33 a and 33 b , which are stacked sequentially on the source-side selector transistor layer 20 .
  • the word line conductive layers 31 a to 31 d function as the gates of the memory transistors MTr 1 to MTr 4 and as the word lines WL 1 to WL 4 .
  • holes 55 a to 55 d are formed from a layer provided above to reach the top surface of the word line conductive layers 31 a to 31 d .
  • the protecting layers 33 a and 33 b protect the word line conductive layers 31 a to 31 d and prevent the holes 55 a to 55 d from becoming deeper than a predetermined depth.
  • the word line conductive layers 31 a to 31 d and the insulating layers 32 a to 32 d are formed to spread two-dimensionally (like a plate) in the row and column directions.
  • the word line conductive layers 31 a to 31 d and the insulating layers 32 a to 32 d are divided memory block MB by memory block MB.
  • the word line conductive layers 31 a to 31 d and the insulating layers 32 a to 32 d are formed stepwise such that their row-direction ends facing the peripheral region AR 2 are located at different positions. That is, the row-direction ends of the word line conductive layers 31 a to 31 d and insulating layers 32 a to 32 d constitute a stairway portion ST that is formed like a staircase.
  • the stairway portion ST is formed to descend in the row direction toward the peripheral region AR 2 .
  • the stairway portion ST includes steps (stages) ST 1 to ST 4 that are arranged side by side in one line in the row direction. As shown in FIG. 4 , each of the steps ST 1 to ST 4 is constituted by an end portion of one of the word line conductive layers 31 a to 31 d and an end portion of one of the insulating layers 32 a to 32 d.
  • the protecting layer 33 a covers side surfaces of row-direction end portions of the steps ST 3 and ST 4 (the word line conductive layers 31 c and 31 d and the insulating layers 32 c and 32 d ).
  • the protecting layer 33 a also covers top surfaces of the steps ST 2 to ST 4 (the insulating layers 32 b to 32 d ).
  • the protecting layer 33 b covers the protecting layer 33 a .
  • the protecting layer 33 b also covers side surfaces of row-direction end portions of the steps ST 1 and ST 2 (the word line conductive layers 31 a and 31 b and the insulating layers 32 a and 32 b ).
  • the protecting layer 33 b also covers a top surface of the step ST 1 (the insulating layer 32 a ).
  • the steps ST 2 to ST 4 (first portion), which are the second or higher-order steps as counted upward from the bottom, have their top surface covered with two protecting layers 33 a and 33 b .
  • the step ST 1 (second portion located at a lower level than the first portion), which is the first step as counted upward from the bottom, has its top surface covered with one protecting layer 33 b .
  • the protecting layer 33 a is not formed on the top surface of the step ST 1 .
  • the word line conductive layers 31 a to 31 d are made of polysilicon (poly-Si)
  • the insulating layers 32 a to 32 d are made of silicon oxide (SiO 2 ).
  • the protecting layers 33 a and the protecting layers 33 b are made of the same material, e.g., silicon nitride (SiN).
  • the memory transistor layer 30 has memory holes 34 .
  • the memory holes 34 are formed to penetrate the word line conductive layers 31 a to 31 d and the insulating layers 32 a to 32 d .
  • the memory holes 34 are provided in a matrix formation in the row and column directions.
  • the memory holes 34 are formed at positions matching the source-side holes 24 .
  • the memory transistor layer 30 also includes a memory gate insulating layer 35 and a memory columnar semiconductor layer 36 .
  • the memory columnar semiconductor layer 36 functions as a body (channel) of the memory transistors MTr 1 to MTr 4 .
  • the memory gate insulating layer 35 is formed on a side wall of the memory hole 34 to have a predetermined thickness.
  • the memory columnar semiconductor layer 36 is formed to contact the side surface of the memory gate insulating layer 35 and fill the memory hole 34 .
  • the memory columnar semiconductor layer 36 is formed in a columnar shape that extends in the stacking direction. A bottom surface of the memory columnar semiconductor layer 36 contacts a top surface of the source-side columnar semiconductor layer 26 .
  • FIG. 5 is an expanded diagram of FIG. 4 .
  • the memory gate insulating layer 35 includes a block insulating layer 35 a , a charge storing layer 35 b , and a tunnel insulating layer 35 c , which are formed in this order from the side surface of the memory hole 34 toward the memory columnar semiconductor layer 36 .
  • the charge storing layer 35 b can store charges.
  • the block insulating layer 35 a is formed on the side wall of the memory hole 34 to have a predetermined thickness.
  • the charge storing layer 35 b is formed on a side wall of the block insulating layer 35 a to have a predetermined thickness.
  • the tunnel insulating layer 35 c is formed on a side wall of the charge storing layer 35 b to have a predetermined thickness.
  • the block insulating layer 35 a and the tunnel insulating layer 35 c are made of silicon oxide (SiO 2 ).
  • the charge storing layer 35 b is made of silicon nitride (SiN).
  • the memory columnar semiconductor layer 36 is made of polysilicon (poly-Si).
  • the tunnel insulating layer 35 c is formed to surround the memory columnar semiconductor layer 36 .
  • the charge storing layer 35 b is formed to surround the tunnel insulating layer 35 c .
  • the block insulating layer 35 a is formed to surround the charge storing layer 35 b .
  • the word line conductive layers 31 a to 31 d are formed to surround the block insulating layer 35 a.
  • the drain-side selector transistor layer 40 includes a drain-side conductive layer 41 and protecting layers 42 a and 42 b .
  • the drain-side conductive layer 41 functions as the gates of the drain-side selector transistors SDTr and as the drain-side selector gate lines SGD.
  • the drain-side conductive layer 41 is stacked on the memory transistor layer 30 .
  • the drain-side conductive layer 41 is formed immediately above where the memory columnar semiconductor layers 36 are formed.
  • the drain-side conductive layer 41 extends in the row direction and is formed as stripes that are provided at a predetermined pitch in the column direction.
  • the drain-side conductive layer 41 is formed such that its row-direction end is located at a position that is different from the position of the row-direction end of the word line conductive layer 31 d , thereby forming a step ST 5 .
  • the protecting layer 42 a is formed to cover the drain-side conductive layer 41 and to be continuous and integral with the protecting layer 33 a .
  • the protecting layer 42 b is formed to cover the protecting layer 42 a and to be continuous and integral with the protecting layer 33 b.
  • the drain-side conductive layer 41 is made of, for example, polysilicon (poly-Si).
  • the protecting layers 42 a and 42 b are made of silicon nitride (SiN).
  • the drain-side selector transistor layer 90 has drain-side holes 43 .
  • the drain-side holes 43 are formed to penetrate the drain-side conductive layer 41 and the protecting layers 42 a and 42 b .
  • the drain-side holes 43 are provided in a matrix formation in the row and column directions.
  • the drain-side holes 43 are formed at positions matching the memory holes 34 .
  • the drain-side selector transistor layer 40 includes a drain-side gate insulating layer 44 and a drain-side columnar semiconductor layer 45 .
  • the drain-side columnar semiconductor layer 45 functions as a body (channel) of the drain-side selector transistor SDTr.
  • the drain-side gate insulating layer 44 is formed on a side wall of the drain-side hole 43 to have a predetermined thickness.
  • the drain-side columnar semiconductor layer 45 is formed to contact the drain-side gate insulating layer 44 and fill the drain-side hole 43 .
  • the drain-side columnar semiconductor layer 45 is formed in a columnar shape that extends in the stacking direction. A bottom surface of the drain-side columnar semiconductor layer 45 contacts a top surface of the memory columnar semiconductor layer 36 .
  • the drain-side gate insulating layer 44 is made of silicon oxide (SiO 2 ).
  • the drain-side columnar semiconductor layer 45 is made of polysilicon (poly-Si).
  • the drain-side gate insulating layer 44 is formed to surround the drain-side columnar semiconductor layer 45 .
  • the drain-side conductive layer 41 is formed to surround the drain-side columnar semiconductor layer 45 via the drain-side gate insulating layer 44 .
  • the wiring layer 50 includes a first wiring layer 51 , a second wiring layer 52 , and contact plug layers 53 a to 53 d .
  • the first wiring layer 51 functions as the bit lines BL.
  • the second wiring layer 52 functions as various wires to be connected to the word lines WL 1 to WL 4 .
  • the first wiring layer 51 and the second wiring layer 52 are formed in a layer above the drain-side selector transistor layer 40 .
  • the first wiring layer 51 is formed to contact a top surface of the drain-side columnar semiconductor layers 45 .
  • the first wiring layer 51 is formed at a predetermined pitch in the row direction to extend in the column direction.
  • the second wiring layer 52 is formed at a predetermined pitch in the column direction to extend in the row direction.
  • Each of the contact plug layers 53 a to 53 d is formed to connect a bottom surface of the second wiring layer 52 to a top surface of a corresponding one of the word line conductive layers 31 a to 31 d .
  • the first wiring layer 51 , the second wiring layer 52 , and the contact plug layers 53 are made of tungsten (W).
  • the contact plug layers 53 a to 53 d will now be described in more detail.
  • the contact plug layers 53 a to 53 d are formed in holes 55 a to 55 d .
  • the holes 55 a to 55 d are formed to penetrate an interlayer insulating layer 56 that covers the source-side selector transistor layer 20 , the memory transistor layer 30 , and the drain-side selector transistor layer 90 .
  • the holes 55 a to 55 d are formed to also penetrate the protecting layers 33 a and 33 b and the respective insulating layers 32 a to 32 d.
  • the peripheral region AR 2 includes a peripheral wiring layer 60 , a first dummy layer 70 , a second dummy layer 80 , and the wiring layer 50 , which are stacked sequentially on the semiconductor substrate Ba.
  • the semiconductor substrate Ba within the peripheral region AR 2 functions as sources/drains of various transistors.
  • the peripheral wiring layer 60 functions as transistors constituting the row decoder 12 , etc. and as other wires.
  • the first dummy layer 70 and the second dummy layer 80 are layers where contact plug layers are formed. These contact plug layers extend from a layer above the first dummy layer 70 and the second dummy layer 80 to the peripheral wiring layer 60 or to the semiconductor substrate Ba.
  • the first dummy layer 70 and the second dummy layer 80 do not function as wires.
  • the semiconductor substrate Ba includes diffused layers Ba 2 in its surface.
  • the diffused layers Ba 2 function as the source/drain of the transistors constituting the row decoder 12 , etc.
  • the peripheral wiring layer 60 is formed in the same layer as the source-side selector transistor layer 20 .
  • the first dummy layer 70 is formed in the same layer as the memory transistor layer 30 .
  • the second dummy layer 80 is formed in the same layer as the drain-side selector transistor layer 40 .
  • the peripheral wiring layer 60 , the first dummy layer 70 , and the second dummy layer 80 share the same layers as the source-side selector transistor layer 20 , the memory transistor layer 30 , and the drain-side selector transistor layer 40 when deposited, respectively, but are divided from them by etching.
  • the wiring layer 50 is provided in common between the memory region AR 1 and the peripheral region AR 2 .
  • the peripheral wiring layer 60 includes an insulating layer 61 , a conductive layer 62 , and an insulating layer 63 , which are stacked sequentially on the semiconductor substrate Ba.
  • the conductive layer 62 functions as the gate of the transistors constituting the row decoder 12 and as other wires.
  • the insulating layer 61 is formed in the same layer as the insulating layer 21 .
  • the conductive layer 62 is formed in the same layer as the source-side conductive layer 22 .
  • the insulating layer 63 is formed in the same layer as the insulating layer 23 .
  • the peripheral wiring layer 60 has through holes 64 and interlayer insulating layers 65 .
  • the through holes 64 are formed to penetrate the insulating layer 61 , the conductive layer 62 , and the insulating layer 63 .
  • the through holes 64 are formed at positions matching the diffused layers Ba 2 .
  • the interlayer insulating layers 65 are formed to fill the through holes 64 .
  • the dummy layer 70 includes conductive layers 71 a to 71 d , insulating layers 72 a to 72 d , and protecting layers 73 a and 73 b , which are sequentially stacked on the peripheral wiring layer 60 .
  • the conductive layers 71 a to 71 d are formed in the same layers as the word line conductive layers 31 a to 31 d .
  • the insulating layers 72 a to 72 d are formed in the same layers as the insulating layers 32 a to 32 d .
  • the conductive layers 71 a to 71 d and the insulating layers 72 a to 72 d are formed stepwise such that their row-direction ends facing the memory region AR 1 are located at different positions. That is, the row-direction ends of the conductive layers 71 a to 71 d and insulating layers 72 a to 72 d constitute a stairway portion STa that is formed like a staircase.
  • the stairway portion STa is formed to descend in the row direction toward the memory region AR 1 .
  • the stairway portion STa includes steps (stages) ST 1 a to ST 4 a that are arranged side by side in one line in the row direction. As shown in FIG. 4 , each of the steps ST 1 a to ST 4 a is constituted by an end portion of one of the conductive layers 71 a to 71 d and an end portion of one of the insulating layers 72 a to 72 d.
  • the protecting layer 73 a covers side surfaces of the row-direction end portions of the steps ST 3 a and ST 4 a (the conductive layers 71 c and 71 d and the insulating layers 72 c and 72 d ).
  • the protecting layer 73 a also covers top surfaces of the steps ST 2 a to ST 4 a (the insulating layers 72 b to 72 d ).
  • the protecting layer 73 b covers the protecting layer 73 a .
  • the protecting layer 73 b also, covers side surfaces of the row-direction end portions of the steps ST 1 a and ST 2 a (the conductive layers 71 a and 71 b and the insulating layers 72 a and 72 b ).
  • the protecting layer 73 b also covers a top surface of the step ST 1 a (the insulating layer 72 a ).
  • the protecting layer 73 b is formed to be continuous and integral with the protecting layer 33 b . That is, the steps ST 2 a to ST 4 a (first portion), which are the second or higher-order steps as counted upward from the bottom, have their top surface covered with two protecting layers 73 a and 73 b .
  • the step ST 1 a (second portion located at a lower level than the first portion), which is the first step as counted upward from the bottom, has its top surface covered with one protecting layer 73 b . In other words, the protecting layer 73 a is not formed on the top surface of the step ST 1 a.
  • the first dummy layer 70 has through holes 74 and interlayer insulating layers 75 .
  • the through holes 74 are formed to penetrate the conductive layers 71 a to 71 d and the insulating layers 72 a to 72 d .
  • the through holes 74 are formed at positions matching the through holes 64 .
  • the interlayer insulating layers 75 are formed to fill the through holes 74 .
  • the second dummy layer 80 includes a conductive layer 81 and protecting layers 82 a and 82 b , which are stacked on the first dummy layer 70 .
  • the conductive layer 81 is formed in the same layer as the drain-side conductive layer 41 .
  • the conductive layer 81 is formed such that its row-direction end is located at a position different from the position of the row-direction end of the conductive layer 71 d , thereby forming a step ST 5 a.
  • the protecting layer 82 a is formed to cover the conductive layer 81 and to be continuous and integral with the protecting layer 73 a .
  • the protecting layer 82 b is formed to cover the protecting layer 82 a and to be continuous and integral with the protecting layer 73 b.
  • the second dummy layer 80 has through holes 83 and interlayer insulating layers 84 .
  • the through holes 83 are formed to penetrate the conductive layer 81 .
  • the through holes 83 are formed at positions matching the through holes 74 .
  • the interlayer insulating layers 84 are formed to fill the through holes 83 .
  • the wiring layer 50 includes a second wiring layer 52 and contact plug layers 54 a and 54 b .
  • the contact plug layers 54 a extend downward while penetrating the interlayer insulating layers 65 , 75 , and 84 , thereby electrically connecting the second wiring layer 52 and the diffused layers Ba 2 .
  • the contact plug layer 54 b extends downward while penetrating the interlayer insulating layers 75 and 84 , thereby electrically connecting the second wiring layer 52 and the conductive layer 62 .
  • FIG. 6 to FIG. 20 are cross sections showing the process of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
  • the process to be shown below is a process after the source-side selector transistor layer 20 (the peripheral wiring layer 60 ) is formed.
  • polysilicon poly-Si
  • silicon oxide SiO 2
  • the layers 31 Aa to 31 Ad will later be processed into the word line conductive layers 31 a to 31 d and the conductive layers 71 a to 71 d .
  • the layers 32 Aa to 32 Ad will later be processed into the insulating layers 32 a to 32 d and the insulating layers 72 a to 72 d .
  • the layer 41 A will later be processed into the drain-side conductive layer 41 and the conductive layer 81 .
  • the layer 41 A is pattern-etched to form a groove 90 therein.
  • the groove 90 is formed to penetrate the layer 41 A.
  • the groove 90 has a width D in the row direction, the center of which is at the boundary A between the memory region AR 1 and the peripheral region AR 2 .
  • a first stairway portion ST( 1 ) is formed by processing the layers 31 Ad and 31 Ac, which are the topmost layer and the first layer as counted downward from the topmost layer 31 Ad, such that the ends of the layers 31 Ad and 31 Ac are located at different positions. That is, first, as shown in FIG. 8 , a resist layer 91 Aa is formed to cover the layer 41 A. Here, the resist layer 91 Aa has a groove 92 Aa that extends in the column direction. The groove 92 Aa is formed to penetrate the resist layer 91 Aa. The groove 92 Aa has a width D 1 (D 1 ⁇ D) in the row direction, the center of which is at the boundary A.
  • etching by using the resist layer 91 Aa as a mask is carried out to form a groove 93 a that penetrates the layer 31 Ad and the layer 32 Ad.
  • the groove 93 a has a width D 1 in the row direction, the center of which is at the boundary A.
  • the resist layer 91 Aa is slimmed in the row direction.
  • the resist layer 91 Aa comes to have a groove 92 Ab.
  • the groove 92 Ab has a width D 2 (D 1 ⁇ D 2 ⁇ D) in the row direction, the center of which is at the boundary A.
  • etching by using the resist layer 91 Aa as a mask is carried out to form a groove 93 b that penetrates the layer 31 Ad and the layer 32 Ad, and a groove 93 c that penetrates the layer 31 Ac and the layer 32 Ac.
  • the grooves 93 b and 93 c are formed to have their center located at the boundary A.
  • the groove 93 b has a width. D 2 in the row direction and the groove 93 c has a width D 1 in the row direction.
  • the resist layer 91 Aa is removed, and silicon nitride is deposited to form a protecting layer 94 a .
  • the protecting layer 94 a will later be processed into the protecting layers 33 a , 92 a , 73 a , and 82 a .
  • the protecting layer 94 a is formed to cover the stairway portion ST( 1 ) (the layers 31 Ad, 32 Ad, 31 Ac, 32 Ac, and 32 Ab).
  • the protecting layer 94 a is divided. Further, the layers 31 Ab and 31 Aa, which are the second layer as counted downward from the topmost layer, and the first layer as counted downward from this layer, are processed such that the ends of the layers 31 Ab and 31 Aa are located at different positions, thereby forming a stairway portion ST( 2 ).
  • a resist layer 91 Ab is formed on the protecting layer 94 a .
  • the resist layer 91 Ab has a groove 92 Ac that extends in the column direction.
  • the groove 92 Ac is formed to penetrate the resist layer 91 Ab.
  • the groove 92 Ac has a width D 3 (D 3 ⁇ D 1 ) in the row direction, the center of which is at the boundary A.
  • etching by using the resist layer 91 Ab as a mask is carried out to form a groove 93 d that penetrates the layer 31 Ab, the layer 32 Ab, and the protecting layer 94 a .
  • the groove 93 d has a width D 3 in the row direction, the center of which is at the boundary A.
  • the resist layer 91 Ab is slimmed in the row direction.
  • the resist layer 91 Ab comes to have a groove 92 Ad.
  • the groove 92 Ad has a width D 4 (D 3 ⁇ D 4 ⁇ D 1 ) in the row direction, the center of which is at the boundary A.
  • etching by using the resist layer 91 Ab as a mask is carried out to form a groove 93 e and a groove 93 f .
  • the groove 93 e is formed to penetrate the layer 31 Ab, the layer 32 Ab, and the protecting layer 94 a
  • the groove 93 f is formed to penetrate the layer 31 Aa and the layer 32 Aa.
  • the grooves 93 e and 93 f are formed to have their center located at the boundary A.
  • the groove 93 e has a width D 4 in the row direction.
  • the groove 93 f has a width D 3 in the row direction.
  • the resist layer 91 Ab is removed.
  • the layers 31 Ab and 31 Aa are processed to constitute the stairway portion ST( 2 ), in which their ends are located at different positions.
  • silicon nitride is deposited to form a protecting layer 94 b on the protecting layer 94 a .
  • the protecting layer 94 b will later be processed into the protecting layers 33 b , 42 b , 73 b , and 82 b .
  • the protecting layer 94 b is formed to cover the second stairway portion ST( 2 ) (the layers 31 Ab and 31 Aa) and the protecting layer 94 a.
  • silicon oxide is deposited to form the interlayer insulating layer 56 .
  • a top surface of the interlayer insulating layer 56 is planarized by CMP.
  • the holes 55 a to 55 d that penetrate the interlayer insulating layer 56 are formed, and tungsten is deposited to fill the holes 55 a to 55 d , whereby the contact plug layers 53 a to 53 d are formed.
  • reactive ion etching is used under a processing condition in which etching selectivity of the protecting layers 94 a and 94 b is high. This makes it possible to simultaneously form the contact plug layers 53 a to 53 d , which have different lengths in the stacking direction.
  • the first embodiment will be shown in contrast with a comparative example to explain advantages of the first embodiment.
  • the memory transistor layer 30 includes two protecting layers 33 a and 33 b , which are formed over different regions.
  • the memory transistor layer 30 includes only one protecting layer 33 .
  • the hole 55 d is formed to dig into the topmost word line conductive layer 31 d . That is, in the comparative example, the word line conductive layer 31 d becomes deficient.
  • one protecting layer 33 a is formed above the word line conductive layer 31 a above which a long hole 55 a is formed, while two protecting layers 33 a and 33 b are formed above the word line conductive layer 31 d above which a short hole 55 d is formed.
  • the number (thickness) of protecting layers 33 a and 33 b to be stacked is determined in accordance with the length of the holes 55 a to 55 d , and hence the word line conductive layer 31 d will not become deficient like it does in the comparative example. That is, the first embodiment can realize a stable operation.
  • the processing condition changes at the interface between the protecting layer 33 a and the protecting layer 33 b .
  • the tapered shape of the holes 55 a to 55 d changes at the interface to deform the shape of the contact plug layers 53 a to 53 d.
  • the protecting layer 33 a and the protecting layer 33 b are made of the same material and have the same etching rate. Hence, the protecting layers 33 a and 33 b are processed under the same processing condition. Therefore, the tapered shape of the holes 55 a to 55 d will not change at the interface between the protecting layers 33 a and 33 b and the shape of the contact plug layers 53 a to 53 d will not deform.
  • FIG. 22( a ) is a perspective diagram showing a stairway portion STb of the nonvolatile semiconductor memory device according to the second embodiment.
  • FIG. 22( b ) is a perspective diagram showing a state obtained by peeling a protecting layer 33 d from FIG. 22( a ).
  • FIG. 22( c ) is a perspective diagram showing a state obtained by peeling a protecting layer 33 c from FIG. 22( b ).
  • Any components of the second embodiment that are the same as those of the first embodiment will be denoted by the same reference numerals and not be explained repeatedly.
  • the nonvolatile semiconductor memory device according to the second embodiment includes steps STb 1 to STb 8 (the stairway portion STb) arranged in a matrix formation in the row and column directions, and protecting layers 33 c and 33 d that cover the steps STb 1 to STb 8 , as shown in FIG. 22 .
  • the second embodiment differs from the first embodiment in this point.
  • the memory transistor layer 30 includes word line conductive layers 31 Ba to 31 Bh and insulating layers 32 Ba to 32 Bh, which are stacked alternately.
  • the word line conductive layers 31 Ba to 31 Bh and the insulating layers 32 Ba to 32 Bh are provided memory block MB by memory block MB, and spread two-dimensionally (like a plate) in the row and column directions.
  • the word line conductive layers 31 Ba to 31 Bh and the insulating layers 32 Ba to 32 Bh are formed stepwise such that their row-direction and column-direction ends are located at different positions. That is, the row-direction and column-direction ends of the word line conductive layers 31 Ba to 31 Bh and insulating layers 32 Ba to 32 Bh constitute a stairway portion STb that is formed like a staircase.
  • the stairway portion STb includes steps (stages) STb 1 to STb 8 , which are arranged in a matrix formation in the row and column directions.
  • the steps STb 1 to STb 8 are located in a matrix formation that has three rows and three columns.
  • the step STb 1 is located at a position on the second row and the first column.
  • the step STb 2 is located at a position on the third row and the first column.
  • the step STb 3 is located at a position on the first row and the second column.
  • the step STb 4 is located at a position on the second row and the second column.
  • the step STb 5 is located at a position on the third row and the second column.
  • the step STb 6 is located at a position on the first row and the third column.
  • the step STb 7 is located at a position on the second row and the third column.
  • the step STb 8 is located at a position on the third row and the third column.
  • the steps STb 1 to STb 8 are located in lower layers to upper layers sequentially.
  • Each of the steps STb 1 to STb 8 has a stacked structure of one of the word line conductive layers 31 Ba to 31 Bh and one of the insulating layers 32 Ba to 32 Bh.
  • the memory transistor layer 30 also has protecting layers 33 c and 33 d that cover the word line conductive layers 31 Ba to 31 Bh and the insulating layers 32 Ba to 32 Bh, as shown in FIGS. 22( a ) and ( b ).
  • the protecting layer 33 c covers side surfaces of column-direction and row-direction ends of the steps STb 6 to STb 8 .
  • the protecting layer 33 c covers side surfaces of row-direction ends of the steps STb 3 to STb 5 .
  • the protecting layer 33 c also covers top surfaces of the steps STb 3 to STb 8 .
  • the protecting layer 33 d covers the protecting layer 33 c .
  • the protecting layer 33 d covers side surfaces of column-direction ends of the steps STb 1 to STb 5 .
  • the protecting layer 33 d covers side surfaces of row-direction ends of the steps STb 1 and STb 2 .
  • the protecting layer 33 d also covers top surfaces of the steps STb 1 and STb 2 .
  • a plurality of steps STb 3 to STb 8 (first portion), which are located on the second and third columns, are covered with two protecting layers 33 c and 33 d
  • a plurality of steps STb 1 and STb 2 (second portion located at a lower level than the first portion), which are located on the first column, are covered with one protecting layer 33 d .
  • the protecting layer 33 c is not formed on the top surface of the steps STb 1 and STb 2 .
  • contact plug layers are formed on the top surface of the word line conductive layers 31 Ba to 31 Bh in the respective steps STb 1 to STb 8 , similarly to the first embodiment.
  • FIG. 23 to FIG. 28 are schematic perspective diagrams showing the process of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
  • polysilicon (p-Si) and silicon oxide (SiO 2 ) are alternately deposited to form layers 31 Ca to 31 Ch and layers 32 Ca to 32 Ch.
  • the layers 31 Ca to 31 Ch will later be processed into the word line conductive layers 31 Ba to 31 Bh
  • the layers 32 Ca to 32 Ch will later be processed into the insulating layers 32 Ba to 32 Bh.
  • a resist layer 91 Ba is formed. Then, as shown in FIG. 24 , slimming of the resist layer 91 Ba in the row direction and etching are repeatedly carried out. As a result, three rows of steps STc 1 to STc 3 are formed at equal intervals in the row direction.
  • the step STc 1 is constituted by row-direction end portions of the layers 31 Ca to 31 Cf and layers 32 Ca to 32 Cf.
  • the step STc 2 is constituted by row-direction end portions of the layer 31 Cg and layer 32 Cg.
  • the step STc 3 is constituted by row-direction end portions of the layer 31 Ch and layer 32 ch.
  • the lower step STd 1 is formed to have a larger width in the column direction than that of the upper step STd 2 .
  • the step STd 1 is constituted by column-direction end portions of the layers 31 Ca to 31 Ce and layers 32 Ca to 32 Ce.
  • the step STd 2 is constituted by column-direction end portions of the layers 31 Cd to 31 Ch and layers 32 Cd to 32 Ch.
  • a resist layer 91 Bc is formed.
  • the resist layer 91 Bc is formed to cover the protecting layer 33 c on the step STd 2 and the protecting layer 33 c on a partial region of the step STd 1 .
  • step STe etching by using the resist layer 91 Bc as a mask is carried out to form a step STe.
  • the step STe is constituted by column-direction end portions of the layers 31 Ca and 31 Cb and layers 32 Ca and 32 Cb.
  • the protecting layer 33 c is divided along a boundary between the column-direction step STe and step STd 1 .
  • the resist layer 91 Bc is removed as shown in FIG. 22( b ), and the protecting layer 33 d is formed as shown in FIG. 22( a ).
  • An interlayer insulating layer is formed on the protecting layer 33 d , and contact plug layers are formed to penetrate the interlayer insulating layer.
  • the nonvolatile semiconductor memory device has a configuration similar to that of the first embodiment, and achieves advantages similar to that of the first embodiment. Furthermore, the second embodiment includes the steps STb 1 to STb 8 that are arranged in the matrix formation. Therefore, the second embodiment can make an area occupied by the contact plug layers smaller than in the first embodiment.
  • FIG. 29 is a cross section showing the nonvolatile semiconductor memory device according to the third embodiment. Any components of the third embodiment that are the same as those of the first embodiment will be denoted by the same reference numerals and not be explained repeatedly.
  • the memory columnar semiconductor layer 36 is formed in the shape of a letter “I” that extends in the stacking direction when seen in the row direction.
  • a memory columnar semiconductor layer 36 D according to the third embodiment is formed in the shape of a letter “U” when seen in the row direction, as shown in FIG. 29 . That is, the memory columnar semiconductor layer 36 D has a pair of columnar portions 36 Da that extend in the stacking direction and a joining portion 36 Db that joins the bottom ends of the pair of columnar portions 36 Da.
  • Word line conductive layers 31 Da to 31 Dd and insulating layers 32 Da to 32 Dd are formed as stripes that extend in the row direction with a predetermined pitch between them in the column direction, and are formed to surround the columnar portions 36 Da via a memory gate insulating layer 35 D.
  • the third embodiment includes a back gate conductive layer 37 D that is formed to surround the joining portion 36 Db via the memory gate insulating layer 35 D.
  • the back gate conductive layer 37 D is made of polysilicon.
  • a source-side columnar semiconductor layer 26 D is formed to extend in the stacking direction from a top surface of one of the pair of columnar portions 36 Da, and a drain-side columnar semiconductor layer 45 D is formed to extend in the stacking direction from a top surface of the other columnar portion 36 Da.
  • a source-side conductive layer 22 D and a drain-side conductive layer 41 D are formed as stripes that extend in the row direction with a predetermined pitch between them in the column direction.
  • the source-side conductive layer 22 D is formed to surround the source-side columnar semiconductor layer 26 D via a source-side gate insulating layer 25 D, and the drain-side conductive layer 41 D is formed to surround the drain-side columnar semiconductor layer 45 D via a drain-side gate insulating layer 44 D.
  • a top surface of the source-side columnar semiconductor layer 260 is connected to a third wiring layer 57 D.
  • the third wiring layer 57 D functions as a source line SL.
  • a top surface of the drain-side columnar semiconductor layer 45 D is connected to a first wiring layer 51 D (bit line BL) via a plug layer 58 D.
  • the word line conductive layers 31 Da to 31 Dd and the insulating layers 32 Da to 32 Dd constitute a stairway portion ST (steps ST 1 to ST 4 ) at their row-direction ends.
  • the source-side conductive layer 22 D and the drain-side conductive layer 41 D constitute a step ST 5 at their row-direction end.
  • the protecting layers 33 a , 33 b , 42 a , and 42 b are formed on the steps ST 1 to ST 5 .
  • the nonvolatile semiconductor memory device has a configuration similar to that of the first embodiment, and achieves advantages similar to that of the first embodiment.
  • the nonvolatile semiconductor memory device may include n word line conductive layers 31 ( 1 ) to 31 ( n ) (where n is a natural number equal to or greater than 2) and m protecting layers 33 ( 1 ) to 33 ( m ) (where m is a natural number equal to or greater than 2). That is, a stairway portion STf may include n steps STf( 1 ) to STf(n).
  • steps STf(h) to STf(n) which are the h-th or higher-order steps as counted from the bottom (where h is a natural number equal to or greater than 2 and equal to or smaller than n), have their top surface covered with the m protecting layers 33 ( 1 ) to 33 ( m ).
  • steps STf( 1 ) to STf(h ⁇ 1) which are the (h ⁇ 1) th or lower-order steps as counted from the bottom, have their top surface covered with m′ protecting layers 33 ( 1 ) to 33 ( m ′) (where m′ is a natural number smaller than m).
  • a process of manufacturing the configuration shown in FIG. 30 will be as follows. First, n conductive layers (word line conductive layers 31 ( 1 ) to 31 ( n )) are stacked. Then, memory holes 34 are formed to penetrate the conductive layers, and a memory gate insulating layer 35 and a memory columnar semiconductor layer 36 are formed in the memory holes 34 . Then, the topmost conductive layer and the (n-h+1)th or higher-order layers as counted downward from the topmost conductive layer are processed such that their ends are located at different positions, thereby forming a first stairway portion. Then, the protecting layers 33 ( 1 ) to 33 ( m ′) are formed to cover the first stairway portion.
  • the protecting layers 33 ( 1 ) to 33 ( m ′) are divided, and the conductive layers under the (n-h+1)th layer counted downward from the topmost layer are processed such that the ends of the plurality of conductive layers are located at different positions, thereby forming a second stairway portion. Then, the protecting layers 33 ( m - m ′) to 33 ( m ) are formed to cover the protecting layers and the second stairway portion.
  • the row-direction length L 0 of the step ST 3 of the first embodiment is determined by lengths L 1 to L 4 as shown in FIG. 31 .
  • the length L 1 corresponds to the total thickness of the two protecting layers 33 a and 33 b on the side surface of the step ST 4 .
  • the length L 2 is the length from the protecting layer 33 b on the side surface of the step ST 4 to the side surface of the contact plug layer 53 c .
  • the length L 2 is necessary in order for the contact plug layer 53 c not to contact the protecting layers 33 a and 33 b .
  • the length L 3 corresponds to the diameter of the bottom end of the contact plug layer 53 c .
  • the length L 4 is the length from the side surface of the contact plug layer 53 c to the end of the step ST 3 .
  • the length L 4 is necessary in order for the contact plug layer 53 c not to fall down to the step ST 2 .
  • the length L 4 needs to be defined in consideration of the variation of the end position of the step ST 3 in the manufacturing process.
  • all of the protecting layers 33 a and 33 b , the protecting layers 42 a and 42 b , and the protecting layers 33 c and 33 d are made of silicon nitride.
  • the protecting layers 33 a , 42 a and 33 c may be made of silicon nitride and the protecting layers 33 b , 42 b , and 33 d may be made of alumina.
  • the total film thickness of the protecting layer 33 a made of silicon nitride and the protecting layer 33 b made of alumina can be smaller than the total film thickness of the protecting layer 33 a made of silicon nitride and the protecting layer 33 b made of silicon nitride. That is, in the above-described modified example, the length L 1 shown in FIG. 31 can be made shorter. Accordingly, the length L 0 of the step can be made shorter, and hence the area occupied by the nonvolatile semiconductor memory device can be made smaller.
  • the protecting layers 33 a , 42 a , and 33 c may be made of alumina and the protecting layers 33 b , 42 b , and 33 d may be made of silicon nitride.

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