US7429538B2 - Manufacturing method for two-step post nitridation annealing of plasma nitrided gate dielectric - Google Patents

Manufacturing method for two-step post nitridation annealing of plasma nitrided gate dielectric Download PDF

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US7429538B2
US7429538B2 US11/167,526 US16752605A US7429538B2 US 7429538 B2 US7429538 B2 US 7429538B2 US 16752605 A US16752605 A US 16752605A US 7429538 B2 US7429538 B2 US 7429538B2
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silicon oxynitride
film
oxygen
partial pressure
annealing
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Christopher S. Olsen
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Applied Materials Inc
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Priority to US11/167,526 priority Critical patent/US7429538B2/en
Priority to KR1020077031042A priority patent/KR100993124B1/ko
Priority to JP2008518181A priority patent/JP5072837B2/ja
Priority to PCT/US2006/020508 priority patent/WO2007001709A2/en
Priority to CN2006800229813A priority patent/CN101208782B/zh
Priority to TW095119255A priority patent/TWI343604B/zh
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
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    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
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    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
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    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3145—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers formed by deposition from a gas or vapour
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Definitions

  • Embodiments of the present invention generally relate to the field of semiconductor manufacturing. More specifically, the present invention relates to a method of forming a silicon oxynitride (SiO x N y ) gate dielectric and integrating it into a gate stack using plasma nitridation and a two-step post plasma nitridation annealing (PNA) process.
  • SiO x N y silicon oxynitride
  • PNA post plasma nitridation annealing
  • Integrated circuits are made up of literally millions of active and passive devices that function as basic components such as transistors, capacitors and resistors.
  • a transistor generally includes a source, a drain, and a gate stack.
  • the gate stack consists of the substrate (silicon) on top of which is grown a dielectric (usually silicon dioxide: SiO 2 ) and this is capped with an electrode (such as polycrystalline silicon).
  • SiO 2 gate dielectrics below 20 ⁇ .
  • boron from a boron doped gate electrode can penetrate through a thin SiO 2 gate dielectric into the underlying silicon substrate.
  • gate leakage i.e., tunneling
  • Thin SiO 2 gate dielectrics may be susceptible to hot carrier damage, in which high energy carriers traveling across the dielectric can damage or destroy the gate.
  • Thin SiO 2 gate dielectrics may also be susceptible to negative bias temperature instability (NBTI), wherein the threshold voltage or drive current drifts with operation of the gate.
  • NBTI negative bias temperature instability
  • the alternative gate dielectric material must have a dielectric constant that is higher than that of silicon dioxide.
  • the thickness of such an alternative dielectric material layer is expressed in terms of the equivalent oxide thickness (EOT).
  • EOT equivalent oxide thickness
  • One method that has been used to address the problems with thin SiO 2 gate dielectrics is to incorporate nitrogen into the SiO 2 layer to form a SiO x N y gate dielectric. Incorporating nitrogen into the SiO 2 layer blocks boron penetration into the underlying silicon substrate and raises the dielectric constant of the gate dielectric, allowing the use of a thicker dielectric layer.
  • Thermally grown silicon oxynitride has been used as gate dielectrics for several years from the 0.2 ⁇ m to 0.13 ⁇ m device generations. As the device technology has advanced from 0.2 ⁇ m to 0.1 ⁇ m the gate oxide has thinned from >25 ⁇ to ⁇ 12 ⁇ . In order to block boron and reduce gate leakage the amount of nitrogen in the film has been increased from ⁇ 3% for 25 ⁇ SiO x N y layers to 5-10% for 12 ⁇ SiO x N y layers.
  • nitric oxide (NO) and nitrous oxide (N 2 O) are used to grow the oxynitride gate dielectric the nitrogen gets incorporated in the dielectric film simultaneously as the oxynitride grows, hence nitrogen is distributed evenly in the film.
  • NO or N 2 O are used to form silicon oxynitride by annealing an existing SiO 2 layer at elevated temperatures, the nitrogen is incorporated by growing SiON at the Si-substrate/Oxide interface.
  • the amount of Nitrogen in the latter case ( ⁇ 2%) is less than in the former case (4-5%).
  • PN plasma nitridation
  • This technique results in high nitrogen concentration at the poly gate/oxide interface, which prevents boron penetration into the oxide dielectric.
  • the bulk of the oxide dielectric gets lightly doped with unassociated nitrogen during the plasma nitridation process, which reduces the electrical oxide thickness (EOT) over the starting oxide. This allows one to achieve a gate leakage reduction at the same EOT higher than conventional thermal processes. Scaling this dielectric in the EOT ⁇ 12 ⁇ range while preserving good channel mobility and drive current (Idsat) has been the industry challenge.
  • SiO 2 At low pressure and high temperature, SiO 2 will breakdown into SiO which desorbs from the silicon surface resulting in a phenomenon called pitting.
  • a gate electrode is deposited on the silicon oxynitride film after the two-step post plasma annealing.
  • the gate electrode comprises a polysilicon film.
  • the gate electrode comprises an amorphous silicon film.
  • the gate electrode comprises a metal electrode.
  • Embodiments of the invention also provide a method of forming a SiO x N y gate dielectric in an integrated processing system.
  • a silicon substrate is introduced into a first processing chamber of the integrated processing system where a silicon dioxide film is formed on the substrate.
  • the substrate is transferred to a second processing chamber of the integrated processing system where the substrate is exposed to a plasma comprising a nitrogen source.
  • the substrate is then transferred to a third processing chamber of the integrated processing system where the substrate is subjected to a two-step post plasma anneal.
  • the first step involves annealing the silicon oxynitirde film in a first ambient comprising an inert ambient with a first partial pressure of oxygen at a first temperature.
  • the second step involves annealing the silicon oxynitride film in a second ambient comprising a second partial pressure of oxygen at a second temperature wherein the second partial pressure of oxygen is greater than the first partial pressure of oxygen.
  • the plasma nitridation process includes decoupled plasma nitridation.
  • a SiO x N y gate dielectric is formed by a method comprising heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH 3 to incorporate nitrogen into the silicon oxide film, and then exposing the structure to a plasma comprising a nitrogen source to form a SiO x N y gate dielectric on the substrate.
  • FIG. 1 is a top schematic view of an integrated processing system.
  • FIG. 2 is a flow chart depicting an embodiment of the invention.
  • FIG. 3 illustrates an exemplary sequence of forming a gate stack in accordance with the embodiments of the present invention.
  • FIG. 4 is a graph showing Negative Channel Metal Oxide Semiconductor (NMOS) drive current relative to NMOS gate leakage for gate stacks comprising SiO x N y gate dielectrics.
  • NMOS Negative Channel Metal Oxide Semiconductor
  • Embodiments of the invention include a method of forming a dielectric that includes nitrogen, such as SiON or SiO x N y (silicon oxynitride) using a nitrogen plasma (or plasma nitridation) process.
  • the silicon oxynitride is then subjected to a two-step post plasma nitridation annealing processes.
  • the embodiments allow for the control of the EOT and the nitrogen concentration profile of the silicon oxynitride film.
  • a method of forming a silicon oxynitride dielectric film using a plasma nitridation process such as Decoupled Plasma Nitridation (DPN).
  • a plasma nitridation process such as Decoupled Plasma Nitridation (DPN).
  • the silicon oxynitride is subjected to a two-step post plasma nitridation annealing (PNA) process.
  • a first PNA step is performed using an inert agent in combination with a trace amount of oxygen to densify the silicon oxynitride.
  • a second PNA step is performed with an oxidizing agent to modify the nitrogen concentration profile.
  • the two-step PNA process moves nitrogen towards the surface of the silicon oxynitride and the substrate thus blocking Boron more efficiently.
  • the concentration profile of nitrogen tends to peak at the surface of the silicon oxynitride.
  • a method of integrating the silicon oxynitride film formed using a plasma nitridation process followed by a two-step PNA process into a gate stack for forming a semiconductor device such as a transistor in another embodiment, there is provided a method of integrating the silicon oxynitride film formed using a plasma nitridation process followed by a two-step PNA process into a gate stack for forming a semiconductor device such as a transistor.
  • a substrate having a silicon dioxide film formed thereon is subjected to a plasma nitridation process to convert the silicon dioxide film into silicon oxynitride film.
  • the plasma nitridation process used is Decoupled Plasma Nitridation (DPN), which is known in the art.
  • DPN is a technology using inductive coupling to generate nitrogen plasma and incorporate a high level of nitrogen into an oxide film.
  • a surface film e.g., an SiO 2 film, is bombarded with nitrogen ions which break the SiO 2 film forming a silicon oxynitride film.
  • DPN is performed in a chamber with pressure ranging from about 5-20 mTorr or 10-20 mTorr, with a plasma power of 200-800 Watt.
  • the nitrogen gas may be flown into the chamber at a flow rate ranging from about 100-200 sccm.
  • the DPN uses a pulse radio frequency plasma process at about 10-20 MHz and pulse at about 5-15 kHz.
  • the DPN process parameters can be modified depending on the chamber size and volume, and the desired thickness of the dielectric film.
  • Decoupled Plasma Nitridation chamber Other details of the Decoupled Plasma Nitridation chamber are described in U.S. Patent Application Publication No. 2004/0242021, entitled “Method And Apparatus For Plasma Nitridation Of Gate Dielectrics Using Amplitude Modulated Radio Frequency Energy,” assigned to Applied Materials, Inc., and herein incorporated by reference to the extent not inconsistent with the invention.
  • suitable DPN chambers include the DPN CenturaTM, which is commercially available from Applied Materials, Inc., Santa Clara, Calif.
  • the silicon oxynitride film is annealed twice.
  • the silicon oxynitride is annealed to density the nitrogen concentration.
  • the first annealing step is carried out in an inert ambient, using an inert gas such as N 2 , He, Ar, or a combination thereof combined with a trace amount of oxygen.
  • the first annealing step is carried out immediately after the plasma nitridation process.
  • the first PNA step is performed at a temperature between about 700° C. and about 1100° C., such as a temperature between about 950° C. and 1100° C.
  • the second PNA step follows the first PNA step.
  • the annealing ambient is changed over to one which contains an oxidizing agent (or an oxygen comprising agent) such as O 2 , O 2 /N 2 , O 2 /Ar, O 2 /He, N 2 O, or NO.
  • the second PNA step is carried out at reduced pressure ranging from about 10 mTorr to about 100 Torr and at a temperature between about 900° C. and about 1100° C. or between about 1000° C. and 1050° C.
  • the second PNA step can be carried out for about 1-120 seconds.
  • the temperature, time, and pressure of the second PNA step are controlled to achieve a 0.1 ⁇ to 2 ⁇ increase in the EOT of the silicon oxynitride.
  • both the first PNA step and the second PNA step are performed in a single wafer rapid thermal processing (RTP) chamber configured to carry out the rapid thermal annealing (RTA) process.
  • RTP rapid thermal processing
  • a commercially available reduced pressure (RTP) chamber hardware such as XE, XE Plus or Radiance made by Applied Materials, Inc. can be used to carry out the first and second PNA processes.
  • the SiO x N y gate dielectric described herein comprises at least 5 atomic percent nitrogen.
  • the SiO x N y gate dielectric comprises between about 5 atomic percent nitrogen and about 15 atomic percent nitrogen.
  • a gate electrode such as a polysilicon layer, an amormphous silicon layer, or a metal layer may be deposited on the SiO x N y gate dielectric to complete a gate stack.
  • a SiO x N y gate dielectric may be formed on a substrate in an integrated processing system, such as an integrated semiconductor processing system, in a method in which the substrate is not removed from the integrated processing system until after the SiO x N y gate dielectric is formed.
  • an integrated processing system 100 that may be used is the Gate Stack Centura® system, available from Applied Materials, Inc. of Santa Clara, Calif., which is shown in FIG. 1 .
  • the integrated processing system 100 includes a central transfer chamber 102 , a transfer robot 103 , load locks 104 , 106 , a cool down chamber 108 , a deposition chamber 110 , a plasma processing chamber 114 , and two rapid thermal processing (RTP) chambers 116 and 118 .
  • the deposition chamber 110 can be a conventional chemical or physical vapor deposition that can be used to form a film or a layer as is know in the art.
  • CVD processing chamber 110 is a low pressure chemical vapor deposition chamber (LPCVD), such as a POLYgen chamber, available from Applied Materials.
  • the RTP chambers 116 and 118 are chambers that can run a rapid thermal annealing (RTA) process at a reduced or ultra-low pressure (e.g., about equal to or less than 10 Torr).
  • RTA rapid thermal annealing
  • a substrate is introduced into an integrated processing system and a silicon oxide film, a SiO x N y gate dielectric, and a gate electrode are deposited on the substrate without removing the substrate from the integrated processing system. This embodiment will be described below with respect to FIGS. 1 and 2 .
  • the processing conditions for embodiments in which the SiO x N y gate dielectric is formed in an integrated processing system are the same as the processing conditions described above for the formation of the silicon oxide film and the SiO x N y gate dielectric.
  • a silicon substrate is introduced into the integrated processing system 100 via a load lock 104 or 106 and placed in RTP chamber 116 , where a silicon oxide film is formed on the silicon substrate, as shown in steps 200 and 202 of FIG. 2 .
  • the structure, including the substrate and the silicon oxide film is then transferred to a plasma processing chamber 114 , where it is exposed to a plasma comprising a nitrogen source to incorporate nitrogen into the silicon oxide film and form the SiO x N y gate dielectric, as shown in steps 204 and 206 .
  • the structure is transferred to RTP chamber 116 as shown in step 208 where the structure is annealed, as shown in steps 210 and 212 .
  • the structure is then transferred to CVD processing chamber 110 , as shown in step 214 , and a gate electrode, such as a polysilicon layer or an amorphous silicon layer is deposited on the structure, as shown in step 216 .
  • the structure is then removed from the integrated processing system 100 via a load lock 104 or 106 .
  • the silicon oxide film is formed on the substrate in RTP chamber 116 in one step and the structure is annealed in RTP chamber 118 in another step.
  • a single RTP chamber is configured to form the silicon oxide film and to also perform the two-step post plasma anneal.
  • a structure comprising a silicon dioxide film on a silicon substrate is heated in an atmosphere comprising NH 3 in a first processing chamber of the integrated processing system to incorporate nitrogen into the silicon oxide film. Because the substrate is exposed to an atmosphere comprising NH 3 within an enclosed integrated processing system, contaminating oxygen is typically not incorporated into the structure during the heating in an atmosphere comprising NH 3 .
  • the structure is then transferred to a second processing chamber of the integrated processing system and exposed to a plasma comprising a nitrogen source in the second processing chamber. After exposing the structure to the plasma, the structure is transferred to a third processing chamber of the integrated processing system and annealed in the third processing chamber.
  • heating the structure in an atmosphere comprising NH 3 prior to treating the structure with a plasma comprising nitrogen smoothens the interface between the gate dielectric and the underlying silicon substrate, resulting in enhanced device performance and reliability. It is also believed that the formation of a slightly thicker oxide film by heating the structure first in an atmosphere comprising NH 3 prior to plasma treating the structure enhances the performance characteristics of a PMOS device.
  • FIG. 3 illustrates an exemplary sequence of forming a gate stack in accordance with embodiments of the present invention.
  • the substrate 302 can be a monocrystalline silicon or a semiconductor wafer typically used in making semiconductor devices.
  • the SiO 2 film 304 has a physical thickness of about 4-15 ⁇ .
  • the SiO 2 film 304 is grown using a reduced pressure RTP chamber such as the RTP chamber 116 of the integrated processing system 100 ( FIG. 1 ).
  • the SiO 2 film 304 is formed by a rapid thermal oxidation, which is an oxidation process where the chamber uses lamps to quickly heat and dry a substrate surface to form an oxidized layer in the presence of oxygen.
  • the rapid thermal oxidation of a silicon substrate (or a wafer) is carried out using a dry process rapid thermal oxidation with the presence of O 2 , O 2 +N 2 , O 2 +Ar, N 2 O, or N 2 O+N 2 gas mixtures.
  • the gas or gas mixtures can have a total flow rate of about 1-5 slm.
  • the rapid thermal oxidation of a silicon substrate is carried out using a wet process such as In-Situ Steam Generation (ISSG) with the presence of O 2 +H 2 , O 2 +H 2 +N 2 , or N 2 O+H 2 having, for example, a total flow rate of about 1-5 slm with 1-13% H 2 .
  • the rapid thermal oxidation process used to form the SiO 2 dielectric film is performed at a processing temperature of about 750-1000° C. and a processing pressure of about 0.5-50 Torr for about 5-90 seconds which results in an SiO 2 dielectric film having a thickness in the range of about 4-15 ⁇ .
  • the substrate 302 is transferred to the DPN chamber 114 of the integrated processing system 100 under an inert (e.g., N 2 or Ar) environment with the transfer chamber pressure being approximately at the same pressure for the plasma nitiridation process.
  • the plasma nitridation process exposes the SiO 2 film 304 to nitrogen plasma and incorporates nitrogen into the SiO 2 film 304 to form a silicon oxynitride film 304 .
  • the DPN chamber 114 is a reduced pressure inductively coupled RF plasma reactor that can accommodate an inert gas such as N 2 , He, or Ar.
  • the silicon oxynitride film 304 is then subjected to a two-step post nitridation anneal (PNA) process in an RTP chamber, e.g. the RTP chamber 118 of the integrated processing system 100 .
  • the RTP chamber 118 can be a reduced pressure chamber reactor such as an Applied Materials reactor XE, XE Plus, or Radiance.
  • the PNA occurs, first in a mild oxidizing ambient (inert ambient) to densify the nitrogen plasma treated film (the silicon oxynitride film 304 ) at a temperature of about equal to or greater than 700° C., followed by a second anneal in an oxidizing ambient at a temperature of about equal to or greater than 900° C.
  • an inert gas e.g., N 2 or Ar
  • a trace amount of O 2 is flown into the RTP chamber to densify the silicon oxynitride film 304 .
  • the first PNA includes heating up the substrate having the silicon oxynitride film 304 to the appropriate annealing temperature of about equal to or greater than 700° C. at less than or equal to about 5 Torr total pressure.
  • the inert gas such as N 2 gas of about 1 slm is flown into the RTP chamber for about 60-120 seconds and a trace amount of oxygen is flown into the chamber at a flow rate of about 30 sccm and a pressure of about 5 Torr.
  • the RTP chamber is evacuated of the inert gas and an oxidizing gas such as O 2 is flown into the RTP chamber for the second PNA.
  • the temperature may be changed to about or greater than 900° C.
  • the oxidizing gas is flown into the RTP chamber at about 1 slm total flow rate for about 15 seconds. It is to be appreciated that the flow rates mentioned are examples only for a particular reactor or process chamber size (e.g., a 200 mm reactor). The flow rates are proportionately adjusted (increased or decreased) for other size reactors owing to the difference in volume.
  • the silicon oxynitride film 304 is capped with a conductive layer such as a polysilicon film 306 .
  • the polysilicon film 306 can be formed in a deposition chamber such as the deposition chamber 110 of the integrated processing system 100 ( FIG. 1 ). Instead of polysilicon, the film 306 can be an amorphous silicon film or other suitable conductive material. Further, metals such as titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, and other refractory metals or other suitable electrode materials may be deposited thereover.
  • the deposition chamber 110 can be a low-pressure chemical vapor deposition chamber (LPCVD) that can be incorporated into the integrated processing system 100 .
  • LPCVD low-pressure chemical vapor deposition chamber
  • the gate stack is transferred to a cool down chamber 108 and then transferred to a storage area such as the load locks 104 and 106 for further processing, testing, or other processes known in the art.
  • the gate stack that includes the gate dielectric film and the polysilicon cap film can be formed in several processing chambers not necessarily incorporated into the integrated processing system 100 previously described.
  • the SiO 2 film can be formed first in one chamber.
  • the SiO 2 film can be converted into silicon oxynitride in a plasma nitridation chamber.
  • the silicon oxynitride chamber is then annealed in a two-step PNA process using an RTP chamber.
  • the polysilicon film is formed over a SiON or a SiO x N y film in the same RTP chamber.
  • a trace amount of oxygen in the first step of a two-step post anneal of silicon oxynitride improves NMOS drive current relative to NMOS gate leakage.
  • the x-axis represents NMOS gate leakage and the y-axis represents NMOS drive current.
  • a SiO 2 film of about 10 ⁇ is used as the base oxide.
  • various post-annealing conditions were used to anneal the film. For instance, a first step involving annealing at 1000° C. for 30 seconds at 15 mTorr partial pressure of oxygen in the presence of nitrogen gas is followed by a second step at 1000° C. for 15 seconds at 10 Torr of oxygen.
  • a first step involving annealing at 1000° C. for 15 seconds at 15 mTorr in the presence of nitrogen gas is followed by a second step at 1050° C. for 15 seconds at 1.5 Torr of oxygen.
  • a first step involving annealing at 1050° C. for 30 seconds at 15 mTorr in the presence of nitrogen gas is followed by a second step at 1050° C. for 15 seconds at 0.5 Torr.
  • a first step involving annealing at 1000° C. for 30 seconds at 0.015 mTorr in the presence of nitrogen gas is followed by a second step at 1100° C. for 5 seconds at 0.05 Torr.
  • the two-step post anneal containing a trace amount of oxygen in the first step exhibits a 4% improvement in NMOS ldsat over a two-step post anneal without a trace amount of oxygen in the first step.

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