US7012285B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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US7012285B2
US7012285B2 US10/416,261 US41626103A US7012285B2 US 7012285 B2 US7012285 B2 US 7012285B2 US 41626103 A US41626103 A US 41626103A US 7012285 B2 US7012285 B2 US 7012285B2
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gate
fet
voltage
electrode
semiconductor device
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US20040026742A1 (en
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Tadayoshi Nakatsuka
Toshiharu Tambo
Takahiro Kitazawa
Akiyoshi Tamura
Katsuyoshi Tara
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/095—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being Schottky barrier gate field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802—Resistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H01L27/0811—MIS diodes

Definitions

  • the present invention relates to semiconductor devices, for example, for amplifying or switching signals in mobile communication apparatuses and the like, in particular to MES (metal semiconductor) FETs.
  • MES metal semiconductor
  • FIG. 11A shows a cross-sectional view of the structure of a MESFET in the ON-state, formed on a GaAs semi-insulating substrate
  • FIG. 11B shows an equivalent circuit diagram corresponding to FIG. 11A
  • FIG. 11C shows a circuit diagram when the FET in FIG. 11A is switched
  • FIG. 12A shows a cross-sectional view of the structure in the OFF-state
  • FIG. 12B shows an equivalent circuit diagram corresponding to FIG. 12 A.
  • numeral 10 a denotes a source electrode.
  • Numeral 10 b denotes a drain electrode.
  • Numeral 11 a denotes a Schottky gate electrode.
  • Numeral 21 denotes a GaAs ohmic contact layer.
  • Numeral 22 denotes an AlGaAs undoped layer.
  • Numeral 23 denotes an AlGaAs active layer.
  • Numeral 24 denotes a buffer layer in which AlGaAs layers and GaAs layers are laminated alternately and numeral 25 denotes the GaAs semi-insulating semiconductor substrate.
  • numeral 27 a denotes a depletion layer.
  • Cgs_on indicates the gate-source capacitance in the ON-state.
  • Cgd_on indicates the gate-drain capacitance in the ON-state.
  • Cds_on indicates the drain-source capacitance in the ON-state.
  • Rch indicates the channel resistance in the ON-state.
  • Rc 1 indicates the contact resistance between the source electrode 10 a and the ohmic contact layer 21 .
  • Rc 2 indicates the contact resistance between the drain electrode 10 b and the ohmic contact layer 21 .
  • Rin 1 indicates the resistance component existing between the source and the gate other than Rch and Rin 2 indicates the resistance component existing between the drain and the gate other than Rch.
  • numeral 30 a denotes the FET.
  • Numerals 40 a, 40 b and 41 a denotes bias resistances.
  • Numeral 50 denotes an input terminal.
  • Numeral 51 denotes an output terminal.
  • Numeral 52 denotes a drain-source bias terminal and numeral 53 denotes a gate bias terminal.
  • FIG. 12A shows a cross-sectional view of the structure of the FET 30 a in the OFF-state.
  • FIG. 12A is different from FIG. 11A in that Cgs_off indicates the gate-source capacitance in the OFF-state, Cgd_off indicates the gate-drain capacitance in the OFF-state and Cds_off indicates the drain-source capacitance in the OFF-state and that Rch is so high that it is negligible in the equivalent circuit.
  • the gate width of the FET 30 a shown in the conventional example is 1 mm and the gate electrode 11 a has a gate length of 0.5 ⁇ m.
  • a standard value of Rch is 1.0 ⁇ /mm.
  • a voltage of 0 V is applied to the drain-source bias terminal 52 and a voltage of 0V or a positive voltage not higher than the Schottky barrier potential (about 0.7 V) is applied to the gate bias terminal 53 .
  • the FET 30 a becomes forward biased and is turned on between the drain and the source.
  • the channel of the FET 30 a is opened and transmission of signals becomes possible, so that signals can be transmitted from a point A to a point B.
  • the equivalent circuit for a region underneath the gate of the FET can be represented by a circuit in which a series capacitance of Cgs_on and Cgd_on is connected in parallel with Cds_on and Rch.
  • the impedance of Rch is much lower than those of the capacitance components and is dominant.
  • the on-resistance (Ron) that indicates the sum of the resistance components within the FET in the ON-state is about 1.5 ⁇ .
  • the insertion loss which represents the characteristics of a switching circuit in the ON-state, is proportional to Ron.
  • Ron the resistance components constituting Ron, Rch is most dominant, so that it is effective to decrease Rch in order to reduce the insertion loss.
  • Cgs_on, Cgd_on and Cds_on but also Cgs_off, Cgd_off and Cds_off, which are the capacitances in the OFF-state, become higher.
  • FIG. 12A in order to turn off the FET, the gate-source potential is set to the threshold potential of the FET or less, while keeping the potentials at the drain terminal and the source terminal unchanged. Thus, the channel of the FET closes and the FET is turned off.
  • FIG. 12B shows the equivalent circuit of the FET in the OFF-state, from which it can be understood that a parallel capacitance of the series capacitance of Cgs_off and Cgd_off, and Cds_off is dominant in the OFF-state.
  • the sum of the above-mentioned capacitances is about 0.1 pF.
  • Isolation characteristics which indicate the characteristics of the switching circuit in the OFF-state, represent the leakage of signals from input to output, and as the capacitance components between input and output increase, the isolation characteristics deteriorate.
  • the present invention solves the above-mentioned problems and it is an object thereof to provide a semiconductor device whose insertion loss is reduced and isolation characteristics are improved by reducing the capacitance component when an FET is off.
  • a first semiconductor device includes a field effect transistor (FET) having a gate electrode with a gate length of not more than 0.8 ⁇ m formed on a semiconductor substrate in which a buffer layer having an impurity concentration of at least 10 10 cm ⁇ 3 and at most 10 14 cm ⁇ 3 is formed on a semi-insulating semiconductor having at least 10 14 cm ⁇ 3 and at most 10 16 cm ⁇ 3 p-type or n-type impurities, and at least one active layer having a p-type or n-type impurity concentration of at least 10 15 cm ⁇ 3 and at most 10 17 cm ⁇ 3 is formed on the buffer layer.
  • FET field effect transistor
  • N FETs are combined with each other, and when 1 ⁇ m ⁇ n ⁇ 1 (n and m are integers, n>1), a drain terminal of the m-th FET is connected to a source terminal of the (m+1)th FET, resistors are connected to the gate electrodes of all of the first to n-th FETs, and all of the other ends of the resistors are coupled to the same electric potential.
  • the reason that the impurity concentration in the semi-insulating semiconductor is set within a range of at least 10 14 cm ⁇ 3 and at most 10 16 cm ⁇ 3 is that sufficient functionality cannot be obtained when the impurity concentration is lower than 10 14 cm ⁇ 3 or higher than 10 16 cm ⁇ 3 .
  • the reason that the impurity concentration in the buffer layer is set within a range of at least 10 10 cm ⁇ 3 and at most 10 14 cm ⁇ 3 is that sufficient functionality as a buffer layer cannot be obtained when the impurity concentration is lower than 10 10 cm ⁇ 3 or higher than 10 14 cm ⁇ 3 .
  • the reason that the impurity concentration in the active layer is set within a range of at least 10 15 cm ⁇ 3 and at most 10 17 cm ⁇ 3 is that sufficient functionality as an active layer cannot be obtained when the impurity concentration is lower than 10 15 cm ⁇ 3 or higher than 10 17 cm ⁇ 3 .
  • the gate-drain capacitance value of the first FET is set to not more than 2 ⁇ 3 of the gate-source capacitance value of the first FET
  • the gate-source capacitance value of the n-th FET is set to not more than 2 ⁇ 3 of the gate-drain capacitance value of the n-th FET
  • the gate-source capacitance values and the gate-drain capacitance values of the second to (n ⁇ 1)th FETs are set to not more than 2 ⁇ 3 of the gate-source capacitance value of the first FET or the gate-drain capacitance value of the n-th FET.
  • the reason that the capacitance ratio between each of the electrodes is set to not more than 2 ⁇ 3 is that when it is greater than 2 ⁇ 3, the increment of the insertion loss due to the increase in the resistance value exceeds the insertion loss reduction effect due to the reduction in the capacitance, so that a sufficient effect cannot be obtained.
  • the first semiconductor device it is preferable that an electrode is formed on the buffer layer and any voltage between the first voltage as an upper limit and the second voltage as a lower limit is applied to the electrode.
  • the first voltage and the second voltage respectively indicate a high value and a low value of the control voltage of a switching circuit.
  • any voltage between the first voltage as an upper limit and the second voltage as a lower limit is applied to a connection point between the drain terminal of the m-th FET and the source terminal of the (m+1)th FET.
  • the first voltage and the second voltage respectively indicate a high value and a low value of the control voltage of a switching circuit.
  • a second semiconductor device includes a multi-gate FET having n (n>1) gate electrodes, each with a gate length of not more than 0.8 ⁇ m, formed on a semiconductor substrate in which a buffer layer having an impurity concentration of at least 10 10 cm ⁇ 3 and at most 10 14 cm ⁇ 3 is formed on a semi-insulating semiconductor having at least 10 14 cm ⁇ 3 and at most 10 16 cm ⁇ 3 p-type or n-type impurities, and at least one active layer having a p-type or n-type impurity concentration of at least 10 15 cm ⁇ 3 and at most 10 17 cm ⁇ 3 is formed on the buffer layer.
  • Resistors are connected to all of the first to n-th gate electrodes, and all of the other ends of the resistors are coupled to the same electric potential.
  • the first gate-drain capacitance value is set to not more than 2 ⁇ 3 of the first gate-source capacitance value and the n-th gate-source capacitance value is set to not more than 2 ⁇ 3 of the n-th gate-drain capacitance value.
  • the reason that the capacitance ratio between each of the electrodes is set to not more than 2 ⁇ 3 is that when it is greater than 2 ⁇ 3, the increment of the insertion loss due to the increase in the resistance value exceeds the insertion loss reduction effect due to the reduction in the capacitance, so that a sufficient effect cannot be obtained.
  • the second semiconductor device it is preferable that an electrode is formed on the buffer layer and any voltage between the first voltage as an upper limit and the second voltage as a lower limit is applied to the electrode.
  • the first voltage and the second voltage respectively indicate a high value and a low value of the control voltage of a switching circuit.
  • an electrode is provided in a region on the active layer between the m-th gate electrode and the (m+1)th gate electrode, and any voltage between the first voltage as an upper limit and the second voltage as a lower limit is applied to the electrode.
  • the first voltage and the second voltage respectively indicate a high value and a low value of the control voltage to a switching circuit.
  • the buffer layer is formed by laminating two or more layers of different kinds of semiconductors, an electrode is formed on any of the layers of the buffer layer, and any voltage between a first voltage as an upper limit and a second voltage as a lower limit is applied to the electrode.
  • the first voltage and the second voltage indicate a high value and a low value of the control voltage to a switching circuit, respectively.
  • FIG. 1A is a cross-sectional view of the structure of a MESFET, which is a semiconductor device according to Embodiment 1 of the present invention, in the ON-state.
  • FIG. 1B is an equivalent circuit diagram corresponding to FIG. 1 A.
  • FIG. 1C is a circuit diagram when the FET in FIG. 1A is switched.
  • FIG. 2A is a cross-sectional view of the structure of the MESFET, which is the semiconductor device according to Embodiment 1 of the present invention, in the OFF-state.
  • FIG. 2B is an equivalent circuit diagram corresponding to FIG. 2 A.
  • FIG. 3A is a cross-sectional view of the structure of MESFET, which is a semiconductor device according to Embodiment 2 of the present invention, in the ON-state.
  • FIG. 3B is an equivalent circuit diagram corresponding to FIG. 3 A.
  • FIG. 3C is a circuit diagram when the FET in FIG. 3A is switched.
  • FIG. 4A is a cross-sectional view of the structure of the MESFET, which is the semiconductor device according to Embodiment 2 of the present invention, in the OFF-state.
  • FIG. 4B is an equivalent circuit diagram corresponding to FIG. 4 A.
  • FIG. 5A is a cross-sectional view of the structure of a MESFET, which is a semiconductor device according to Embodiment 3 of the present invention, in the ON-state.
  • FIG. 5B is an equivalent circuit diagram corresponding to FIG. 5 A.
  • FIG. 5C is a circuit diagram when the FET in FIG. 5A is switched.
  • FIG. 6A is a cross-sectional view of the structure of the MESFET, which is the semiconductor device according to Embodiment 3 of the present invention, in the OFF-state.
  • FIG. 6B is an equivalent circuit diagram corresponding to FIG. 6 A.
  • FIG. 7A is a cross-sectional view of the structure of a dual-gate MESFET, which is a semiconductor device according to Embodiment 4 of the present invention, in the ON-state.
  • FIG. 7B is an equivalent circuit diagram corresponding to FIG. 7 A.
  • FIG. 7C is a circuit diagram when the FET in FIG. 7A is switched.
  • FIG. 8A is a cross-sectional view of the structure of the dual-gate MESFET, which is the semiconductor device according to Embodiment 4 of the present invention, in the OFF-state.
  • FIG. 8B is an equivalent circuit diagram corresponding to FIG. 8 A.
  • FIG. 9A is a cross-sectional view of the structure of a dual-gate MESFET, which is a semiconductor device according to Embodiment 5 of the present invention, in the ON-state.
  • FIG. 9B is an equivalent circuit diagram corresponding to FIG. 9 A.
  • FIG. 9C is a circuit diagram when the FET in FIG. 9A is switched.
  • FIG. 10A is a cross-sectional view of the structure of the dual-gate MESFET, which is the semiconductor device according to Embodiment 5 of the present invention, in the OFF-state.
  • FIG. 10B is an equivalent circuit diagram corresponding to FIG. 10 A.
  • FIG. 11A is a cross-sectional view of the structure of a conventional MESFET in the ON-state.
  • FIG. 11B is an equivalent circuit diagram corresponding to FIG. 11 A.
  • FIG. 11C is a circuit diagram when the FET in FIG. 11A is switched.
  • FIG. 12A is a cross-sectional view of the structure of the conventional MESFET in the OFF-state.
  • FIG. 12B is an equivalent circuit diagram corresponding to FIG. 12 A.
  • FIG. 13 is a diagram showing the frequency characteristics of the insertion losses in a conventional FET having a single-stage configuration and a FET having a two-stage configuration in accordance with the present invention.
  • FIG. 1A a MESFET that is a semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIG. 1A , FIG. 1B , FIG. 1C , FIG. 2 A and FIG. 2 B.
  • FIG. 1A shows a cross-sectional view of the structure of the MESFET in the ON-state, formed on a GaAs semi-insulating substrate.
  • FIG. 1B shows an equivalent circuit diagram corresponding to FIG. 1 A.
  • FIG. 1C shows a circuit diagram when the FET in FIG. 1A is switched.
  • FIG. 2A shows a cross-sectional view of the structure of the MESFET in the OFF-state and FIG. 2B shows an equivalent circuit diagram corresponding to FIG. 2 A.
  • numeral 10 a denotes a source electrode of an FET 30 a.
  • Numeral 10 b denotes a drain electrode of the FET 30 a and also a source electrode of an FET 30 b.
  • Numeral 11 a denotes a Schottky gate electrode of the FET 30 a.
  • Cgs 11 _on indicates the gate-source capacitance of the FET 30 a in the ON-state.
  • Cgd 11 _on indicates the gate-drain capacitance of the FET 30 a in the ON-state.
  • Cds 11 _on indicates the drain-source capacitance of the FET 30 a in the ON-state and Rch 1 indicates the channel resistance of the FET 30 a in the ON-state.
  • numeral 10 c denotes a drain electrode of the FET 30 b.
  • Numeral 11 b denotes a Schottky gate electrode of the FET 30 b.
  • Cgs 22 _on indicates the gate-source capacitance of the FET 30 b in the ON-state.
  • Cgd 22 _on indicates the gate-drain capacitance of the FET 30 b in the ON-state.
  • Cds 22 _on indicates the drain-source capacitance of the FET 30 b in the ON-state and Rch 2 indicates the channel resistance of the FET 30 b in the ON-state.
  • numeral 21 denotes a GaAs ohmic contact layer having a film thickness of 100 nm and an impurity density of 1.0 ⁇ 10 18 /cm ⁇ 3 .
  • Numeral 22 denotes an AlGaAs undoped layer having a film thickness of 20 nm and an impurity density of 1.0 ⁇ 10 16 /cm ⁇ 3 .
  • Numeral 23 denotes an AlGaAs active layer having a film thickness of 500 nm and an impurity density of 2.0 ⁇ 10 18 /cm ⁇ 3 .
  • Numeral 24 denotes a superlattice-structured buffer layer having an impurity density of 1.0 ⁇ 10 15 /cm ⁇ 3 in which five AlGaAs layers each with a film thickness of 5 nm and five GaAs layers each with a film thickness of 5 nm are laminated alternately
  • numeral 25 denotes a GaAs semi-insulating semiconductor substrate having a substrate thickness of 450 ⁇ m and an impurity density of 1.0 ⁇ 10 15 /cm ⁇ 3
  • numerals 27 a and 27 b denote depletion layers. Standard values of Rch 1 and Rch 2 are 1.0 ⁇ /mm. Both of the gate electrodes 11 a and 11 b have a gate length of 0.5 ⁇ m.
  • the FETs 30 a and 30 b share the active layer 23 . However, they are separated from the other FETs formed on the same semiconductor substrate by etching so as not to share the active layer 23 .
  • FIG. 2A is the cross-sectional view of the structure of the FET in the OFF-state.
  • the configuration of FIG. 2A is different from that of FIG. 1A in that Cgs 11 _off indicates the gate-source capacitance of the FET 30 a in the OFF-state, Cgd 11 _off indicates the gate-drain capacitance of the FET 30 a in the OFF-state, Cds 11 _off indicates the drain-source capacitance of the FET 30 a in the OFF-state, Cgs 22 _off indicates the gate-source capacitance of the FET 30 b in the OFF-state, Cgd 22 _off indicates the gate-drain capacitance of the FET 30 b in the OFF-state and Cds 22 _off indicates the drain-source capacitance of the FET 30 b in the OFF-state, and that Rch 1 and Rch 2 are so high that they are negligible in the equivalent circuit.
  • the FETs 30 a and 30 b are in the ON-state, that is to say, the case where signals are transmitted from a point A (in this case, the source terminal) to a point B (in this case, the drain terminal) will be described.
  • the source terminal and the drain terminal are set to 0 V and the gate terminal is set to 0.3 V.
  • a forward voltage of 0.3 V is applied between the gates and the drains, and the gates and the sources.
  • the channels of the respective FETs open sufficiently, so that signals can be transmitted from the point A to the point B.
  • the equivalent circuit for the region underneath the gate of the FET 30 a can be represented by a circuit in which a series capacitance of Cgs 11 _on and Cgd 11 _on is connected in parallel with Cds 11 _on and Rch 1 .
  • the impedance of Rch 1 is much lower than those of the capacitance components and is dominant.
  • the gate voltage is set to the threshold voltage or less, that is to ⁇ 3 V in this case, while keeping the potentials at the drain terminal and the source terminal at 0 V.
  • the channels of the FETs 30 a and 30 b close and both of the FETs are turned off.
  • the depletion layer 272 a on the electrode 10 b side of the gate 11 a and the depletion layer 271 b on the electrode 10 b side of the gate 11 b extend wider than the depletion layer 271 a on the 10 a side of the gate electrode 11 a and the depletion layer 272 b on the 10 c side of the gate 11 b, respectively.
  • Cgd 11 _off and Cgs 22 _off become smaller (2 ⁇ 3 or less) than Cgs 11 _off and Cgd 22 _off, respectively, so that the capacitance between A and B in the equivalent circuit of FIG. 2B can be decreased.
  • the capacitance value between A and B is 0.03 pF or lower, which is about 1 ⁇ 3 of that of the conventional configuration.
  • the frequency characteristics are improved because of the reduction of the capacitance value, and therefore, at a frequency at or above a critical point, the insertion loss becomes smaller when the number of stages of the FET is set to two.
  • the active layer is a uniform AlGaAs layer.
  • the same effect also can be obtained using a single heterostructure or a double heterostructure.
  • a superlattice structure is used as the buffer layer.
  • the same effect can be obtained using other structures.
  • FIG. 3A , FIG. 3B , FIG. 3C , FIG. 4 A and FIG. 4 B a MESFET that is a semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIG. 3A , FIG. 3B , FIG. 3C , FIG. 4 A and FIG. 4 B.
  • FIG. 3A shows a cross-sectional view of the structure of the MESFET in the ON-state formed on a GaAs semi-insulating substrate.
  • FIG. 3B shows an equivalent circuit diagram corresponding to FIG. 3 A.
  • FIG. 3C show a circuit diagram when the FET in FIG. 3A is switched.
  • FIG. 4A shows a cross-sectional view of the structure of the MESFET in the OFF-state and FIG. 4B shows an equivalent circuit diagram corresponding to FIG. 4 A.
  • Embodiment 2 is different from that of Embodiment 1 in that an ohmic electrode 12 for voltage application is connected to the buffer layer 24 .
  • the buffer layer 24 five layers, each of different kinds of semiconductors, are laminated. In this embodiment, two layers of the five layers are removed starting at the top layer, before the ohmic electrode 12 is connected.
  • the FETs 30 a and 30 b are in the ON-state, that is to say, the case where signals are transmitted from the point A (in this case, the source terminal) to point B (in this case, the drain terminal)
  • the source terminal and the drain terminal are set to 0 V and the gate terminal is set to 0.3 V.
  • a forward voltage of 0.3 V is applied between the gates and the drains, and the gates and the sources.
  • the channels of the respective FETs open sufficiently, so that signals can be transmitted from the point A to the point B.
  • a voltage of 0 V is applied to the ohmic electrode 12 for voltage application.
  • the equivalent circuit of the region underneath the gate of the FET 30 a can be represented by a circuit in which a series capacitance of Cgs 11 _on and Cgd 11 _on is connected in parallel with Cds 11 _on and Rch 1 .
  • the impedance of Rch 1 is much lower than those of the capacitance components and is dominant.
  • the resistance of the FETs 30 a and 30 b in the ON-state can be approximated by the sum of Rch 1 and Rch 2 , and the on-resistance becomes 1.5 ⁇ or lower by using the FET having a gate width of 2 mm.
  • the gate voltage is set to the threshold voltage or less, that is, to ⁇ 3 V in this case, while keeping the potentials at the drain terminal and the source terminal at 0 V.
  • the channels of the FETs 30 a and 30 b close and both of the FETs are turned off.
  • Cdg 11 _off and Cgs 22 _off can be decreased to such an extent that they are negligible. Therefore, in the OFF-state, Cds 12 _off becomes a dominant and the series capacitance component of the FET in the OFF-state can be reduced.
  • the value of Cds 12 _off is 0.02 pF, which is about 1 ⁇ 5 of that of the conventional configuration.
  • the ohmic electrode 12 for voltage application is formed on the buffer layer 24 .
  • the same effect also can be expected even when it is formed on the GaAs semi-insulating semiconductor substrate 25 .
  • an ohmic metal is used as the electrode for voltage application, the same effect also can be obtained with a Schottky junction metal.
  • FIG. 5A , FIG. 5B , FIG. 5C , FIG. 6 A and FIG. 6 B a MESFET that is a semiconductor device according to Embodiment 3 of the present invention will be described with reference to FIG. 5A , FIG. 5B , FIG. 5C , FIG. 6 A and FIG. 6 B.
  • FIG. 5A shows a cross-sectional view of the structure of the MESFET in the ON-state, formed on a GaAs semi-insulating substrate.
  • FIG. 5B shows an equivalent circuit diagram corresponding to FIG. 5 A.
  • FIG. 5C shows a circuit diagram when the FET in FIG. 5A is switched.
  • FIG. 6A shows a cross-sectional view of the structure of the MESFET in the OFF-state and FIG. 6B shows an equivalent circuit diagram corresponding to FIG. 6 A.
  • Embodiment 3 is different from Embodiment 1 in that a voltage of 2.7 V is applied from a biasing terminal 54 via a resistor 42 to an ohmic electrode 10 b that is the drain electrode of the FET 30 a and also the source electrode of the FET 30 b.
  • the depletion layer 27 c can be formed easily when the FETs 30 a and 30 b are off, without forming the ohmic electrode 12 for voltage application on the buffer layer 24 as in Embodiment 2.
  • the value of Cds 12 _off is 0.02 pF, which is about 1 ⁇ 5 of that of the conventional configuration.
  • a voltage of 2.7 V is applied to the biasing terminal 54 .
  • the required minimum voltage applied to the biasing terminal 54 is determined by the electric power that is input and the threshold value of the FET, it should be obvious that the same effect also can be obtained even when a voltage that is different from 2.7 V is applied thereto.
  • FIG. 7A , FIG. 7B , FIG. 7C , FIG. 8 A and FIG. 8 B a MESFET that is a semiconductor device according to Embodiment 4 of the present invention will be described with reference to FIG. 7A , FIG. 7B , FIG. 7C , FIG. 8 A and FIG. 8 B.
  • FIG. 7A shows a cross-sectional view of the structure of a dual-gate MESFET in the ON-state, formed on a GaAs semi-insulating substrate.
  • FIG. 7B shows an equivalent circuit diagram corresponding to FIG. 7 A.
  • FIG. 7C shows a circuit diagram when the FET in FIG. 7A is switched.
  • FIG. 8A shows a cross-sectional view of the structure of the dual-gate MESFET in the OFF-state and FIG. 8B shows an equivalent circuit diagram corresponding to FIG. 8 A.
  • numeral 10 a denotes a source electrode.
  • Numeral 21 b denotes an n+ region between gates.
  • Numeral 10 c denotes a drain electrode.
  • Numeral 11 a denotes a first gate electrode.
  • Numeral 11 b denotes a second gate electrode.
  • Cgs 11 13 on indicates the capacitance between the first gate and the source of the FET in the ON-state.
  • Cgd 11 13 on indicates the capacitance between the first gate and the n+ region between the gates of the FET in the ON-state.
  • Cds 11 _on indicates the capacitance between the first source and the n+ region between the gates of the FET in the ON-state.
  • Rch 1 indicates the channel resistance of the first gate region.
  • Cgs 22 _on indicates the capacitance between the second gate and the n+ region between the gates.
  • Cgd 22 _on indicates the capacitance between the second gate and the drain.
  • Cds 22 _on indicates the capacitance between the second source and the n+ region between the gates of the FET in the ON-state and Rch 2 indicates the channel resistance of the second gate region.
  • numeral 21 denotes a GaAs ohmic contact layer having a film thickness of 100 nm and an impurity density of 1.0 ⁇ 10 18 /cm ⁇ 3 .
  • Numeral 22 denotes an AlGaAs undoped layer having a film thickness of 20 nm and an impurity density of 1.0 ⁇ 10 15 /cm ⁇ 3 .
  • Numeral 23 denotes an AlGaAs active layer having a film thickness of 500 nm and an impurity density of 2.0 ⁇ 10 18 /cm ⁇ 3 .
  • Numeral 24 denotes a superlattice-structured buffer layer having an impurity density of 1.0 ⁇ 10 15 /cm ⁇ 3 in which five AlGaAs layers each with a film thickness of 5 nm and five GaAs layers each with a film thickness of 5 nm are laminated alternately.
  • Numeral 25 denotes a GaAs semi-insulating semiconductor substrate having a substrate thickness of 450 ⁇ m and an impurity density of 1.0 ⁇ 10 15 /cm ⁇ 3 .
  • Numeral 27 b denotes a depletion layer under the first gate electrode and numeral 27 b denotes a depletion layer under the second gate electrode. Standard values of Rch 1 and Rch 2 are 1.5 ⁇ /mm. Both of the gate electrodes 11 a and 11 b have a gate length of 0.5 ⁇ m.
  • the first and the second gate of the dual-gate FET share the active layer 23 . However, they are separated from the other FETs formed on the same semiconductor substrate by etching so as not to share the active layer 23 .
  • the gate width of the FET shown in this embodiment is 2 mm.
  • FIG. 8A is the cross-sectional view of the structure of the FET in the OFF-state.
  • the configuration of FIG. 8A is different from that of FIG. 7A in that Cgs 11 _off indicates the capacitance between the first gate and the source of the FET in the OFF-state, Cgd 11 _off indicates the capacitance between the first gate and the n+ region betwene the gates of the FET in the OFF-state, Cds 11 _off indicates the capacitance between the first source and the n+ region between the gates of the FET in the OFF-state, Cgs 22 _off indicates the capacitance between the second gate and the n+ region between the gates, Cgd 22 _off indicates the capacitance between the second gate and the drain and Cds 22 _off indicates the capacitance between the second source and the n+ region between the gates of the FET in the OFF-state, and that Rch 1 and Rch 2 are so high that they are negligible in the equivalent
  • the method for switching the FET of FIG. 7A is the same as that in the case of Embodiment 1.
  • the resistance of the FETs 30 a and 30 b in Embodiment 1 in the ON-state can be approximated by the sum of Rch 1 and Rch 2 .
  • Rin 2 can be decreased in comparison with that in the case of the circuit in which two FETs are connected in series as shown in Embodiment 1. Therefore, when using an FET having a gate width of 2 mm, the on-resistance is 1.0 ⁇ or lower.
  • the reason that the on-resistance can be reduced as above is as follows.
  • a spacing of 5 ⁇ m or more is required in order to join the source of the FET 30 a and the drain of the FET 30 b and form the electrode 10 b at this joined portion.
  • the need for the electrode 10 b is eliminated and only the n+ layer is required, so that the spacing can be decreased to about 2 ⁇ m, and consequently, the on-resistance can be reduced.
  • FIG. 9A , FIG. 9B , FIG. 9C , FIG. 10 A and FIG. 10 B a MESFET that is a semiconductor device according to Embodiment 5 of the present invention will be described with reference to FIG. 9A , FIG. 9B , FIG. 9C , FIG. 10 A and FIG. 10 B.
  • FIG. 9A shows a cross-sectional view of the structure of the dual-gate MESFET in the ON-state, formed on a GaAs semi-insulating substrate.
  • FIG. 9B shows an equivalent circuit diagram corresponding to FIG. 9 A.
  • FIG. 9C shows a circuit diagram when the FET in FIG. 9A is switched.
  • FIG. 10A shows a cross-sectional view of the structure of the dual-gate MESFET in the OFF-state and FIG. 10B shows an equivalent circuit diagram corresponding to FIG. 10 A.
  • Embodiment 5 is different from that of Embodiment 4 in that an ohmic electrode 12 for voltage application is provided on the buffer layer 24 .
  • a voltage of 0 V is applied to the ohmic electrode 12 for voltage application.
  • the electric charge in the region sandwiched between the depletion layers 27 a and 27 b can be dissipated to the ground when the FET is off, and as a result, the depletion layers underneath the gates in the OFF-state extend over the entire active layer to form one depletion layer 27 c.
  • Cdg 11 _off and Cgs 22 _off can be decreased to such an extent that they are negligible.
  • Cds 12 _off becomes dominant and the series capacitance component of the FET in the OFF-state can be reduced.
  • the value of Cds 12 _off is 0.02 pF, which is about 1 ⁇ 5 of that of the conventional configuration.
  • the ohmic electrode 12 for voltage application is formed on the buffer layer 24 .
  • the same effect also can be expected even when it is formed on the GaAs semi-insulating semiconductor substrate 25 .
  • an ohmic metal is used as the electrode for voltage application, the same effect can be obtained with a Schottky junction metal.

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  • Junction Field-Effect Transistors (AREA)
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JP4854980B2 (ja) * 2005-03-30 2012-01-18 住友電工デバイス・イノベーション株式会社 スイッチ回路及び半導体装置の製造方法
JP5112620B2 (ja) * 2005-05-31 2013-01-09 オンセミコンダクター・トレーディング・リミテッド 化合物半導体装置
JP4538016B2 (ja) * 2007-03-23 2010-09-08 パナソニック株式会社 高周波スイッチ装置および半導体装置

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EP1427017A1 (en) 2004-06-09
US20040026742A1 (en) 2004-02-12

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