US6930361B2 - Semiconductor device realizing characteristics like a SOI MOSFET - Google Patents

Semiconductor device realizing characteristics like a SOI MOSFET Download PDF

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US6930361B2
US6930361B2 US10/042,264 US4226402A US6930361B2 US 6930361 B2 US6930361 B2 US 6930361B2 US 4226402 A US4226402 A US 4226402A US 6930361 B2 US6930361 B2 US 6930361B2
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impurity doped
doped layer
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Satoshi Inaba
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Kioxia Corp
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0883—Combination of depletion and enhancement field effect transistors
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure

Definitions

  • This invention relates generally to semiconductor devices using bulk semiconductor for achievement of highly miniaturized transistors with enhanced performance.
  • the invention also relates to a method of fabricating the same.
  • MOSFETs metal insulator semiconductor field effect transistors
  • SOI silicon-on-insulator
  • the MOSFETs of this type will be referred to as fully depleted SOIFETs or simply FD-SOIFETs.
  • FD-SOIFETs typically these FD-SOIFETs are designed to have a specific thickness and impurity concentration low enough to permit a silicon layer overlying an oxide film for use as a channel region to be fully depleted.
  • a vertical electric field from a gate electrode is partly allotted by a buried oxide film at the bottom of a channel region, resulting in a likewise decrease in vertical electric field being applied to the channel region.
  • the channel region increases in carrier mobility, leading to an advantage or merit as to the obtainability of higher current driving ability or “drivability.”
  • the advantage of FD-SOIFETs does not come without accompanying several penalties. Examples of the penalties are as follows. First, in order to suppress the so-called “short channel” effect, it becomes inevitable to employ SOI substrates with ultra-thin silicon layers. Second, the use of such ultrathin silicon layers would result in an unwanted increase in parasitic resistance values. Third, as a channel region surrounded by oxide films which are ordinarily less in thermal conductivity than silicon, the conductivity of heat generated in self-heatup regions near a drain is made inferior, resulting in an increase in degradation of performance. Another penalty is a problem that the SOI substrates are relatively less in quality whereas gate dielectric films stay less in reliability, causing possible plasma damages to increase accordingly. A further penalty lies in high price of the SOI substrates at least at the present time.
  • the proposed pseudo-SOIFET structures are still encountered with many problems to be solved, one of which is the difficulty in obtaining any sufficient performance on the order of submicrons of minimum feature size. More specifically, the pseudo-SOIFETs as taught from the above-identified three documents (“D1-D3”) are arranged so that a channel region is greater in depth (thickness) than its associated source and drain diffusion layers. This is a serious bar to suppression of short-channel effects in the case of further miniaturization or shrinkage.
  • a semiconductor device includes a semiconductor substrate; a gate electrode formed over a surface of the semiconductor substrate with a gate dielectric film interposed therebetween; a pair of source and drain diffusion layers formed in the semiconductor substrate to oppose each other with a channel region residing therebetween at a location immediately beneath the gate electrode, the source and drain diffusion layers each having a low resistivity region and an extension region being formed to extend from this low resistivity region toward the channel region and being lower in impurity concentration and shallower in depth than the low resistivity region; a first impurity doped layer of a first conductivity type formed in the channel region between the source/drain diffusion layers; a second impurity doped layer of a second conductivity type formed under the first impurity doped layer; and a third impurity doped layer of the first conductivity type formed under the second impurity doped layer, wherein the first impurity doped layer is equal to or less in junction depth than the extension region of each of the source/drain diffusion layers, and wherein
  • a semiconductor device in accordance with another aspect of this invention, includes a semiconductor substrate; a gate electrode as formed above a surface of the semiconductor substrate with a gate dielectric film sandwiched therebetween; a pair of source and drain diffusion layers formed in the semiconductor substrate to oppose each other with a channel region laterally interposed therebetween at a location immediately beneath the gate electrode; a first impurity doped layer of a first conductivity type formed in the channel region between the source/drain diffusion layers; a second impurity doped layer of a second conductivity type formed under the first impurity doped layer; and a third impurity doped layer of the first conductivity type formed under the second impurity doped layer, wherein the first impurity doped layer is equal to or less in junction depth than the source and drain diffusion layers, and wherein the second impurity doped layer is determined in impurity concentration and thickness causing a depth of its junction with the third impurity doped layer to be greater than a junction depth of the source/drain diffusion layers while permitting the second
  • a method of fabricating a semiconductor device includes: letting a first semiconductor layer with no impurity doped therein epitaxially grow on a semiconductor substrate having in at least its surface a first impurity doped layer of a first conductivity type; performing ion implantation into the first semiconductor layer to form a second impurity doped layer of a second conductivity type as contacted with the first impurity doped layer; doing ion implantation into a surface portion of the first semiconductor layer to form a third impurity doped layer of the first conductivity type in contact with the second impurity doped layer; forming above the third impurity doped layer a gate electrode with a gate dielectric film sandwiched therebetween; and forming in the semiconductor substrate a pair of source and drain diffusion layers being self-aligned with the gate electrode and having a junction depth deeper than a junction between the third impurity doped layer and the second impurity doped layer and yet shallower than a junction between the second im
  • FIG. 1 is a diagram illustrating, in cross-section, main part of an FD-SOIFET structure in accordance with an embodiment of this invention.
  • FIG. 2 is a graph showing impurity concentration distribution patterns in a direction along the depth of a channel region of the FD-SOIFET shown in FIG. 1 .
  • FIG. 3 is a graph showing a relation of a threshold voltage roll-off value ⁇ Vth versus p-type layer thickness of an SODELFET embodying the invention in comparison with that of an SOIFET.
  • FIG. 4 is a graph showing a relation of a threshold voltage roll-off value ⁇ Vth and electron mobility ⁇ e versus n ⁇ -type layer thickness of the SODELFET embodying the invention in comparison with that of the SOIFET.
  • FIGS. 5A through 5D illustrate, in cross-section, some of the major process steps in the manufacture of a p/n ⁇ /p multilayer structure of the FD-SODELFET of the embodiment.
  • FIGS. 6A to 6 E depict, in cross-section, some major process steps of another fabrication method of the p/n ⁇ /p multilayer structure of the embodiment FD-SODELFET.
  • FIG. 7 shows a sectional view of a device structure at a process step of forming the p/n ⁇ /p structure and a step of element isolation for integration of the embodiment FD-SODELFET.
  • FIG. 8 is a sectional view of a device structure at a gate electrode formation step and source/drain extension region formation step in the manufacture of the FD-SODELFET.
  • FIG. 9 is a sectional view of a device structure at a gate sidewall dielectric film formation step in the manufacture of the FD-SODELFET.
  • FIG. 10 is a sectional view of a device structure at a step of selective epitaxial growth of source/drain regions in the manufacture of the FD-SODELFET.
  • FIG. 11 is a sectional view of a device structure at a source/drain low-resistivity region formation step in the manufacture of the FD-SODELFET.
  • FIG. 12 is a sectional view of a device structure at a step of forming an interlayer dielectric film and contact plugs in the manufacture of the FD-SODELFET.
  • FIG. 13 is a graph showing a plot of threshold voltage roll-off value as a function of gate length.
  • FIG. 14 is a diagram showing a sectional view of an FD-SODELFET structure in accordance with another embodiment of this invention.
  • FIG. 15 is a diagram showing a sectional view of an FD-SODELFET structure in accordance with still another embodiment of the invention.
  • FIG. 16 depicts a sectional view of a device structure with an FD-SODELFET and a bulk FET integrated together.
  • FIG. 17 shows a sectional view of a device structure with an FD-SODELFET and a PD-SODELFET integrated together.
  • FIG. 18 is a graph showing impurity concentration distribution patterns in a channel region of the PD-SODELFET of FIG. 17 .
  • FIG. 19 is a graph showing static characteristics of the PD-SODELFET of FIG. 17 .
  • FIG. 20 is a graph showing the drain voltage dependency of a body potential of the PD-SODELFET of FIG. 18 .
  • FIG. 21 depicts a sectional view of a device structure with a PD-SODELFET and a bulk FET integrated together.
  • FIG. 22 is a diagram showing a configuration of one preferable circuit example adaptable for application of this invention.
  • FIG. 23 is a diagram showing another preferred circuit example adaptable for application of this invention.
  • FIG. 24 is a graph demonstrating the effect of substrate bias application of the FD-SODELFET in accordance with this invention.
  • FIG. 25 depicts a sectional view of a device structure with an SOIFET and a bulk FET integrated together.
  • MISFETs metal insulator semiconductor field effect transistors
  • FIG. 1 there is illustrated a sectional view of a structure of main part of a MISFET in accordance with a first embodiment of the invention.
  • a silicon substrate 1 has its top surface in which a p-type impurity doped layer 2 is formed by well ion implantation techniques. Formed on this p-type layer 2 are a lightly-doped n (n ⁇ ) type impurity doped layer of low impurity concentration and further a p-type impurity doped layer 4 for use as a channel region. These layers 2 - 4 make up a multilayer lamination structure with p/n ⁇ /p junction.
  • this p/n ⁇ /p junction multilayer structure at least the upper p-type layer 4 and its underlying n ⁇ -type layer 3 —are fabricated by epitaxial growth process and ion implantation process in combination, as will be described in detail later in the description.
  • a gate electrode 6 is formed over the p-type layer 4 for use as the channel region, with a gate dielectric film 5 being interposed therebetween.
  • the gate electrode 6 consists essentially of a metal electrode 6 a having a prespecified work function and a polycrystalline silicon or “polysilicon” electrode 6 b stacked on metal electrode 6 a.
  • the illustrative MISFET structure also includes source and drain diffusion layers 7 .
  • These source/drain diffusion layers 7 are each structured from a heavily-doped n (n + ) type region 7 a of low electrical resistivity and a shallow n-type extension region 7 b that is lower in impurity concentration than n + -type region 7 a.
  • the low-resistivity n + -type layer 7 a is fabricated through ion implantation with both the gate electrode 6 and a sidewall dielectric film 8 as provided on a lateral wall of gate electrode 6 being used as a mask therefor.
  • the shallow n-type extension region 7 b is formed by ion implantation with gate electrode 6 as a mask, prior to fabrication of sidewall dielectric film 8 , in such a manner as to extend from n + -type low-resistivity region 7 a toward the channel region.
  • Low resistivity region 7 a is formed in the state that it is upwardly projected than the level of gate dielectric film 5 .
  • this structure is obtainable by effectuation of selective epitaxial growth after having formed gate electrode 6 . And the use of this structure permits a junction plane or surface at the bottom of low resistivity region 7 a is located at a position that does not reach the underlying p-type layer 2 —that is, within n ⁇ -type layer 3 .
  • n ⁇ -type layer 3 of the p/n ⁇ /p junction multilayer structure beneath the gate electrode 6 is carefully designed to have a specific impurity concentration and thickness, causing layer 3 to be completely or fully depleted due to a built-in potential between the upper and lower p-type layers 4 , 2 .
  • the transistor of this embodiment becomes a “pseudo” silicon-on-insulator (SOI) FET that is similar to an SOI structure with a buried oxide film under a channel region.
  • SOI silicon-on-insulator
  • This unique type of transistor may be considered to be the one that employs silicon overlying a depletion layer. In this respect, the transistor will be referred to hereinafter as “silicon on depletion layer” FET or simply “SODEL” FET.
  • the p-type channel region layer 4 is carefully adjusted both in its impurity concentration and in thickness to ensure that layer 4 is fully depleted upon formation of a channel inversion layer.
  • the illustrative structure becomes a fully depleted (FD) element—that is, FD-SODELFET.
  • the p-type layer 4 should be required to be sufficiently thin in order to suppress or minimize the so-called short channel effects.
  • its junction depth (the position of a junction plane with n ⁇ -type layer 3 ) is set less than or equal to that of the source/drain extension regions 7 b.
  • the example of FIG. 1 is illustratively such that p-type layer 4 is less or “shallower” in junction depth than source/drain extension regions 7 b.
  • This graph shows a relation of threshold voltage's roll-off value ⁇ Vth (a difference between a threshold voltage upon occurrence of short-channeling and a threshold voltage during long-channeling) versus thickness of the p-type layer 4 in the channel region, with the impurity concentration of p-type layer 4 as a parameter. Additionally it is known among those skilled in the semiconductor device art that the threshold voltage roll-off value ⁇ Vth increases with a decrease in gate length Lg (i.e. channel length) as shown in FIG. 13 .
  • Lg i.e. channel length
  • n ⁇ -type layer 3 measure 1E16/cm 3 in impurity concentration and a gate oxide film thickness be set at 3 nanometers (nm) under application of a supply voltage Vdd of 1.2 volts (V).
  • Vdd supply voltage
  • the graph of FIG. 3 shows data of an SOIFET by dotted lines; in addition, data plotted in a rectangle of broken lines indicates the case of a standard or “ordinary” bulk FET using a uniformly doped p-type bulk silicon.
  • the threshold voltage roll-off value ⁇ Vth decreases and comes closer to zero with a decrease in thickness of the p-type layer 4 , thus enabling suppression of short-channel effects.
  • This is a similar effect to the SOIFET and is due to the fact that making the channel region thinner weakens the two-dimensional effect of a potential distribution along a drain shape, resulting in determination of the threshold voltage only by a one-dimensional potential distribution in the vertical direction.
  • FIG. 3 also indicates that if the ⁇ Vth value is kept identical, the FD-SODELFET of this embodiment may be greater in thickness of the p-type layer 4 than SOIFETs.
  • the effects and advantages stated above depend on the impurity concentration of the p-type layer 4 .
  • the impurity concentration of p-type layer 4 becomes greater than or equal to about 1E17/cm 3 , then the intended thinning-based short-channel effect suppressibility will hardly be obtainable.
  • successful establishment of the effects does strictly require execution of a significant amount of thinning processing. This is due to the fact that thinning must result in a decrease in extension or elongation of a depletion layer at a location immediately beneath the transistor channel region.
  • the p-type layer 4 for use as the channel region be optimized both in impurity concentration and in thickness.
  • n ⁇ -type layer 3 which is required to be fully depleted due to a built-in potential, this is also to be optimized in impurity concentration and thickness. This can be said because if part of n ⁇ -type layer 3 is failed to be depleted, then electrical shorting can occur between the source and drain, resulting in an increase in current leakage therebetween.
  • the film thickness of n ⁇ -type layer 3 may be set relatively greater in order to retain the channel region greater in carrier mobility.
  • FIG. 4 is a graph showing a relation of ⁇ Vth value and carrier mobility (electron mobility ⁇ e) for indication of short channel effects versus thickness of this n ⁇ -type layer 3 .
  • the thicker the n ⁇ -type layer 3 the greater the electron mobility ⁇ e, and thus the greater the ⁇ Vth value also.
  • the short-channel effect suppressibility suppressibility and the carrier mobility improvement.
  • the junction depth of the n + -type layers 7 a for use as the source/drain low resistivity regions are specifically set shallower than—i.e. higher in level than—the junction between n ⁇ -type layer 3 and p-type layer 2 .
  • junction depth setup it is possible to suppress both the source/drain junction capacitance values and junction leakage more significantly than possible with ones having n + -type layers 7 a formed deep enough to reach the underlying p-type layer 2 ; in addition, it becomes expectable to obtain a higher punch-through immunity even when the threshold voltage is kept at low levels.
  • a further advantage lies in a capability to speed up an operation of the resultant transistor owing to a decrease in source/drain junction capacitance.
  • the resulting impurity profile is far from the initially desired one even when forming the n ⁇ -type layer 3 and p-type layer 4 of low impurity concentration values by further effectuating extra ion implantation into a surface portion of the p-type layer thus formed.
  • SODELFET fabrication methodology of this invention is specifically arranged to utilize epitaxial growth layers with respect to the p-type layer 4 for use as the channel region in FIG. 1 and its underlying n ⁇ -type layer 3 .
  • Exemplary fabrication processes for obtaining the p/n ⁇ /p multilayer structure of FIG. 1 will be set forth below.
  • FIGS. 5A to 5 D there are shown some major steps in a p/n ⁇ /p junction multilayer structure fabrication process including an element isolation process(s), in view of the applicability to practically reduced integrated circuit (IC) chips with complexities of from large-scale integration (LSI) to very large-scale integration (VLSI) and also to ultralarge-scale integration (ULSI).
  • IC integrated circuit
  • FIG. 5A a silicon substrate 1 is prepared.
  • a multilayer mask having a buffer oxide film 21 and an overlying silicon nitride film 22 .
  • Use reactive ion etching (RIE) techniques to define trenches in element isolation regions. Embed or bury in the trenches a dielectric film 23 for use as an element isolator.
  • RIE reactive ion etching
  • boron (B) ions are implanted with a dose of 10 13 /cm 2 under application of an acceleration voltage of 20 KeV. And, let an undoped or “non-doped” silicon layer 10 epitaxially grow on this p-type layer 2 to a predetermined thickness of about 80 nanometers (nm), by way of example.
  • n ⁇ -type layer 3 on layer 2 in substrate 1 .
  • Exemplary conditions of this As ion implantation are as follows: an acceleration voltage is set at 20 KeV; dose is at 5 ⁇ 10 11 /cm 2 .
  • FIG. 5D perform B ion implantation to thereby form in a surface portion of the n ⁇ -type layer 3 a p-type layer 4 for later use as a transistor channel region.
  • this B ion implantation is conducted under the conditions which follow: its acceleration voltage is at 5 KeV with a dose of 6 ⁇ 10 11 /cm 2 .
  • FIGS. 6A-6E a process example is shown which utilizes a two-step epitaxial growth scheme in order to fabricate the p/n ⁇ /p junction multilayer structure.
  • FIG. 6A shows an element isolation step similar to that shown in FIG. 5 A.
  • FIG. 6B after completion of the element isolation, form p-type layer 2 by B ion implantation into the surface of silicon substrate 1 ; thereafter, let a non-doped silicon layer 10 epitaxially grow on this layer 2 . Then, as shown in FIG. 6C , perform As ion implantation into this silicon layer 10 , thereby forming an n ⁇ -type layer 3 .
  • FIG. 6D again perform epitaxial growth, thus forming a non-doped silicon layer 11 on n ⁇ -type layer 3 .
  • FIG. 6E perform B ion implantation into silicon layer 11 , forming a p-type layer 4 for later use as the transistor channel region.
  • FIG. 2 An impurity profile of the p/n ⁇ /p junction multilayer structure thus fabricated in this way is shown in FIG. 2 .
  • Combined use of epitaxial growth process makes it possible to successfully form the n ⁇ -type layer 3 and p-type layer 4 each having an adequately lowered impurity concentration and a carefully chosen thickness value as required to establish the complete or full depletability required.
  • Performing the element isolation process prior to fabrication of the p/n ⁇ /p multilayer structure in the way stated above is preferable for preclusion of any unwanted re-diffusion of an impurity once doped into the p/n ⁇ /p structure due to the presence of heat during such element isolation.
  • This process is encountered with a risk that silicon layer components in neighboring element regions are accidentally coupled or interconnected together on the surface of an element isolation region during epitaxial growth of the silicon layer. Fortunately this risk is avoidable without fail by specifically arranging the execution order of process steps in such a manner that the element isolation comes after fabrication of the p/n ⁇ /p structure.
  • FIGS. 7 through 12 As per the case of such element isolation process step ordering scheme, one practically implementable process for SODELFET integration will next be set forth with reference to FIGS. 7 through 12 below. Assume here that a p-type layer 2 and n ⁇ -type layer 3 plus p-type layer 4 laminated on the silicon substrate 1 shown in FIG. 7 are the ones as fabricated by combined effectuation of the epitaxial growth process and ion implantation process as previously discussed in conjunction with either FIGS. 5A to 5 D or FIGS. 6A-6E .
  • the substrate with such p/n ⁇ /p multilayer structure formed is then subjected to pattern formation of a mask in a transistor region, the mask being made up from a lamination of a buffer oxide film 21 and silicon nitride film 22 as shown in FIG. 7 .
  • RIE is done to define therein required element isolation grooves deep enough to reach the underlying p-type layer 2 .
  • an element isolation film 23 be buried in the grooves.
  • the gate electrode 6 may be a multilayer electrode formed of a metallic electrode 6 a having its work function necessary for obtaining a prespecified threshold voltage level and a polysilicon electrode 6 b.
  • This multilayer electrode is pattern-formed with a silicon nitride film 24 being used as a mask.
  • perform As ion implantation with gate electrode 6 as a mask thereby to form a couple of spaced-apart n-type layers for use as the source/drain extension regions 7 b.
  • Each extension region 7 b is greater in junction depth than p-type layer 4 ; thus, the former is deeper than the latter. Note here that the junction depth of extension region 7 b may alternatively be almost the same as that of p-type layer 4 , when the need arises.
  • each low resistivity region 7 a is carefully adjusted to ensure that its bottom does not reach the underlying p-type layer 2 .
  • an interlayer dielectric (ILD) film 27 is deposited; then, form required contact holes therein for embedment of contact plugs 28 made of tungsten (W) or other similar suitable materials.
  • the process to be done thereafter includes the step of forming a pattern of metallic on-chip leads on or above the ILD film 27 .
  • the SODELFET embodying the invention is specifically arranged so that the p-type layer 4 of the channel region is fabricated causing its junction depth to be less or “shallower” than that of the source/drain extension regions 7 b while at the same time letting the thickness of n ⁇ -type layer 3 be relatively significant to thereby ensure that the bottom surface of a respective one of the source/drain low-resistivity regions 7 a resides within the n ⁇ -type layer 3 .
  • higher carrier mobility in the channel region is guaranteed owing to vertical electric field relaxation effects; in addition, it becomes possible to greatly suppress or minimize creation of any possible short-channel effects even in sub-micron regions.
  • the gate electrode 6 is comprised of metal electrode 6 a.
  • the metal electrode 6 a may be made of TiN, WN or the like.
  • the metal electrode 6 a having two work functions are the ones using in combination two different conductive materials—such as TiN and WN or, alternatively, W and WN.
  • any desired threshold voltage is attainable by use of such metal electrode 6 a with appropriate work functions in a way pursuant to the threshold voltage required.
  • the gate electrode may be formed of polysilicon film pursuant to the threshold voltage required.
  • the p-type layer 4 may be replaced with either a SiGe or Si/SiGe distortion alloy layer in order to further improve the carrier mobility of the channel region.
  • a SiGe or Si/SiGe distortion alloy layer in order to further improve the carrier mobility of the channel region.
  • the use of such layer makes it possible to obtain SODELFETs with much higher current drivabilities. The same goes with any one of the following embodiments as will be discussed below.
  • FIG. 14 This diagram depicts a sectional view of an SODELFET structure capable of preventing any punch-through with increased reliability in accordance with a second embodiment of the invention, wherein the depiction here is shown in a way corresponding to FIG. 1 .
  • This embodiment is similar to that of FIG. 1 except that p-type layers 9 are additionally provided as “halo” regions. These layers are buried in the n ⁇ -type layer 3 at locations immediately beneath the source/drain extension regions 7 b, respectively.
  • appropriate value setting of the impurity concentration and thickness of p-type layer 4 enables accomplishment of the intended FD-SODELFET device.
  • letting p-type layer 4 have a further increased impurity concentration makes it possible to obtain a PD-SODELFET.
  • p/n ⁇ /p multilayer structures may be formed in substantially the same way, i.e. through combined effectuation of epitaxial growth and ion implantation into the entire surface of a substrate.
  • similar results are obtainable by use of selective ion implantation techniques—in this case, the p/n ⁇ /p structures are fabricated in units of channel regions of respective transistors involved.
  • FIG. 15 there is shown in a manner corresponding to FIG. 1 a sectional view of an SODELFET also embodying the invention, which employs selective ion implantation to selectively fabricate the intended p/n ⁇ /p junction multilayer structure in a specified region immediately beneath a gate electrode.
  • arsenic (As) ion implantation is selectively done only at a channel body forming portion of an undoped or “nondoped” epitaxially grown silicon layer 10 , thereby forming an n ⁇ -type layer 3 .
  • the resulting extension regions 7 b of source/drain diffusion layers 7 are such that the bottom surface of each is in contact with its underlying n ⁇ -type layer 3 while a respective n + -type low-resistivity region 7 a has its bottom face residing within the nondoped silicon layer 10 .
  • n ⁇ -type layer 3 Forming the n ⁇ -type layer 3 exclusively at a selected portion just beneath the channel region in this way forces the bottom surfaces of source/drain low-resistivity regions 7 a to stay within the nondoped, intrinsic (“i”-type) silicon layer 10 . This makes it possible to further reduce the source/drain junction capacitance values.
  • FIG. 16 A structure of main part of an LSI chip with an FD-SODELFET and a normal bulk FET integrated together is depicted in cross-section in FIG. 16 , wherein the FD-SODELFET is the same in principle as that of the third embodiment stated supra.
  • the illustrative “hybrid” LSI device structure will now be explained in accordance with a flow of its fabrication process steps. As in the fabrication process of the first embodiment, let an undoped or nondoped silicon layer 10 epitaxially grow on a silicon substrate 1 with a p-type layer formed therein. Then, embed or bury an element isolation film 30 in each element isolation region by shallow trench isolation (STI) techniques. If necessary, the p-type layer 2 may be selectively formed by ion implantation only in an SODELFET region, rather than is formed to cover an entire surface of the substrate.
  • STI shallow trench isolation
  • the FD-SODELFET region is subjected, prior to formation of a gate electrode 6 , to selective ion implantation similar to that discussed in conjunction with the fourth embodiment, thereby sequentially forming an n ⁇ -type layer 3 and p-type layer 4 .
  • the epitaxially grown nondoped silicon layer 10 is subject to another selective ion implantation, forming a p-type bulk layer (i.e., channel body) 31 that is deep sufficient to reach the underlying p-type layer 2 . Further, channel ion implantation may be done as occasion demands.
  • FIG. 17 A hybrid LSI device structure also embodying the invention with an FD-SODELFET and a PD-SODELFET integrated together is shown in FIG. 17 , wherein the PD-SODELFET is a partially depletable element which lacks full depletability even upon formation of a channel inversion layer.
  • the FD-SODELFET shown is manufacturable by similar process to that shown in FIG. 16 .
  • the n ⁇ -type layer 3 a and p-type layer 4 a are sequentially fabricated under specific ion implantation conditions different from the FD-SODELFET.
  • the n ⁇ -type layer 3 a of PD-SODELFET may be the same in process conditions as an n ⁇ -type layer 3 on the FD-SODELFET side.
  • At least the PD-SODELFET's p-type layer 4 a is to be formed in such a manner that it is greater both in impurity concentration and in thickness than the p-type layer 4 of FD-SODELFET.
  • the p-type layer 4 a is greater or “deeper” in diffusion depth than source/drain extension regions 7 b and yet shallower than n + -type low-resistivity regions 7 a.
  • n ⁇ -type layer 3 a are selectively formed at a location immediately beneath a channel region associated therewith.
  • the n ⁇ -type layer 3 a has its opposite terminate end portions as contacted with source/drain extension regions 7 b respectively.
  • FIG. 18 which demonstrates an exemplary plot of impurity concentration distribution of a p/n ⁇ /p junction multilayer structure of the PD-SODELFET in comparison with that of FD-SODELFET shown in FIG. 2 .
  • the p-type layer 4 a 's boron concentration is higher than that of FIG. 2 by about one order of magnitude.
  • the intended PD-SODELFET is obtained which is higher in threshold voltage than the FD-SODELFET and permits p-type layer 4 a to be partially depleted upon formation of a channel inversion layer.
  • p-type layer 4 a is surrounded by a depletion layer occurring between itself and extension region 7 b and the fully depleted n ⁇ -type layer 3 a, thereby becoming an electrically “floating” p-type layer.
  • FIG. 19 is a graph showing drain voltage Vd versus drain current Id characteristics of the above-noted PD-SODELFET with gate voltage Vg as a parameter, which have been obtained through computation.
  • the gate length Lg is set at 70 nm
  • the drain current Id behaves to rapidly increase in intensity at a certain value of drain voltage Vd. This is known as “kink” characteristics among those skilled in the semiconductor device art.
  • This kink instability is the property unique to PD-SODELFETs, which is obtainable by virtual threshold voltage drop-down occurring due to partial depletion of the p-type layer 4 a. Practically this kink property takes place upon virtual reduction of the threshold voltage, which in turn is caused by a mechanism which follows: upon exceeding of a certain drain voltage, holes as created by impact ionization are stored or accumulated at the p-type layer.
  • FIG. 20 This is a graph showing experimental data of the PD-SODELFET for demonstrating a typical plot of voltage Vb of the channel body (i.e. p-type layer 4 a ) as a function of time with epitaxially grown silicon layer 10 's thickness as a parameter when causing a drain voltage Vd to rapidly vary in potential with time in a pulse-like fashion as indicated by dotted lines, while letting a gate voltage Vg kept constant.
  • the drain voltage Vd changes, the body potential Vb changes accordingly, which in turn well demonstrates that p-type layer 4 a is substantially in the floating state.
  • FIG. 21 shows an integrated structure having an PD-SODELFET and a normal bulk FET in accordance with sixth embodiment.
  • the respective channel body structures of the PD-SODELFET and the bulk FET are similar to that of the embodiment of FIG. 16 .
  • the p-type layer 4 of the PD-SEDELFET is, however, formed to have a higher impurity concentration than that of the FD-SODELFET in FIG. 16 . Whereby, the p-type layer 4 becomes to be partially depleted when a channel inversion layer is formed.
  • gate threshold voltage thereof becomes too high.
  • the threshold voltage of the bulk FET may be set to lower. AS a result, it is possible to obtain a high current drivable bulk FET.
  • FD-SODELFETs and PD-SODELFETs in FIGS. 16 , 17 and 21 are modifiable so that each is structured so that p-type layers 9 are buried as halo regions at locations right below the source/drain extension regions 7 b respectively, as in the embodiment of FIG. 14 .
  • FIG. 22 depicts a configuration of NAND gate circuitry, which is arranged using a serial connection of three n-channel transistors QN 1 to QN 3 and a parallel combination of p-channel transistors QP 1 -QP 3 .
  • the n-channel transistors QN 1 to QN 3 serially connected between an output terminal OUT and ground terminal Vss with the gates serving as input terminals A, B and C, respectively.
  • the p-channel transistors QP 1 to QP 3 are connected in parallel between the output terminal OUTPUT and a power supply terminal Vdd with the gates being connected to the respective input terminals A to C.
  • the transistors QN 1 -QN 3 are formed of FD-SODELFETs, PD-SODELFETs shown in FIG. 1 , or PD-SODELFETs shown in FIG. 17 which are inherently less in substrate bias influence than bulk FETs.
  • the p-channel transistors QP 1 -QP 3 are designed to employ bulk FETs that have the same structure shown in FIG. 16 and are less in current leakage otherwise occurring due to the presence of possible parasitic bipolar transistor components. With such an arrangement, it is possible to attain higher operation stability and also higher noise margins.
  • n-channel transistors QN 11 -QN 13 that are connected between nodes N 1 and N 2 in parallel, are switching devices with the gates serving as input terminals A, B, and C, respectively.
  • a precharging p-channel transistor QP 11 Provided between the node N 1 and a power supply terminal Vdd is a precharging p-channel transistor QP 11 , of which gate is driven by precharge signal PRE.
  • n-channel activation transistor QN 14 is disposed between the node N 2 and a ground terminal Vss, of which gate is driven by clock signal CK.
  • the node N 1 is coupled to an output terminal OUT through an inverter INV.
  • a p-channel transistor QP 12 Further provided between node N 1 and supply terminal Vdd is a p-channel transistor QP 12 as controlled by a voltage appearing at output terminal OUT.
  • node N 1 With such clock-driven dynamic circuit, it becomes difficult to achieve high speed operations if the node N 1 is significant in capacitance.
  • the capacitance Adversely if the capacitance is less then the resultant noise margin tends to decreases.
  • analog circuits and/or sense amplifier circuits for use with semiconductor memory devices are typically formed of differential amplifiers.
  • a differential amplifier made up from two complementary metal oxide semiconductor (CMOS) circuits is under a strict requirement that such two CMOS circuits are exactly identical in threshold voltage to each other.
  • CMOS complementary metal oxide semiconductor
  • SODELFETs embodying the invention these can experience deviation or “offset” in threshold voltage values under influence of the history in the past in view of the fact that a channel body region(s) is/are in the floating state. This makes it rather difficult to align the threshold voltage levels of two CMOS circuits in any events. Consequently, even in the LSI chip using SODELFETs embodying the invention, it will be preferable to employ “different-FET-for-different-part” schemes for using bulk FETs for the differential amplifiers.
  • LSIs using the FD-SODELFETs embodying the invention it is also effective to additionally comprise substrate bias application circuitry for selectively applying a substrate bias voltage for threshold voltage adjustment to the p-type layer at lower part in case p/n ⁇ /p junction multilayer structures are provided separately in units of on-chip elements.
  • substrate bias application circuitry for selectively applying a substrate bias voltage for threshold voltage adjustment to the p-type layer at lower part in case p/n ⁇ /p junction multilayer structures are provided separately in units of on-chip elements.
  • FIG. 24 shows a plot of drain current Id of the FIG.
  • FIG. 22 and the dynamic domino circuit shown in FIG. 23 may be configured to employ a combination of SOIFETs and bulk FETs which are formed in a partial SOI substrate.
  • FIG. 25 shows an integrated structure of an SOIFET and a bulk FET integrally formed in a partial SOI substrate.
  • the partial SOI substrate has an SOI structure region where a thin silicon layer 103 is formed over a silicon substrate 101 with an insulating film 102 buried therebetween, and a bulk region where no insulating film is buried.
  • the SOIFET is formed in the silicon layer 103 of the SOI region.
  • the SOIFET has a gate electrode 202 formed above the silicon layer 103 with a gate insulating film 201 interposed therebetween, and source/drain diffused layers 203 .
  • the source/drain diffused layers 203 are formed as to be contacted with the insulating film 102 .
  • the SOIFET becomes a fully depleted FET.
  • an n-type (or p-type) well layer 301 is formed in the bulk region to have a gate electrode 303 formed above the well layer 301 with a gate insulating film 302 interposed therebetween, and source/drain diffused layers 304 .
  • n-channel transistors QN 1 -QN 3 in the NAND gate circuit shown in FIG. 22 are formed of SOIFETs as shown in FIG. 25 .
  • p-channel transistors QP 1 -QP 3 in the NAND gate circuit are formed of bulk FET shown in FIG. 25 .
  • n-channel transistors QN 11 -QN 13 in the dynamic domino circuit shown in FIG. 23 are formed of SOIFETs shown in FIG. 25 .
  • p-channel transistors QP 1 , QP 12 and n-channel transistor QN 14 in the dynamic domino circuit are formed of bulk FET shown in FIG. 25 .

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US20050218449A1 (en) 2005-10-06
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EP1225622B1 (fr) 2006-08-16
CN1220271C (zh) 2005-09-21
CN1366347A (zh) 2002-08-28
EP1225622A3 (fr) 2003-11-12
US20020093064A1 (en) 2002-07-18
EP1225622A2 (fr) 2002-07-24
US7400016B2 (en) 2008-07-15
KR20020062200A (ko) 2002-07-25
DE60213889T2 (de) 2007-09-06

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