US6791878B2 - Word line decoder in nand type flash memory device - Google Patents

Word line decoder in nand type flash memory device Download PDF

Info

Publication number
US6791878B2
US6791878B2 US10/310,033 US31003302A US6791878B2 US 6791878 B2 US6791878 B2 US 6791878B2 US 31003302 A US31003302 A US 31003302A US 6791878 B2 US6791878 B2 US 6791878B2
Authority
US
United States
Prior art keywords
node
gate
memory cell
negative voltage
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US10/310,033
Other languages
English (en)
Other versions
US20030214842A1 (en
Inventor
Jong Bae Jeong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JEONG, JONG BAE
Publication of US20030214842A1 publication Critical patent/US20030214842A1/en
Application granted granted Critical
Publication of US6791878B2 publication Critical patent/US6791878B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Definitions

  • the invention relates generally to a NAND type flash memory device, and more particularly to, a word line decoder having a switch structure for applying a negative voltage to a word line, and transistors.
  • a NAND type flash memory device one of non-volatile semiconductor memory devices, has a level of integration and a memory capacity corresponding to DRAM. Due to these advantages, the NAND type flash memory device has been increasingly used.
  • the NAND type flash memory device has basically a structure in which a memory string where a plurality of memory cells are serially connected is serially connected between a bit line and a source line. A plurality of the memory cells are arranged to form a memory cell array. The memory cells connected to one word line with the memory string intervened them form a page unit or a byte unit. In order to perform a read operation or a write operation by selecting a given cell of the flash memory device, a corresponding cell is selected by word line and bit line select signals.
  • the decoder for selecting the word line is called a word line decoder.
  • a conventional word line decoder and memory cell will be below described by reference to FIG. 1 and FIG. 2 .
  • FIG. 1 is a structure of the conventional word line decoder and memory cell.
  • the structure includes a row decoder & charge pump 10 , a block-driving unit 12 and a memory cell array 14 .
  • One cell block includes a plurality of strings. At this time, each of the strings is intervened between one bit line B/L and a common source line.
  • One cell block includes a string select line SSL, a plurality of word lines W/L and a ground select line GSL.
  • the block-driving unit 12 includes a string control line SS, a plurality of word control lines S, a ground control line GS and a plurality of transistors for driving the blocks.
  • the plurality of the transistors are controlled by the row decoder & charge pump 10 to control only one cell block.
  • the transistor includes one string driving transistor connected to the string control line SS, a plurality of word driving transistors connected to the word control lines S, and one ground driving transistor connected to the ground control line GS.
  • a desired cell transistor at the cell array 14 region is to be selectively programmed, 0V is applied to a semiconductor substrate in which the cell array 14 region is formed, that is, the bulk region and the common source line of the cell transistor. Also, 0V is applied to the bit line and the ground control line connected to the selected cell transistor. At this time, a program inhibition voltage is applied to all of not-selected bit lines. Also, a program voltage is applied to the word control line connected to the selected cell transistor. A voltage that is sufficiently higher than the program voltage applied to the word control line, is applied to the transistor of the block driving unit 12 , so that the block driving transistors can be sufficiently turned on. That is, the string driving transistors, the word driving transistors and the ground driving transistor are all turned on. At this time, a program operation for the selected cell transistor is performed by means of a F-N tunneling current. Program inhibition of the not-selected cell transistors is performed by means of a self-boosting phenomenon.
  • FIG. 1 will be further explained by reference to FIG. 2 .
  • FIG. 2 is a detailed circuit diagram of the word line decoder shown in FIG. 1 .
  • the word line decoder includes a row decoder 20 , a high-voltage control circuit 22 and a driving transistor 24 .
  • the high-voltage control circuit 22 includes a second NAND gate NAND 2 , transistors M 1 , M 2 , M 3 , M 5 , an inverter INV 1 and capacitors C 1 , C 2 .
  • An output signal of the row decoder 20 and the clock signal (CLK) are inputted to an input of the second NAND gate NAND 2 .
  • a power supply voltage (Vcc) is applied to the gate of the transistor M 1 , and a voltage Vpp that is same to or lower than the power supply voltage is applied to one inputs of the transistors M 3 and M 5 .
  • the driving transistors 24 includes a string driving transistor connected to the string control line SS, a plurality of cell transistors connected to the word control lines S, and a ground driving transistor connected to the ground control line GS.
  • the driving transistors may be implemented using NMOS.
  • the high-voltage control circuit 22 outputs (Vpp+Vtn) using the clock signal (CLK). At this time, Vtn is the threshold voltage of the driving transistors 24 . Therefore, the driving transistors 24 are turned on. If the positive voltage is applied to the string control line SS, the word control lines S and the ground control line GS, Vtn is applied to the string select line SSL, the word lines WL and the ground select line GSL. The capacitors C 1 , C 2 serve to boost the applied Vpp in order to make it (Vpp+Vtn).
  • the output of the row decoder is LOW, the output of the second NAND gate NAND 2 is regardless of the clock signal (CLK) and the capacitors C 1 , C 2 do not serve to boost Vpp. Therefore, as LOW inputted from the row decoder 20 is intact outputted through transistor M 1 , the driving transistors 24 is turned off. Also, the positive voltage applied to the string control line SS, the word control lines S and the ground control line GS is not transferred to the string select line SSL, the word lines WL and the ground select line GSL.
  • the conventional word line decoder can apply only the positive voltage to the memory cell array. This is because only the positive voltage can be applied to the string control line SS, the word control lines S and the ground control line GS of the driving transistors 24 but the negative voltage could not be applied to them.
  • FIG. 3 is a cross sectional view of the flash memory cell in which the negative voltage is applied to the driving transistors shown in FIG. 2 . If the driving transistor is to be implemented using NMOS, a P well is grounded. If ⁇ 10V of the negative voltage is applied to the source S, the NMOS transistor does not properly operate due to a forward condition of the PN junction.
  • FIG. 3 is a cross sectional view of a flash memory cell in which a negative voltage is applied to the driving transistors shown in FIG. 2;
  • FIG. 5 is a detailed circuit of the control unit shown in FIG. 4 according to a preferred embodiment of the present invention.
  • FIG. 6 is a circuit diagram for implementing the inverter shown in FIG. 5;
  • FIG. 8 is a circuit diagram of the driving unit shown in FIG. 4 according to a preferred embodiment of the present invention.
  • FIG. 9 is a cross sectional view of the NMOS transistor shown in FIG. 8 for explaining triple well structures of the transistors.
  • FIG. 4 is a block diagram of a word line decoder in a NAND type flash memory device according to a preferred embodiment of the present invention.
  • the word line decoder includes a row decoder 40 , a control unit 42 and a driving unit 44 .
  • the word line decoder in the NAND type flash memory device serves to decode a word line select signal for a selected memory cell in order to perform a specific operation such as a read operation or a write operation for the specific memory cell of the memory cell array.
  • the row decoder 40 receives an address of a given memory cell to output a signal informing that a given memory cell is selected or not selected. If a given memory cell is selected, the row decoder 40 outputs HIGH. The row decoder 40 may output LOW for other not-selected memory cells. At this time, the given memory cell is a predetermined memory cell in the apparatus for processing the operation of the flash memory device. For example, if a second cell transistor in a first string is to be programmed, the second word line must be selected. If an address corresponding to the second word line is inputted, the row decoder 40 outputs a signal of HIGH. The row decoder 40 outputs LOW for the remaining word lines.
  • the output signal of the row decoder 40 is inputted to the control unit 42 .
  • the output signal of the control unit 42 is inputted to the driving unit 44 .
  • the driving unit 44 is connected to the transistor of each of the memory cells, so that the transistor of each of the memory cells can perform an operation depending on the signal of the driving unit 44 .
  • the control unit 42 serves to control the transistor of the driving unit 44 . If the control unit 42 is informed of a fact that a given memory cell is selected from the row decoder 40 , the control unit 42 outputs a positive voltage to the driving unit 44 . On the contrary, if the control unit 42 is informed of a fact that the given memory cell is not selected from the row decoder 40 , the control unit 42 outputs a negative voltage to the driving unit 44 .
  • FIG. 5 is a detailed circuit of the control unit 42 shown in FIG. 4 according to a preferred embodiment of the present invention.
  • the control unit 42 includes an inverter INV, PMOS transistors MP 1 , MP 2 , MP 3 , and NMOS transistors MN 1 , MN 2 , MN 3 .
  • the inverter INV is connected between a first input terminal IN 1 and a first node n 1 .
  • the first NMOS transistor MN 1 is connected between the first node n 1 and a second node n 2 .
  • the power supply voltage (Vcc) is applied to a gate of the first NMOS transistor MN 1 .
  • a first PMOS transistor MP 1 is connected between the first node n 1 and a third node n 3 .
  • a gate of the first PMOS transistor MP 1 is grounded.
  • a second PMOS transistor MP 2 is connected to the second node n 2 .
  • a second input terminal IN 2 is connected to the other side of the second PMOS transistor MP 2 .
  • a positive voltage is applied to the second input terminal IN 2 .
  • V PPX a voltage higher than the power supply voltage may be applied to the second input terminal IN 2 .
  • a gate of the second PMOS transistor MP 2 is connected to an output terminal OUT.
  • the second NMOS transistor MN 2 is connected between the third node n 3 and the third input terminal IN 3 .
  • a gate of the second NMOS transistor (NM 2 ) is connected to the output terminal OUT.
  • the negative voltage, for example V EEX may be applied to the third input terminal IN 3 .
  • the third PMOS transistor MP 3 is connected between the second input terminal IN 2 and the output terminal OUT.
  • a gate of the third PMOS transistor MP 3 is connected to the second node n 2 .
  • the third NMOS transistor MN 3 is connected between the third input terminal IN 3 and the output terminal OUT.
  • a gate of the third NMOS transistor MN 3 is connected to the third node n 3 .
  • the inverter INV inverts a signal inputted from the input terminal. Thus, if the signal inputted to the inverter INV from the row decoder 40 through the first input terminal IN 1 is HIGH, the inverter INV outputs a LOW signal. If the signal inputted to the inverter INV from the row decoder 40 through the first input terminal IN 1 is LOW, the inverter INV outputs a HIGH signal.
  • FIG. 6 A circuit that implements the inverter INV is shown in FIG. 6 .
  • a PMOS transistor (MP) is connected between the power supply voltage (Vcc) and the first node n 1 .
  • a gate of the PMOS transistor (MP) is connected to the first input terminal IN 1 .
  • a NMOS transistor MN is connected between the first node n 1 and the ground.
  • a gate of the NMOS transistor MN is connected to the first input terminal IN 1 . If the signal inputted through the first input terminal IN 1 is HIGH, the NMOS transistor MN is turned on but the PMOS transistor (MP) is turned off. Thus, the ground voltage, i.e., LOW is outputted to the first node n 1 .
  • the inverter circuit serves to invert the signal inputted through the first input terminal IN 1 .
  • control unit 42 One embodiment of implementing the control unit 42 will be explained by reference to FIG. 5 again.
  • the first node n 1 becomes LOW.
  • the power supply voltage is applied to the gate of the first NMOS transistor MN 1 and the gate of the first PMOS transistor MP 1 is grounded, the first NMOS transistor MN 1 and the first PMOS transistor MP 1 are turned on.
  • the LOW signal of the first node n 1 is thus applied to the gate of the third PMOS transistor MP 3 through the second node n 2 , so that the third PMOS transistor MP 3 is turned on.
  • the positive voltage inputted through the second input terminal IN 2 for example V PPX is outputted through the output terminal OUT.
  • the LOW signal of the first node n 1 is applied to the gate of the third NMOS transistor MN 3 through the third node n 3 , so that the third NMOS transistor MN 3 is turned off. Also, the negative voltage inputted through the third input terminal IN 3 , for example V EEX is not outputted through the output terminal OUT.
  • the first node n 1 becomes HIGH.
  • the power supply voltage is applied to the gate of the first NMOS transistor MN 1 and the gate of the first PMOS transistor MP 1 is grounded, the first NMOS transistor MN 1 and the first PMOS transistor MP 1 are turned on.
  • the third PMOS transistor MP 3 is turned off.
  • the third NMOS transistor MN 3 is turned on.
  • the negative voltage inputted through the third input terminal IN 3 for example V EEX is outputted to the output terminal OUT.
  • V EEX is applied to both the gates of them.
  • V EEX should not be applied to other not-selected transistors
  • V EEX should be applied to the gate of the third NMOS transistor MN 3
  • V EEX should be applied to the third node n 3 .
  • V EEX is applied to the source and gate of the third NMOS transistor MN 3 , so that the third NMOS transistor MN 3 is turned off.
  • the second NMOS transistor MN 2 serves to turn off the third NMOS transistor MN 3 .
  • control unit 42 An operation of the control unit 42 will be described by reference to FIG. 7 .
  • FIG. 7 is a waveform for explaining the output signal of the control unit 42 depending on the input signal.
  • FIG. 7A is a waveform when the input of the first input terminal IN 1 is LOW and
  • FIG. 7B is a waveform when the input of the first input terminal IN 1 is HIGH.
  • Vcc the power supply voltage
  • the driving unit 44 includes a NMOS transistor. If the positive voltage applied from the control unit 42 is applied to the gate of the NMOS transistor, the NMOS transistors is turned on so that it outputs the negative voltage inputted to the source of the NMOS transistor to the memory cell. If the negative voltage is applied to the gate of the NMOS transistor from the control unit 42 , the NMOS transistors is turned off, so that it prohibits the negative voltage inputted to the source of the NMOS transistor from being outputted to the memory cell. Also, the same voltage to the negative voltage applied to the source of the NMOS transistor is applied to the P well of the NMOS transistor.
  • FIG. 8 is a circuit diagram of the driving unit shown in FIG. 4 according to a preferred embodiment of the present invention.
  • the NMOS transistors includes a ground select transistor MGS for transferring the voltage applied to a ground control line GS to a ground select line GSL, cell transistors MS for transferring the voltage applied to word control lines S to word lines WL, and a string select transistor MSS for transferring the voltage applied to a string control line SS to a string select line SSL.
  • a negative voltage for example V EEX is applied to the ground control line GS, the word control lines S and the string control line SS, and V EEX being a negative voltage is also applied to the P well of the transistor.
  • Each of the output signals of the control unit 42 is applied to the gate of each of the transistors through the fourth input terminal (IN 4 ).
  • the NMOS transistor of the driving unit 44 is turned on.
  • V EEX applied to the string control line SS, the word control lines S and the ground control line GS is transferred to the string select line SSL, the word lines WL and the ground select line GSL.
  • the output of the row decoder 40 is LOW and the output of the control unit 42 is V EEX
  • the NMOS transistor is turned off.
  • V EEX applied to the string control line SS, the word control lines s and the ground control line GS is not transferred to the string select line SSL, the word lines WL and the ground select line GSL.
  • the negative voltage can be applied to the word line of the selected memory cell by the row decoder.
  • V EEX being the same negative voltage to that applied to the string control line SS, the word control lines S and the ground control line GS is applied to the P well of the NMOS transistor implementing the driving unit 44 .
  • This is for the purpose of preventing mal-function of the transistor since the PN junction portion becomes a forward bias.
  • the NMOS transistor of this driving unit 44 can be formed to have a triple well structure, which will be explained by reference to FIG. 9 .
  • FIG. 9 is a cross sectional view of the NMOS transistor of the triple well structure shown in FIG. 8 for explaining triple well structures of the transistors.
  • a N well TNWELL is formed in a P type substrate P sub.
  • a P well TPWELL is the formed in the N well.
  • a source S and drain D region N+ is formed in the P well TPWELL and a region P+ for applying a voltage to the P well TPWELL is formed in the P well TPWELL.
  • Vdd being the power supply voltage is applied to the N well TNWELL and the P type substrate P SUB is grounded.
  • a negative voltage is applied to the word line of the memory cell.
  • write or erase operations can be performed for a selected memory cell using the negative voltage.
  • the present invention has advantageous effects that it can prevent distortion of data by lowering a well bias when the memory cell is erased, and obtain a stable data retention compared to the conventional flash memory device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
US10/310,033 2002-05-17 2002-12-05 Word line decoder in nand type flash memory device Expired - Fee Related US6791878B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR2002-27481 2002-05-17
KR10-2002-0027481 2002-05-17
KR10-2002-0027481A KR100474201B1 (ko) 2002-05-17 2002-05-17 낸드형 플래시 메모리의 워드 라인 디코더

Publications (2)

Publication Number Publication Date
US20030214842A1 US20030214842A1 (en) 2003-11-20
US6791878B2 true US6791878B2 (en) 2004-09-14

Family

ID=29417418

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/310,033 Expired - Fee Related US6791878B2 (en) 2002-05-17 2002-12-05 Word line decoder in nand type flash memory device

Country Status (3)

Country Link
US (1) US6791878B2 (ko)
JP (1) JP2003338189A (ko)
KR (1) KR100474201B1 (ko)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080106947A1 (en) * 2006-11-02 2008-05-08 Samsung Electronics Co., Ltd. Decoders and decoding methods for nonvolatile memory devices using level shifting
US20080106941A1 (en) * 2006-11-02 2008-05-08 Samsung Electronics Co., Ltd. Decoders and decoding methods for nonvolatile semiconductor memory devices
US20080285345A1 (en) * 2005-07-14 2008-11-20 Noboru Shibata Semiconductor memory device capable of increasing writing speed
US20110002173A1 (en) * 2009-07-03 2011-01-06 Nec Electronics Corporation Nonvolatile semiconductor memory device
US20110019495A1 (en) * 2006-07-31 2011-01-27 Scheuerlein Roy E Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same
US20130107627A1 (en) * 2011-10-26 2013-05-02 Fumiaki TOYAMA Back-biasing word line switch transistors
US9208889B2 (en) 2013-02-08 2015-12-08 Sandisk Technologies Inc. Non-volatile memory including bit line switch transistors formed in a triple-well
US20180062508A1 (en) * 2015-02-13 2018-03-01 Apple Inc. Charge pump having ac and dc outputs for touch panel bootstrapping and substrate biasing

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100520682B1 (ko) * 2004-02-25 2005-10-11 주식회사 하이닉스반도체 반도체 소자의 고전압 스위치 회로
KR100607349B1 (ko) * 2004-08-26 2006-07-28 주식회사 하이닉스반도체 반도체 장치의 고전압 스위치 회로
KR100609576B1 (ko) * 2004-10-05 2006-08-09 에스티마이크로일렉트로닉스 엔.브이. 플래쉬 메모리 소자의 블럭 스위치
KR100673170B1 (ko) * 2005-03-10 2007-01-22 주식회사 하이닉스반도체 향상된 소거 기능을 가지는 플래쉬 메모리 장치 및 그 소거동작 제어 방법
US7486550B2 (en) * 2006-06-06 2009-02-03 Micron Technology, Inc. Semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell
KR100908516B1 (ko) * 2007-01-03 2009-07-20 주식회사 하이닉스반도체 플래쉬 메모리 소자용 고전압 생성기
US7672163B2 (en) * 2007-09-14 2010-03-02 Sandisk Corporation Control gate line architecture
JP2010086623A (ja) * 2008-10-01 2010-04-15 Toshiba Corp Ｎａｎｄ型フラッシュメモリ
KR101146820B1 (ko) 2010-09-01 2012-05-21 에스케이하이닉스 주식회사 불휘발성 메모리 장치 및 그 동작 방법
JP2013058276A (ja) 2011-09-07 2013-03-28 Toshiba Corp 半導体記憶装置
JP5249394B2 (ja) * 2011-09-28 2013-07-31 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置
JP5216908B2 (ja) * 2011-12-13 2013-06-19 株式会社東芝 半導体記憶装置
KR102210520B1 (ko) * 2013-12-19 2021-02-02 삼성전자주식회사 비휘발성 메모리 장치 및 그것의 소거 방법
JP6492202B1 (ja) * 2018-03-05 2019-03-27 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置および消去方法
JP2019160379A (ja) * 2018-03-16 2019-09-19 東芝メモリ株式会社 半導体記憶装置及びメモリシステム

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6370062B2 (en) * 1999-12-10 2002-04-09 Samsung Electronics Co., Ltd. NAND-type flash memory device and method of operating the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2804066B2 (ja) * 1989-02-22 1998-09-24 株式会社東芝 不揮発性半導体メモリ装置
JPH06168597A (ja) * 1992-03-19 1994-06-14 Fujitsu Ltd フラッシュメモリ及びレベル変換回路
JP3520532B2 (ja) * 1993-08-06 2004-04-19 ソニー株式会社 Ｎａｎｄ型不揮発性メモリの駆動方法
GB9406117D0 (en) * 1994-03-28 1994-05-18 Ici Plc Oxidation process
KR19980055944A (ko) * 1996-12-28 1998-09-25 김영환 플래쉬 메모리 장치의 프로그램 및 소거방법
JPH1145986A (ja) * 1997-07-28 1999-02-16 Sony Corp 不揮発性半導体記憶装置
JPH1187662A (ja) * 1997-09-08 1999-03-30 Sony Corp 不揮発性半導体記憶装置及びその書き込み方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6370062B2 (en) * 1999-12-10 2002-04-09 Samsung Electronics Co., Ltd. NAND-type flash memory device and method of operating the same

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7933152B2 (en) 2005-07-14 2011-04-26 Kabushiki Kaisha Toshiba Semiconductor memory device capable of increasing writing speed
US8098524B2 (en) 2005-07-14 2012-01-17 Kabushiki Kaisha Toshiba Semiconductor memory device capable of increasing writing speed
US7663919B2 (en) * 2005-07-14 2010-02-16 Kabushiki Kaisha Toshiba Semiconductor memory device capable of increasing writing speed
US8406056B2 (en) 2005-07-14 2013-03-26 Kabushiki Kaisha Toshiba Semiconductor memory device capable of increasing writing speed
US20080285345A1 (en) * 2005-07-14 2008-11-20 Noboru Shibata Semiconductor memory device capable of increasing writing speed
US20110019495A1 (en) * 2006-07-31 2011-01-27 Scheuerlein Roy E Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same
US8279704B2 (en) 2006-07-31 2012-10-02 Sandisk 3D Llc Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same
US7724582B2 (en) 2006-11-02 2010-05-25 Samsung Electronics Co., Ltd. Decoders and decoding methods for nonvolatile memory devices using level shifting
US7616487B2 (en) 2006-11-02 2009-11-10 Samsung Electronics Co., Ltd. Decoders and decoding methods for nonvolatile semiconductor memory devices
US20080106941A1 (en) * 2006-11-02 2008-05-08 Samsung Electronics Co., Ltd. Decoders and decoding methods for nonvolatile semiconductor memory devices
US20080106947A1 (en) * 2006-11-02 2008-05-08 Samsung Electronics Co., Ltd. Decoders and decoding methods for nonvolatile memory devices using level shifting
US20110002173A1 (en) * 2009-07-03 2011-01-06 Nec Electronics Corporation Nonvolatile semiconductor memory device
US8379452B2 (en) * 2009-07-03 2013-02-19 Renesas Electronics Corporation Nonvolatile semiconductor memory device
US20130107627A1 (en) * 2011-10-26 2013-05-02 Fumiaki TOYAMA Back-biasing word line switch transistors
US8917554B2 (en) * 2011-10-26 2014-12-23 Sandisk Technologies Inc. Back-biasing word line switch transistors
US9208889B2 (en) 2013-02-08 2015-12-08 Sandisk Technologies Inc. Non-volatile memory including bit line switch transistors formed in a triple-well
US10277119B2 (en) * 2015-02-13 2019-04-30 Apple Inc. Charge pump having AC and DC outputs for touch panel bootstrapping and substrate biasing
US20180062508A1 (en) * 2015-02-13 2018-03-01 Apple Inc. Charge pump having ac and dc outputs for touch panel bootstrapping and substrate biasing

Also Published As

Publication number Publication date
JP2003338189A (ja) 2003-11-28
US20030214842A1 (en) 2003-11-20
KR20030089315A (ko) 2003-11-21
KR100474201B1 (ko) 2005-03-08

Similar Documents

Publication Publication Date Title
US6791878B2 (en) Word line decoder in nand type flash memory device
US5770963A (en) Flash memory with improved erasability and its circuitry
US7020024B2 (en) Methods and devices for increasing voltages on non-selected wordlines during erasure of a flash memory
KR0172441B1 (ko) 불휘발성 반도체 메모리의 프로그램 방법
US5541879A (en) Nonvolatile semiconductor memory having program verifying circuit
US6587375B2 (en) Row decoder for a nonvolatile memory device
US6717861B2 (en) Non-volatile semiconductor memory device capable of preventing program disturb due to noise voltage induced at a string select line and program method thereof
JP3741735B2 (ja) 不揮発性メモリ装置
US20060077716A1 (en) Row decoder circuit of NAND flash memory and method of supplying an operating voltage using the same
US6236594B1 (en) Flash memory device including circuitry for selecting a memory block
KR100395771B1 (ko) 불휘발성 반도체 메모리 장치 및 그것의 프로그램 방법
US6891757B2 (en) Semiconductor memory device
US5767729A (en) Distribution charge pump for nonvolatile memory device
US7466605B2 (en) Semiconductor device and control method therefor
JP3223877B2 (ja) 半導体記憶装置
EP0842514A1 (en) Flash memory system having reduced disturb and method
US20100080063A1 (en) Nonvolatile semiconductor memory device
US8446764B2 (en) Control voltage generation circuit and non-volatile memory device including the same
US6654294B2 (en) Flash memory device
EP0377841B1 (en) Semiconductor integrated circuit capable of preventing occurrence of erroneous operation due to noise
US5327392A (en) Semiconductor integrated circuit capable of preventing occurrence of erroneous operation due to noise
US6639840B1 (en) Non-volatile latch circuit that has minimal control circuitry
JP3775927B2 (ja) 電圧発生回路を備えた不揮発性半導体記憶装置及びその電圧発生制御方法
US10790028B1 (en) AND type flash memory
KR19990084702A (ko) 불휘발성 메모리 장치의 페이지 버퍼

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JEONG, JONG BAE;REEL/FRAME:013548/0049

Effective date: 20021118

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20160914