US6434062B2 - Delay locked loop for use in semiconductor memory device - Google Patents

Delay locked loop for use in semiconductor memory device Download PDF

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US6434062B2
US6434062B2 US09/745,490 US74549000A US6434062B2 US 6434062 B2 US6434062 B2 US 6434062B2 US 74549000 A US74549000 A US 74549000A US 6434062 B2 US6434062 B2 US 6434062B2
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signal
directional
backward
delay
output
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US20010022745A1 (en
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Seong-Hoon Lee
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter

Definitions

  • the present invention relates to a semiconductor memory device; and, more particularly, to a delay locked loop using a bi-directional ring oscillator and a counter unit.
  • a delay locked loop (DLL) circuit reduces or compensates a skew between a clock signal and data or between an external clock and an internal clock, which is used in synchronizing an internal clock of a synchronous memory to an external clock without incurring any error.
  • a timing delay occurs when a clock provided externally is used within the apparatus.
  • the delay locked loop controls the timing delay to synchronize the internal clock to the external clock.
  • the synchronization between the internal and external clocks requires operations of compensating a jitter of the external clock with an internal delay locked loop, controlling a time delay unit such that a delay of the internal clock is less sensitive to noise introduced by a power supply or random noises, and fastening a locking time at maximum through the control of the time delay unit.
  • a delay locked loop with a reduced jitter and an easily controllable time delay unit to satisfy the foregoing requirements has been recently presented in ISSCC paper in 1999, entitled “A 250 Mb/s/pin 1 Gb Double Data Rate SDRAM with a Bi-Directional Delay and an Inter-Bank Shared Redundancy Scheme” by NEC Corporation.
  • FIG. 1 is a connection diagram of a conventional linear bi-directional delay DLL proposed by NEC Corporation.
  • the conventional DLL includes an input unit 100 , a first to a third D-flip flop 101 , 103 and 104 , a first inverter 102 , a dummy delay unit 105 , a first and a second AND gate 106 and 107 , a first and a second bi-directional delay block 108 and 109 , a first and a second pulse generation unit 110 and 111 , and an OR gate 112 .
  • the input unit 100 receives a clock signal CLK and a non-clock signal CLKB via positive and negative terminals respectively and compares received signals to produce a rising clock Rclk.
  • the first D-flip slop 101 receives the rising clock Rclk as a clock signal and outputs a control signal with a pulse duration corresponding to one cycle of the rising clock Rclk.
  • the first inverter 102 inverts the output of the first D-flip flop 101 to produce an inverted signal to be fed back as input to the first D-flip flop 101 .
  • the second D-flip flop 103 receives the output of the first D-flip flop 101 and the rising clock Rclk from the input unit 100 and produces a first forward signal FWD_A having a pulse duration corresponding to one cycle of the output of the first D-flip flop 101 and a first backward signal BWD_A having an opposite phase to the first forward signal FWD_A.
  • the third D-flip flop 104 receives an inverted value of the output of the first D-flip flop 101 and the rising clock Rclk, and produces a second forward signal FWD_B having a pulse duration corresponding to one cycle of the output of the first D-flip flop 101 and a second backward signal BWD_B having an opposite phase to the second forward signal FWD_B.
  • the dummy delay unit 105 delays the rising clock Rclk by a skew to compensate the clock signal CLK.
  • the first AND gate 106 logically combines the outputs of the second D-flip flop 103 and the dummy delay unit 105 to produce a combined output.
  • the second AND gate 107 logically combines the outputs of the third D-flip flop 104 and the dummy delay unit 105 to produce a combined output.
  • the first bi-directional delay block 108 including a multiplicity of unit bi-directional delays which are connected serially, receives the output of the first AND gate 106 and controls a time delay in a first or second direction under the control of the first forward signal FWD_A and the first backward signal BWD_A.
  • the second bi-directional delay block 109 including a multiplicity of unit bi-directional delays which are connected in series, receives the output of the second AND gate 107 and controls a time delay in the first or second direction under the control of the second forward signal FWD_B and the second backward signal BWD_B.
  • the first pulse generation unit 110 generates a pulse at a rising and a falling edge of the output of the first bi-directional delay block 108 .
  • the second pulse generation unit 111 generates a pulse at a rising and a falling edge of the output of the second bi-directional delay block 109 .
  • the OR gate 112 performs an OR operation on the outputs of the first and second pulse generation units 110 and 111 .
  • FIG. 2A is a connection diagram of a conventional unit bi-directional delay, which has been proposed by FUJITSU Ltd.
  • the unit bi-directional delay proposed by FUJITSU includes four three-phase buffers 200 , 201 , 202 and 203 .
  • the first three-phase buffer 200 receives one of the outputs of the first and second AND gates as a first input signal A m to produce a second control signal B m , wherein the gate of a PMOS transistor is controlled by the first or second backward signal (hereinafter called BWD) and the gate of an NMOS transistor is controlled by the first or second forward signal (hereinafter called FWD).
  • BWD first or second backward signal
  • FWD first or second forward signal
  • the second three-phase buffer 201 receives the second output signal B m , wherein the gate of a PMOS transistor is controlled by the BWD signal and the gate of an NMOS transistor is controlled by the FWD signal.
  • the third three-phase buffer 202 receives the output of a unit bi-directional delay at a previous stage as a second input signal B m+1 , to produce a first output signal A m+1 , wherein the gate of a PMOS transistor is controlled by the backward signal BWD and the gate of an NMOS transistor is controlled by the forward signal FWD.
  • the fourth three-phase buffer 203 receives the first output signal A m+1 to produce the second output signal B m , wherein the gate of a PMOS transistor is controlled by the forward signal FWD and the gate of an NMOS transistor is controlled by the backward signal BWD.
  • the first and second three-phase buffers 200 and 201 are activated to provide input signal to the first direction (i.e., the forward direction).
  • the forward signal FWD is logic low and the backward signal BWD is logic high
  • the third and fourth three-phase buffers 202 and 203 are activated to provide input signal to the second direction (i.e., the backward direction).
  • FIG. 2B is a symbolic diagram of the unit bi-directional delay shown in FIG. 2 A.
  • the construction and operation of the device in FIG. 2B is similar that of the device previously described in conjunction with FIG. 2 A and therefore a further description thereof is omitted.
  • FIG. 2C is a connection diagram of the unit bi-directional delay proposed by NEC Corporation.
  • a difference between NEC and FUJITSU is that the PMOS transistor is removed in the first and fourth three-phase buffers 200 and 203 , and the NMOS transistor is removed in the second and third three-phase buffers 201 and 202 , preventing both of the first and second input signals A m and B m+1 with a logic low value from being transmitted to corresponding buffers.
  • the construction of the delay locked loop described above generates a DLL signal at the rising clock Rclk of the clock signal CLK
  • the construction for the rising clock Rclk is similar to that of a delay locked loop for outputting the DLL signal at the falling clock Fclk of the clock signal CLK except that the output signal of the input unit 100 is a falling clock.
  • FIG. 3 is a timing diagram illustrating the operating principle of the first and second bi-directional delay blocks.
  • the logic high signal A 0 _A is propagated to the first direction (i.e., the forward direction).
  • the forward direction i.e., the forward direction
  • rendering of the forward node to logic high allows the backward node corresponding thereto to be rendered to logic low, it is necessary to set the backward node to logic low in all positions to which the logic high is transmitted.
  • the first forward signal FWD_A is rendered to a logic low and the first backward signal BWD_A is rendered to a logic high, at the same time that the logic high signal is propagated to the second direction (i.e., the backward direction) to thereby render the first output signal B 0 — A to a logic high after an interval t clk -t dm , wherein t clk is one clock cycle. That is, the signal precedes a rising edge of a subsequent clock by t dm .
  • the logic high of the second output signal B 0 _A means that all the backward nodes have been rendered to logic high and also all the forward nodes have been rendered to logic low. In short, a reset may be automatically performed for subsequent processes without any reset operation.
  • the delay locked loop may be implemented with the bi-directional delay.
  • the interval t clk -t dm increases with an increase in one clock cycle t clk , so that the bi-directional delay line should be lengthened by an increased interval. That is, many unit bi-directional delays are additionally required.
  • the first and second bi-directional delay blocks 108 and 109 of the delay locked loop shown in FIG. 1 include 40 stages of unit bi-directional delays to adjust a time delay in low frequency applications, and four control signal lines to be used in controlling each of the unit bi-directional delays.
  • the prior art imposes great chip area requirements, which, in turn, may decrease the number of chips per wafer, thereby leading to increase in cost for the apparatus.
  • a primary object of the present invention to provide a delay locked loop, which is capable of achieving a reduced jitter and a stable time delay adjustment, to thereby perform a bi-directional time delay with a small area even in low frequency applications.
  • a delay locked loop for use in a semiconductor memory device, which comprises: an input unit for receiving a clock signal and a non-clock signal and comparing received signals to produce an internal clock signal; a controller for receiving the internal clock to produce a first forward signal and a second backward signal each having a pulse duration corresponding to one cycle of the clock signal, a first backward signal and a second forward signal each having an opposite phase to the first forward signal and the second backward signal, and a first and a second start signal each having a pulse duration corresponding to a time delay to be compensated; a bi-directional oscillator, responsive to the second forward signal, the second backward signal and the second start signal, for performing a ring oscillation in a first or second direction and fulfilling an addition and subtraction adjustment function for a time delay; a counter for receiving an output signal of the bi-directional oscillator and counting the ring oscillations; and an output means for performing a combination operation on the outputs of the bi
  • the present invention employs only four stages of unit bi-directional delay block and a three-bits counter to allow an operation to be performed at frequencies up to 40 MHz. Also, the present invention employs only four stages of unit bi-directional delay block and a four-bits counter to allow the operation to be performed at frequencies up to 20 MHz. Accordingly, the present invention has the ability to implement a delay locked loop with a reduced layout requirement even at a low frequency of 25 MHz corresponding to a wafer test frequency.
  • FIG. 1 shows a connection diagram of a conventional linear bi-directional delay DLL proposed by NEC Corporation
  • FIG. 2A is connection diagram of a conventional unit bi-directional delay which has been proposed by FUJITSU Ltd.
  • FIG. 2B is a symbolic diagram of the unit bi-directional delay shown in FIG. 2A;
  • FIG. 2C is a connection diagram of the unit bi-directional delay proposed by NEC Corporation.
  • FIG. 3 is a timing diagram illustrating the operating principle of the first and second bi-directional delay blocks
  • FIG. 4 is a connection diagram of a delay locked loop in accordance with preferred embodiments of the present invention.
  • FIG. 5 is a timing diagram illustrating a flow of control signals output from the controller 410 of the present invention.
  • FIG. 6A is a block diagram showing that a unit bi-directional inverter is inserted at the linear bi-directional delays
  • FIG. 6B is a schematic block diagram illustrating the principle of the bi-directional ring oscillator 421 in accordance with a preferred embodiment of the present invention.
  • FIG. 7A is a connection diagram of the unit bi-directional delay 426 in a first stage in accordance with the present invention.
  • FIG. 7B is a symbolic diagram of the unit bi-directional delay shown in FIG. 7A in accordance with the present invention.
  • FIG. 8A is a connection diagram of the unit bi-directional inverter 429 of present invention.
  • FIG. 8B is a connection diagram in which three unit bi-directional inverters are connected in series for simulation.
  • FIG. 9 is a timing diagram of signal waveforms in accordance with the present invention.
  • FIG. 4 There is shown in FIG. 4 a connection diagram of a delay locked loop in accordance with preferred embodiments of the present invention.
  • the delay locked loop of the present invention comprises an input unit 400 , a controller 410 , a first and a second bi-directional delay blocks 420 and 430 , and an OR gate 440 .
  • the input unit 400 receives a clock signal CLK and a non-clock signal CLKB and compares received signals to produce a rising clock Rclk.
  • the controller 410 receives the rising block Rclk as a clock signal, and outputs a first forward signal FWD_A and a second backward signal BWD_B each having a pulse duration corresponding to one cycle of the clock signal CLK, a first backward signal BWD_A and a second forward signal FWD_B each having an opposite phase to the first forward signal FWD_A and the second backward signal BWD_B, and a first and a second start signals START_A and START_B each having a pulse duration corresponding to a time delay to be compensated.
  • the first bi-directional delay block 420 which includes a bi-directional ring oscillator 421 and a counter unit 426 , receives the first forward signal FWD_A, the first backward signal BWD_A and the first start signal START_A from the controller 410 to perform an addition and subtraction adjustment function for a time delay.
  • the second bi-directional delay block 430 which includes a bi-directional ring oscillator and a counter unit, receives the second forward signal FWD_B, the second backward signal BWD_B and the second start signal START_B from the controller 410 to perform an addition and subtraction adjustment function for a time delay.
  • the OR gate 440 performs an OR operation on the outputs of the first and second bi-directional delay blocks 420 and 430 , to generate the result as a final rising block Rclk_DLL.
  • the controller 410 includes a first to third D-flip flops 411 , 412 and 414 , a dummy delay unit 413 , and a first and a second AND gates 415 and 416 .
  • the first D-flip flop 411 receives the rising block Rclk as a clock signal to produce a first forward signal FWD_A having a pulse duration corresponding to one cycle of the clock signal CLK and a first backward signal BWD_A having an opposite phase to the first forward signal FWD_A.
  • the second D-flip flop 412 receives the rising clock Rclk as a clock signal to produce a second forward signal FWD_B having a pulse duration corresponding to one cycle of the clock signal CLK and a second backward signal BWD_B having an opposite phase to the second forward signal FWD_B.
  • the dummy delay unit 413 delays the rising clock Rclk by a skew to compensate the clock signal CLK.
  • the third D-flip flop 414 receives the output of the dummy delay unit 413 as a clock signal to produce a first delay rising clock Rclk_A and a second delay rising clock Rclk_B having an opposite phase to the first delay rising clock Rclk_A.
  • the first AND gate 415 logically combines the first delay rising clock Rclk_A and the first forward signal FWD_A to produce a combined output.
  • the second AND gate 416 logically combines the second delay rising clock Rclk_B and the second forward signal FWD_B to produce a combined output.
  • the first bi-directional delay block 420 includes a bi-directional ring oscillator 421 , a forward counter 422 , a backward counter 423 , a counter comparator 424 and an AND gate 425 .
  • the bi-directional ring oscillator 421 receives the first start signal START_A and performs a ring oscillation in a first and a second directions.
  • the bi-directional ring oscillator 421 receives the first start signal START_A and performs a ring oscillation in a first and a second direction.
  • the forward counter 422 receives a forward loop signal from the bi-directional ring oscillator 421 to count the number of the oscillations.
  • the backward counter 423 receives a backward loop signal from the bi-directional oscillator 421 to count the number of the oscillations.
  • the counter comparator 424 compares the outputs of the forward counter 422 and the backward counter 423 to determine if the outputs (i.e., counted numbers) are identical to each other.
  • the AND gate 425 logically combines the outputs of the bi-directional ring oscillator 421 and the counter comparator 424 to produce a combined value.
  • a simplified bi-directional ring oscillator has the capacity to function as the multi-stages of delay line formed by unit bi-directional delays in the prior art.
  • the construction of the second bi-directional delay block 430 is similar to that of the first bi-directional delay block 420 except that the second start signal START_B is fed to the bi-directional ring oscillator.
  • the bi-directional ring oscillator 421 includes three unit bi-directional delays 426 , 427 and 428 , and a bi-directional inverter 429 .
  • the unit bi-directional delays 426 , 427 and 428 which are connected in series, receive a first output signal A 0 _A from the bi-directional inverter 429 to output the forward loop signal in the first direction, and receive the backward loop signal from the bi-directional inverter 429 to output a second output signal B 0 _A in the second direction, under the control of the first start signal START_A, the first forward signal FWD_A and the first backward signal BWD_A.
  • the bi-directional inverter 429 receives the forward loop signal to output the first output signal A 0 _A in the first direction and receives the second output signal B 0 _A to produce the backward loop signal in the second direction, under the control of the first forward signal FWD_A and the first backward signal BWD_A.
  • FIG. 5 is a timing diagram illustrating a flow of control signals output from the controller 410 of the present invention.
  • the first forward signal FWD_A and the first backward signal BWD_A are out-of-phase and two cycle signals, and similarly the second forward signal FWD_B and the second backward signal BWD_B are out-of-phase and two cycle signals. Accordingly, the first forward signal FWD_A and the second backward signal BWD_B are identical, and the first backward signal BWD_A and the second forward signal FWD_B are identical.
  • the first and second delay rising clocks Rclk_A and Rclk_B are signals reflecting a dummy delay (t dm in FIG. 5 ).
  • the rising of the first start signal START_A is controlled by the first delay rising clock Rclk_A, and the falling thereof is controlled by the first forward signal FWD_A.
  • the first and second bi-directional delay units 420 and 430 have the same structure and operate alternately every one cycle.
  • the delay locked loop In operation, the delay locked loop generates a clock preceding an external clock by the compensation skew t dm , wherein t dm is a fixed value, typically several nanoseconds. Accordingly, these delay locked loops are commonly used to measure the interval between t clk and t dm and to delay a clock by a measured interval.
  • FIG. 6A is a block diagram showing that a unit bi-directional inverter is inserted at the linear bi-directional delays.
  • the inverting operation of the unit bi-directional inverter allows a logic low and a logic high to be alternately rendered to thereby transmit a corresponding signal via a unit delay line.
  • the bi-directional delay unit is indicated by a white block and the bi-directional inverter is indicated by a black block.
  • the overall operation of FIG. 6A is similar to that of the linear bi-directional delay discussed above, except that a phase of the signal is inverted on each occasion that it is passed through the unit bi-directional inverter. That is, a delay to a backward direction may occur in correspondence to a time proceeded to a forward direction.
  • FIG. 6A shows that the signal is periodically passed through the unit bi-directional inverter, so FIG. 6A is contemplated as FIG. 6B as will be explained below.
  • FIG. 6B is a schematic block diagram illustrating the principle of the bi-directional ring oscillator 421 in accordance with a preferred embodiment of the present invention.
  • the bi-directional ring oscillator 421 includes a plurality of unit bi-directional delays and the bi-directional inverter which are connected in a ring fashion, and two counters. Each of the counters serves to count the number of times that a signal is circulated through the ring oscillator.
  • a simplified bi-directional ring oscillator has the ability to act as the conventional bi-directional delay with a long length.
  • the present invention requires only one bi-directional inverter, a very small number of unit bi-directional delays and two counters, thereby drastically reducing chip area requirements and covering even low frequency applications (i.e., a large clock cycle), while maintaining the merits of the linear bi-directional delay block. Further, since the bi-directional ring oscillator oscillates on its own, what is needed is a reset operation before that the first start signal START_A is input.
  • FIG. 7A is a connection diagram of the unit bi-directional delay 426 in a first stage in accordance with the present invention.
  • the unit bi-directional delay 426 used in the present invention includes a first to a fourth three-phase buffer 700 , 710 , 720 and 730 , and a PMOS transistor 740 .
  • the first three-phase buffer 700 receives the output of a unit bi-directional delay in the previous stage to produce a second output signal B m , wherein the gate of a PMOS transistor is controlled by the first and second backward signals (BWD) and the gate of an NMOS transistor is controlled by the first and second forward signals (FWD) and the first and second start signals (START) for applying a start input to the bi-directional ring oscillator line forming a ring.
  • the second three-phase buffer 710 receives the second output signal B m to produce a first output signal S m+1 , wherein the gate of a PMOS transistor is controlled by the backward signal BWD and the gate of an NMOS transistor is controlled by the forward signal FWD.
  • the third three-phase buffer 730 receives the output of the unit bi-directional delay in the previous stage to produce a first output signal A m+1 , wherein the gate of a PMOS transistor is controlled by the forward signal FWD and the gate of an NMOS transistor is controlled by the backward signal BWD.
  • the fourth three-phase buffer 720 receives the first output signal A m+1 to produce the second output signal B m , wherein the gate of a PMOS transistor is controlled by the forward signal FWD and the gate of an NMOS transistor is controlled by the backward signal BWD.
  • the gate of the PMOS transistor 740 receives the first and second start signals START_A and START_B, and its source and drain are formed between a line input voltage and the second output signal B m .
  • FIG. 7B is a symbolic diagram of the unit bi-directional delay shown in FIG. 7A in accordance with the present invention.
  • FIG. 7B a configuration in which the inverters diametrically opposite each other is similar to that of the unit bi-directional delay proposed by FUJITSU Ltd., except that the PMOS transistor 740 is added for a reset operation.
  • FIG. 8A is a connection diagram of the unit bi-directional inverter 429 of present invention.
  • the unit bi-directional inverter 429 of the present invention includes a first and a second three-phase buffer 800 and 810 .
  • the first three-phase buffer 800 receives the first output signal A m of the unit bi-directional delay in the previous stage to produce a forward loop signal and the second output signals A m+1 and B m , wherein the gate of a PMOS transistor is controlled by the backward signal BWD and the gate of an NMOS transistor is controlled by the forward signal FWD.
  • the second three-phase buffer 810 receives a backward loop signal of the unit bi-directional delay in the previous stage to produce the second output signal A m+1 and the forward loop signal B m .
  • FIG. 8B is a connection diagram in which three unit bi-directional inverters are connected in series for simulation.
  • FIG. 9 is a timing diagram of signal waveforms in accordance with a preferred embodiment of the present invention.
  • the bi-directional ring oscillator is reset. If the start signal “Start” is rendered to logic high, the signal is transmitted in a first direction, and the forward counter 422 counts the number of rising edges of the transmitted signal based on a forward loop signal A 3 .
  • the signal is conversely transmitted to allow the backward counter to be activated.
  • the counter comparator 424 compares the outputs of the backward counter and the forward counter and produces a counter match signal “count_match” with a logic high value if the outputs are equal to each other. According to the counter match signal “count_match”, a rising edge of the output signal B 0 of the bi-directional ring oscillator is output as a final rising clock Rclk_DLL. Since one bi-directional ring oscillator produces one DLL clock every two clock cycles, attainment of one DLL per each clock cycle requires an additional bi-directional ring oscillator.
  • the present invention employs a bi-directional ring oscillator, a forward counter and a backward counter to thereby reduce chip area requirements, in contrast with the prior art delay locked loop, and operate in low frequency applications, which, in turn, achieve a fast locking and a reduced jitter.

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KR99-62227 1999-12-24
KR1019990062227A KR100318431B1 (ko) 1999-12-24 1999-12-24 양방향 오실레이터와 카운터를 이용한 지연고정루프
KR1999-62227 1999-12-24

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US20060087353A1 (en) * 2004-10-27 2006-04-27 Alessandro Minzoni Method and apparatus compensating for frequency drift in a delay locked loop
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KR100808052B1 (ko) 2005-09-28 2008-03-07 주식회사 하이닉스반도체 반도체 메모리 장치
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US20030218929A1 (en) * 2002-05-24 2003-11-27 Heiko Fibranz Circuit configuration having a flow controller, integrated memory device, and test configuration having such a circuit configuration
US6693846B2 (en) * 2002-05-24 2004-02-17 Infineon Technologies Ag Command controller for an integrated circuit memory device and test circuitry thereof
US20040150440A1 (en) * 2002-07-24 2004-08-05 Yoji Idei Clock synchronization circuit and semiconductor device
US6867626B2 (en) * 2002-07-24 2005-03-15 Elpida Memory, Inc. Clock synchronization circuit having bidirectional delay circuit strings and controllable pre and post stage delay circuits connected thereto and semiconductor device manufactured thereof
US20050028016A1 (en) * 2003-05-27 2005-02-03 International Business Machines Corporation Processing system and memory module having frequency selective memory
US7254729B2 (en) * 2003-05-27 2007-08-07 Lenovo (Singapore) Pte. Ltd. Processing system and memory module having frequency selective memory
US7230495B2 (en) 2004-04-28 2007-06-12 Micron Technology, Inc. Phase-locked loop circuits with reduced lock time
US20060198237A1 (en) * 2004-08-04 2006-09-07 Johnson James B Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
US7355922B2 (en) * 2004-08-04 2008-04-08 Micron Technology, Inc. Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
US20080225630A1 (en) * 2004-08-04 2008-09-18 Micron Technology, Inc. Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
US7480203B2 (en) 2004-08-04 2009-01-20 Micron Technology, Inc. Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
US20090141571A1 (en) * 2004-08-04 2009-06-04 Micron Technology, Inc. Method and Apparatus for Initialization of Read Latency Tracking Circuit in High-Speed DRAM
US7660187B2 (en) 2004-08-04 2010-02-09 Micron Technology, Inc. Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
US7046060B1 (en) 2004-10-27 2006-05-16 Infineon Technologies, Ag Method and apparatus compensating for frequency drift in a delay locked loop
US20060087353A1 (en) * 2004-10-27 2006-04-27 Alessandro Minzoni Method and apparatus compensating for frequency drift in a delay locked loop
US8710889B1 (en) * 2010-09-22 2014-04-29 Altera Corporation Apparatus for controllable delay cell and associated methods

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TW487923B (en) 2002-05-21
DE10064206B4 (de) 2018-03-29
JP4378560B2 (ja) 2009-12-09
KR100318431B1 (ko) 2001-12-24
KR20010064096A (ko) 2001-07-09
DE10064206A1 (de) 2001-07-26
JP2001251172A (ja) 2001-09-14
US20010022745A1 (en) 2001-09-20

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