US6340829B1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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US6340829B1
US6340829B1 US09/173,616 US17361698A US6340829B1 US 6340829 B1 US6340829 B1 US 6340829B1 US 17361698 A US17361698 A US 17361698A US 6340829 B1 US6340829 B1 US 6340829B1
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layer
region
film
insulating film
insulating
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Yuuichi Hirano
Yasuo Yamaguchi
Shigeto Maegawa
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique for improvement in characteristics of an input protection circuit in an LSI.
  • a well-known method for effectively enhancing a proof stress against variation in voltage amplitude of an input signal which is applied to a source/drain region is formation of a silicide protection.
  • This method is, for example, to form an SiO 2 film over a gate electrode and side walls and then forming silicide on silicide a surface portion of an n + -type layer uncovered with the SiO 2 film as shown in FIG. 33, thereby raising a resistance of the source/drain region near the gate electrode without forming silicide on the region.
  • the SOI layer is very thin (e.g., its thickness is about 1000 ⁇ )
  • the SOI layer is be etched in an etching to form the SiO 2 film for silicide protection. If the SOI layer is etched, too, part of the SOI layer becomes thin because of level difference and the silicide layer which should originally extend from a surface of the SOI layer to the inside thereof reaches an interface between the SOI layer and a buried oxide film, to disadvantageously cause a leakage current and remove the silicide film.
  • a series of steps shown in FIGS. 29 to 33 are carried out. Specifically, a gate electrode and source/drain regions are formed as shown in FIG. 29, and an SiO 2 film is deposited as shown in FIG. 30 . Next, a resist is formed on a portion of the SiO 2 film which is to serve as the silicide protection portion as shown in FIG. 31, and a dry etching is performed to form an SiO 2 film to serve as the silicide protection portion. After that, to unnecessary resist is removed. Then, a silicide layer is formed as shown in FIG. 34 .
  • the Si layer as the SOI layer is very thin, about 1000 ⁇ , the Si layer is also etched in the dry etching and as a result a level difference as shown in FIG. 34 is created locally in a surface of the Si layer.
  • the buried oxide film and a silicide layer come into contact as shown in FIG. 35 .
  • the silicide layer weakly adheres to the buried oxide film in this condition, there is a possibility that the silicide layer may be removed depending on the strength of thermal stress applied in later steps. Further, even if the silicide layer is not removed, a leakage current may be produced between two silicide layers through the buried oxide film, and therefore there may arise an appreciable influence on characteristics of a transistor such as malfunction in a transistor operation.
  • Japanese Patent Application Laid Open Gazette 64-20663 discloses that in a dry etching for forming a side wall of a gate electrode of a MOS transistor, an Si 3 N 4 film is formed as an etching stopper film in advance on a surface of a semiconductor layer to cover both sides of the gate electrode and a gate insulating film and then a side wall is so formed as to cover the Si 3 N 4 film.
  • This prior art which essentially suggests a side wall of double-layered structure consisting of the Si 3 N 4 film and the SiO 2 film, can not be an effective solution of the above problem.
  • the semiconductor device comprises: an underlying layer; a semiconductor layer provided on a surface of the underlying layer; a gate insulating film provided on a first region in a flat surface of the semiconductor layer; a gate electrode provided on a surface of the gate insulating film; a side wall provided on second and third regions adjacent to the first region in the flat surface of the semiconductor layer, covering side surfaces of the gate insulating film and side surfaces of the gate electrode; a first insulating film provided on fourth and fifth regions adjacent to the second and third regions, respectively, in the flat surface of the semiconductor layer, on surfaces of the side walls and on a surface of the gate electrode; a second insulating film provided on a surface of the first insulating film, being different in material from the first insulating film; a first impurity layer of the first conductivity type extending from a center portion of the first region to the inside of the semiconductor layer; a second impurity layer of the second conductivity type adjacent
  • the semiconductor device of the first aspect further comprises: a third insulating film provided on a surface of the second insulating film.
  • the first insulating film and the third insulating film are of the same material.
  • the first insulating film is an SiO 2 film.
  • the first insulating film is an Si 3 N 4 film.
  • the semiconductor device comprises: a semiconductor layer; a gate insulating film formed on a surface of the semiconductor layer; a gate electrode formed on a surface of the gate insulating film; a side wall formed on the surface of the semiconductor layer to cover side surfaces of the gate insulating film and side surfaces of the gate electrode; and first and second insulating layers formed on the surface of the semiconductor layer in this order by dry etching to cover surfaces of the side walls and a surface of the gate electrode, and in the semiconductor device, an etching rate of the second insulating layer is set larger than that of the first insulating layer in the dry etching.
  • a portion of the first insulating layer uncovered with the second insulating layer after the dry etching is removed by wet etching.
  • the first insulating layer comprises first and second insulating films of different materials, and the etching rate of the second insulating layer is set larger than that of the second insulating film adjacent to the second insulating layer.
  • the present invention is also directed to a method for manufacturing a semiconductor device.
  • the method comprises the steps of: (a) providing a semiconductor layer, a gate insulating film formed on a surface of the semiconductor layer, a gate electrode formed on a surface of the gate insulating film, a side wall formed on the surface of the semiconductor layer to cover side surfaces of the gate insulating film and side surfaces of the gate electrode; (b) forming a first insulating layer on surfaces of the side wall, a surface of the gate electrode and an exposed portion of the surface of the semiconductor layer; (c) forming a second insulating layer on a surface of the first insulating layer; (d) forming a resist layer on a surface of the second insulating layer and patterning the resist layer so as to be located above a surface region within a predetermined range surrounding a region in which the side wall is provided in the surface of the semiconductor layer; (e) etching the second and first insulating layers by dry etching with an etch
  • the first insulating layer comprises a first insulating film and a second insulating film
  • the etching rate of the second insulating layer is set larger than that of the second insulating film
  • the step (b) comprises the steps of (b-1) forming the first insulating film equivalent in material to the second insulating layer on the surface of the semiconductor layer; and (b-2) forming the second insulating film different in material from the second insulating layer on a surface of the first insulating film
  • the step (f) comprises the steps of (f-1) removing an exposed portion of the second insulating film after the dry etching by a first wet etching; and (f-2) removing an exposed portion of the first insulating film after the first wet etching by a second wet etching.
  • the second insulating film is an SiO 2 film.
  • the second insulating film is an Si 3 N 4 film.
  • the semiconductor device which has a silicide protection portion covering a gate insulating film, a gate electrode and a side wall covering the side surfaces of the gate insulating film and the gate electrode, has a characteristic feature that the silicide protection portion is of layered structure, consisting essentially of a plurality of insulating films.
  • the surface of the semiconductor layer has no level difference and is flat, and the film thickness of the semiconductor layer is uniform from the first region to the sixth region. Therefore, the bottom surface of the silicide layer provided on the sixth region and in the second impurity layer never reaches the underlying layer and the problems such as the generation of leakage current and the removal of silicide film never arise.
  • the semiconductor device of the fourth or fifth aspect has an advantage of using a flexible and practicable insulating film, such as an SiO 2 film or an Si 3 N 4 film, as a base.
  • the portion of the second insulating layer to be etched is removed and then the etching is stopped at the surface of the first insulating layer.
  • the first insulating layer can be used as an etching stopper layer and it is possible to prevent the surface of the semiconductor layer from being etched by dry etching in forming the first and second insulating layers.
  • the semiconductor device of the seventh aspect since only the portion of the first insulating layer uncovered with the second insulating layer is removed by wet etching, a structure where the first insulating layer is formed on the surface of the semiconductor layer and the second insulating layer is formed on the surface of first insulating layer is obtained. Therefore, the exposed surface of the semiconductor layer after the wet etching is not etched and a flat surface of the semiconductor layer can be obtained. That makes it possible, for example, to form the silicide layer only on the surface of the semiconductor layer and inside the semiconductor layer when the silicide layer is formed in the semiconductor device.
  • an etching stopper layer of triple-layered structure is achieved.
  • the first insulating layer can work as the stopper layer for the dry etching, it is possible to prevent the surface of the semiconductor layer from being etched in the dry etching step, and (ii) since the exposed portion of the first insulating layer after the step (e) is removed by wet etching, a flat surface of the semiconductor layer that has never been etched through the process can be eventually obtained. Since the silicide layer can be thereby formed only inside the semiconductor layer without coming into contact with the interface when the silicide layer is further formed in the semiconductor device, the problems such as the generation of leakage current and the removal of silicide film never arise.
  • the method of the tenth aspect has an advantage that the second insulating film far away from the surface of the semiconductor layer can work as the stopper layer for dry etching.
  • the method of the eleventh and twelfth aspects use the SiO 2 film and the Si 3 N 4 film as a base, it is possible to provide a flexible and practicable manufacturing technique.
  • the silicide protection layer causes no difference in level to be created in the surface of the semiconductor, a flat surface of the semiconductor layer can be obtained and a good silicide layer can be obtained.
  • An object of the present invention is to provide a semiconductor device in which a surface region of a semiconductor layer for forming a silicide layer and that for forming a silicide protection portion are even as one surface, and to provide a method for manufacturing the semiconductor device.
  • FIG. 1 is a cross section showing a semiconductor in accordance with a first preferred embodiment of the present invention
  • FIG. 2A is a plan view showing a semiconductor in accordance with the first preferred embodiment of the present invention.
  • FIGS. 2B-2D are cross-sectional views of the device shown in FIG. 2A;
  • FIGS. 3 and 4 are cross sections showing a first example
  • FIGS. 5 and 6 are cross sections showing a second example
  • FIGS. 7 and 8 are cross sections showing a third example
  • FIGS. 9 and 10 are cross sections showing a fourth example
  • FIGS. 11 to 28 are cross sections showing steps for manufacturing a semiconductor device in accordance with a second preferred embodiment of the present invention.
  • FIGS. 29 to 35 illustrate problems of the background art.
  • FIG. 1 is a cross section showing a structure of a MOSFET on an SOI layer which is an exemplary semiconductor device in accordance with the present invention
  • FIG. 2A is a plan view of the MOSFET of FIG. 1
  • FIG. 1 is a cross section taken along the line I-II of FIG. 2 A.
  • FIGS. 2B-2D are cross-sectional views of the device shown in FIGS. 2A, drawn through respective lines IIB—IIB, IIC—IIC and IID—IID.
  • FIGS. 1 and 2 show an Si single crystal wafer 1 , an underlying layer 2 which is a buried oxide film (BOX) and an SOI (Silicon On Insulator) layer or semiconductor layer 3 provided on a surface 2 S of the underlying layer 2 .
  • the SOI layer 3 is formed by SIMOX. Specifically, atoms of oxygen are injected into the Si single crystal wafer from its surface and the wafer is thereafter annealed at a constant temperature to diffuse the injected atoms of oxygen inside the wafer from its surface and the vicinity, thereby forming the SiO 2 film having a thickness of several thousand ⁇ inside the wafer.
  • the SOI layer 3 as the semiconductor layer having a thickness of about 1000 ⁇ is formed between the surface 2 S of the buried oxide film 2 and a surface 3 S of the Si single crystal wafer 1 .
  • the MOSFET is provided on the flat surface 3 S of the SOI layer 3 and inside the SOI layer 3 . Specifically, a gate insulating film 4 is formed on a first region R 1 (a center portion R 1 C, other than peripheral portions, which occupies most of the region R 1 , corresponds to a surface region of a p ⁇ layer 9 discussed later) in the uniformly flat surface 3 S, and further, a gate electrode or a control electrode 6 of polysilicon and the like is formed on a surface 4 S of the film 4 .
  • a side wall 5 is so formed as to cover side surfaces 6 W of the gate electrode 6 and side surfaces 4 W of the gate insulating film 4 on a second region R 2 and a third region R 3 adjacent to the first region R 1 inside the flat surface 3 S and on regions R 8 and R 9 where no p layer 9 is formed shown in FIG. 2 A.
  • the first impurity layer 9 (p ⁇ layer) having first impurities of the first conductivity type (p type) at relatively low concentration is formed inside the SOI layer 3 , extending from the center portion R 1 C of the first region R 1 in the flat surface 3 S to the second surface 2 S of the buried oxide film 2 immediately therebelow.
  • a second impurity layer 10 (e.g., source region) having second impurities of the second conductive type (n type) is so formed as to be adjacent to the first impurity layer 9 , extending from the regions in the flat surface 3 S, specifically one of peripheral portions RS 1 of the first region R 1 adjacent to the center portion R 1 C, the second region R 2 , a fourth region R 4 externally adjacent to the second region R 2 and a sixth region R 6 externally adjacent to the fourth region R 4 , to the surface 2 S of the buried oxide film 2 .
  • the second impurity layer 10 consists of ⁇ circle around (1) ⁇ an n ⁇ layer 14 having the second impurities at relatively low concentration, extending from the above one peripheral portion RS 1 of the first region R 1 and a portion R 21 of the second region R 2 having an interface with the side wall 5 to the inside of the layer 10 and ⁇ circle around (2) ⁇ an n + layer 12 having the second impurities at relatively high concentration, extending from the remainder of the second region R 2 (externally adjacent to the portion R 21 ) and the fourth region R 4 in the flat surface 3 S adjacent to the remainder of the region R 2 to the inside of the layer 10 .
  • a third impurity layer (e.g., drain region) having the second impurities of the second conductivity type is so formed as to sandwich the first impurity layer 9 with the second impurity layer 10 , extending from the regions in the flat surface 3 S, specifically the other peripheral portion RS 2 of the first region R 1 adjacent to the center portion R 1 C, the third region R 3 , a fifth region R 5 externally adjacent to the region R 3 and a seventh region R 7 externally adjacent to the fifth region R 5 , to the surface 2 S of the buried oxide film 2 .
  • a silicide protection portion 8 consisting of a plurality of layers is so layered on the flat surface 3 S as to cover the gate electrode 6 and the side wall 5 .
  • a first insulating film 81 is formed on the fourth region R 4 and the fifth region R 5 in the flat surface 3 S having no difference in level, surfaces 5 W of the side wall 5 and a surface 6 S of the gate electrode 6
  • a second insulating film 82 different in material from the film 81 is so formed on a surface 81 S of the film 81 as to cover the surface 81 S.
  • the films 81 and 82 are made of different materials.
  • the silicide protection portion 8 has the layered structure consisting of a plurality of insulating films and covers the regions R 1 to R 5 in the flat surface 3 S which are not covered with a silicide layer discussed later.
  • the portion 8 does not reach high-resistance portions 16 and 17 immediately below the regions R 4 and R 5 of the n + layers 12 and 13 in the second and third impurity layers 10 and 11 . Therefore, the high-resistance portions 16 and 17 of the n + layers 12 and 13 each have the same thickness as the layers 9 , 14 and 15 in the SOI layer 3 .
  • the thickness is represented as d 1 in FIG. 1 .
  • a first silicide layer 71 which is a silicified n + layer is formed on the sixth region R 6 in the flat surface 3 S and in the n + layer 12 of the second impurity layer 10 to a depth of d 2 ( ⁇ d 1 ) from the region R 6 .
  • a second silicide layer 72 which is a silicified n + layer is formed on the seventh region R 7 in the flat surface 3 S and in the n + layer 13 to the depth of d 2 from the region R 7 .
  • bottom surfaces 7 B of the first and second silicide layers 71 and 72 are located in the n + layers 12 and 13 without coming into contact with the surface 2 S, and the first and second silicide layers 71 and 72 serve as respective low-resistance portions (the sheet resistance is e.g., 10 ⁇ / ⁇ ) of the second and third impurity layers.
  • the sheet resistance of high-resistance portion in the n + layers 12 and 13 where no silicide layer 71 or 72 are formed is e.g., 100 ⁇ / ⁇ .
  • no portion in the SOI layer 3 is ever etched and the SOI layer 3 has a uniform thickness d 1 .
  • silicide layers 71 and 72 do not reach the interface (surface 2 S) between the SOI layer 3 and the underlying layer 2 . Therefore, the problems in the prior art, such as the generation of leakage current and the removal of silicide film are not caused at all.
  • an insulating film equivalent in quality to the first insulating film 81 may be formed as a third insulating film 83 on a surface 82 S of the second insulating film 82 .
  • more insulating films e.g., a fourth insulating film, a fifth insulating film and so on, may be used to constitute the silicide protection portion 8 of a plurality of films.
  • the above-discussed structure of the semiconductor device of this preferred embodiment can be specified as below from the viewpoint of manufacturing process.
  • the first and second insulating films 81 and 82 of FIG. 1 are formed in this order as first and second insulating layers to cover the surfaces 5 S of the side wall 5 , the surface 6 S of the gate electrode 6 and the uncovered flat surface 3 S.
  • the second insulating layer is first anisotropically etched by dry etching and the etched second insulating layer covers the surfaces 5 S and 6 S and the regions R 4 and R 5 .
  • a wet etching is performed on a range from an exposed surface of the first insulting film through the first insulating layer immediately therebelow to remove the portion.
  • the films 81 and 82 finally have the above-formed structure.
  • a selection ratio of the etching rates of the first and second insulating films is so set as to hold such a relation as (the etching rate of the second insulating film)>(the etching rate of the first insulating film).
  • the third insulating film 83 of FIG. 1 it is necessary to set the selection ratio, by appropriately choosing the etchant, so as to hold such a relation as (the etching rate of the third insulating film 83 )>(the etching rate of the second insulating film 82 ).
  • the third insulating film 83 acts as “the second insulating layer” and a combination unit of the second and first insulating films 82 and 81 acts as “the first insulating layer”.
  • an SiO 2 film for example, having flexibility may be used.
  • an SiN film a polysilicon film undoped with impurity or other insulating film may be used.
  • an Si 3 N 4 film which also has flexibility is used as the first and third insulating films 81 and 83 .
  • an SiO 2 film, a polysilicon film undoped with impurity or other insulating film may be used.
  • an Si 3 N 4 film 8 B is inserted into the SiO 2 film which corresponds to the prior-art silicide protection portion, being sandwiched by SiO 2 films 8 A 1 and 8 A 2 .
  • Such a structure can be achieved by setting the selection ratio of the SiO 2 film 8 A 2 and the Si 3 N 4 film 8 B as follows in the dry etching for the silicide protection portion 8 of layered structure of FIG. 4 . Specifically, when the etching rate of the Si 3 N 4 film 8 B is set smaller than that of the SiO 2 film 8 A 2 in the dry etching, the anisotropic etching is performed on the SiO 2 film 8 A 2 and then stopped at a surface of the Si 3 N 4 film 8 B.
  • an exposed portion of the Si 3 N 4 film 8 B other than a portion to form the silicide protection portion 8 is removed by wet etching with thermal phosphoric acid and a portion of the SiO 2 film 8 A 1 immediately therebelow is removed by wet etching, to form the silicide protection portion 8 .
  • Each thickness of the SiO 2 films 8 A 1 and 8 A 2 and the Si 3 N 4 film 8 B is in a range of several hundred ⁇ to several thousand ⁇ .
  • the Si 3 N 4 film 8 B is provided as the first insulating film and the SiO 2 film 8 A is provided thereon as the second insulating film.
  • a dry etching is performed on the SiO 2 film 8 A with the etching rate of the Si 3 N 4 film 8 B of FIG. 6 set smaller than that of the SiO 2 film 8 A, like the example 1.
  • the dry etching is stopped at the surface of an exposed surface of the Si 3 N 4 film 8 B and a portion of the Si 3 N 4 film 8 B other than the silicide protection portion 8 is removed by wet etching with thermal phosphoric acid.
  • the silicide protection portion 8 of FIG. 5 is formed.
  • Each thickness of the SiO 2 film 8 A and the Si 3 N 4 film 8 B is in a range of several hundred ⁇ to several thousand ⁇ .
  • the SiO 2 film 8 A is provided as the first insulating film under the Si 3 N 4 film 8 B as the second insulating film.
  • the etching rate of the SiO 2 film 8 SA is set smaller than that of the Si 3 N 4 film 8 B, and the SiO 2 film 8 A and the SiN film 5 B which are layered in the order of FIG. 8 are dry-etched. The dry etching is thereby stopped at the surface of the SiO 2 film 8 A, and a portion of the SiO 2 film 8 A other than the silicide protection portion 8 is removed by wet etching, to form the silicide protection portion 8 of FIG. 7 .
  • Each thickness of a lower layer, the SiO 2 film 8 A, and an upper layer, the SiN film 8 B, is in a range of several hundred ⁇ to several thousand ⁇ .
  • the Si 3 N 4 film 8 B 1 as the first insulating film and the SiN film 8 B 2 as the third insulating film sandwich the SiO 2 film 8 A as the second insulating film. It may be considered in this structure that the Si 3 N 4 film 8 B 2 acting as the second insulting layer is formed on a combination unit of the Si 3 N 4 film 8 B 1 and the SiO 2 film 8 A acting as the first insulating layer.
  • the selection ratio of the Si 3 N 4 film 8 B 2 and the SiO 2 film 8 A is so set as to hold such a relation as (the etching rate of the film 8 B 2 )>(the etching rate of the film 8 A), to control an etching for a source/drain region (see FIG. 10 ).
  • Each thickness of the SiO 2 film 8 A and the Si 3 N 4 films 8 B 1 and 8 B 2 is in a range of several hundred ⁇ to several thousand ⁇ .
  • MOSFET semiconductor device having the silicide protection portion as discussed in the first preferred embodiment
  • FIG. 11 shows a step of injecting a channel doping ion.
  • the silicon single crystal wafer 1 is prepared as a support substrate, an SiO 2 film 2 having a thickness of about 4000 ⁇ is formed by the above mentioned SIMOX in the silicon wafer 1 as the buried oxide film (underlying layer) and then the SOI layer 3 having a thickness of about 1000 ⁇ is formed.
  • the first impurity layer having the first impurities of the first conductivity type is formed in the SOI layer 3 .
  • What is used as the first impurity and its injection concentration depend on whether an nMOSFET or a pMOSFET is to formed.
  • a p-type impurity is used as the first impurity of the first conductivity type to be injected, and the SOI layer 3 is implanted with, for example, arsenic having a concentration of about 4E13 cm ⁇ 2 as the first impurity at an acceleration energy of 60 keV.
  • an n-type impurity is used as the second impurity of the second conductivity type, and the SOI layer 3 is implanted with, for example, boron having a concentration of about 4E13 cm ⁇ 2 at an acceleration energy of 10 keV.
  • FIG. 12 shows a step of depositing a gate oxide film (gate insulating film) and a polysilicon film for gate electrode.
  • a gate oxide film 4 A having a thickness of about 70 ⁇ and a polysilicon film 6 A having a thickness of about 2000 ⁇ are layered in this order on the flat surface 3 S of the SOI layer 3 .
  • FIG. 13 shows a step of injecting doping ions to form a gate electrode.
  • the polysilicon film 6 A of FIG. 12 becomes a conductive polysilicon film 6 B.
  • the film 6 A is implanted with phosphorus having a concentration of about 5E15 cm ⁇ 2 at an acceleration energy of 15 keV.
  • the film 6 A is implanted with boron having a concentration of about 5E15 cm ⁇ 2 at an acceleration energy of 10 keV.
  • FIG. 14 shows a step of dry etching for gate patterning. Specifically, a resist pattern 20 is formed in accordance with the gate pattern and a dry etching is performed with this pattern 20 as a mask, to form the gate oxide film 4 as the gate insulating film and the polysilicon film 6 as the gate electrode as shown in FIG. 14 .
  • FIG. 15 shows a step of removing the resist pattern 20 of FIG. 14 and injecting impurity ions for the source/drain.
  • an n-type impurity e.g., arsenic: 60 keV, about 4E13 cm ⁇ 2
  • a p-type impurity e.g., boron: 10 keV, about 4E13 cm ⁇ 2
  • FIG. 16 shows a step of depositing a SiO 2 film 5 A for the side wall.
  • the SiO 2 film 5 A having a thickness of about 800 ⁇ is formed on the flat surface 3 S of the SOI layer 3 , side surfaces of the gate oxide film 4 and surfaces of the polysilicon film 6 for the gate electrode.
  • FIG. 17 shows the second injection step of impurity ions for the source/drain after the dry etching for the SiO 2 film 5 A for the side wall.
  • the SiO 2 film 5 A of FIG. 16 is dry-etched to form the side wall 5 for covering both side surfaces of the gate insulating film 4 and the gate electrode 6 and after that, the second impurities (ions) of the second conductivity type are injected into the source/drain regions.
  • the second impurities (ions) of the second conductivity type are injected into the source/drain regions.
  • arsenic ions having a concentration of about 4E15 cm ⁇ 2 are injected at an acceleration energy of a 60 keV.
  • FIG. 18 shows a state where the first insulating layer 81 A is formed.
  • the first insulating layer 81 A is formed on the surfaces of the side wall 5 , the surface of the gate electrode 6 , and an exposed portion of the flat surface 3 S of the SOI layer 3 uncovered with the side wall 5 .
  • the layer 81 A is an SiO 2 film or an Si 3 N 4 film. If the Si 3 N 4 film is used, the Si 3 N 4 film must have a thickness of 3000 ⁇ or less, lest an stress between the Si 3 N 4 film and the SiO 2 film becomes large.
  • the second insulating layer 82 A is layered on a surface of the first insulting film 81 A.
  • an SiO 2 film for example, is used as the first insulating layer 81 A
  • an SiN film, an undoped polysilicon film or other insulating film is used as the second insulating layer 82 A.
  • an SiO 2 film, an undoped polysilicon film or other insulating film is used as the second insulating layer 82 A.
  • a resist layer (not shown) is formed on an entire surface of the second insulating layer 82 A, and as shown in FIG. 20, the resist layer is patterned to form a resist layer 21 which is located above a portion SR 1 covered with the side wall 5 and the gate insulating film 4 in the flat surface 3 S of the SOI layer 3 and above a surface region SR 2 within a predetermined range surrounding the portion SR 1 .
  • a wet etching is performed on an exposed portion of the first insulating layer 81 A uncovered with the second insulating layer 82 after the dry etching to remove the portion.
  • a wet etching is performed on an exposed portion of the first insulating layer 81 A uncovered with the second insulating layer 82 after the dry etching to remove the portion.
  • the resist layer 21 is removed.
  • the silicide protection portion 8 consisting of the first and second insulating layers 81 and 82 is formed on the flat surface 3 S to cover the gate electrode 6 and the side wall 5 as shown in FIG. 22 .
  • cobalt is sputtered on the exposed flat surface 3 S and the surface of the silicide protection portion 8 , to form a cobalt layer 70 (having a thickness of 120 ⁇ ).
  • this device is annealed (lamp annealing) in N 2 gas at about 800° C. for thirty seconds.
  • Co is removed from the SiO 2 film by means of immersion in an acid solution.
  • the cobalt silicide layers 71 and 72 (having a thickness of about 500 ⁇ ) are formed in the source/drain regions 10 and 11 uncovered with the silicide protection portion 8 .
  • the source/drain regions 10 and 11 have a uniform thickness and therefore the bottom surfaces of the cobalt silicide layers 71 and 72 never penetrate the interface 2 S between the SOI layer 3 and the underlying layer 2 , and a structure that works well as an input/output protection circuit can be achieved in the present device.
  • first insulating layer 81 ( 81 A) of FIG. 18 may be formed of at least double-layered structure. Then, discussion will be made below on a method for manufacturing the first insulating layer 81 of double-layered structure, consisting of the first insulating film 81 a and the second insulating film 82 a.
  • a step of FIG. 25 is further performed between the steps of FIGS. 18 and 19. Specifically, on a surface of the first insulating film 81 a formed in the step of FIG. 18, the second insulating film 82 a different in material therefrom is formed. By this formation, the first insulating layer 81 consisting of the films 81 a and 82 a is formed as shown in FIG. 19 .
  • the etching steps of FIGS. 21 and 22 are amended.
  • the selection ratio is set so that the etching rate of the second insulating layer 82 A equivalent in material to the first insulating film 81 a may be larger than that of the second insulating film 82 a , and with this selection ratio, the dry etching is performed.
  • the dry etching is performed.
  • FIG. 26 a portion of the second insulating film 82 a uncovered with the resist layer 21 is exposed and the dry etching is stopped.
  • the exposed portion of the second insulating film 82 a of FIG. 26 is removed by the first dry etching as shown in FIG. 27, and further the exposed portion of the first insulating film 81 a of FIG.
  • the silicide protection portion 8 is formed to have the first insulating layer 81 consisting of the first and second insulating films 81 a and 82 a shown in FIG. 22 and the second insulating layer 82 made of the third insulating film 83 a shown in FIG. 22 .
  • the “semiconductor layer” and the “underlying layer” of the present invention are not limited to the “SOI layer” and the “BOX layer”.
  • the present invention can be also applied to a case where a p-type MOSFET or an n-type MOSFET is formed in an n well or a p well.
  • the n well or the p well is the “underlying layer” in place of the “BOX layer”, and in the well, the source and drain regions and an n ⁇ layer or a p ⁇ layer serving as a channel sandwiched by the source and drain regions constitute the “semiconductor layer”.

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KR19990087000A (ko) 1999-12-15
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DE19853432A1 (de) 1999-11-18
US6699758B2 (en) 2004-03-02

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