US5327158A - Video processing apparatus - Google Patents

Video processing apparatus Download PDF

Info

Publication number
US5327158A
US5327158A US07/651,265 US65126591A US5327158A US 5327158 A US5327158 A US 5327158A US 65126591 A US65126591 A US 65126591A US 5327158 A US5327158 A US 5327158A
Authority
US
United States
Prior art keywords
data
background picture
character
picture
video
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US07/651,265
Other languages
English (en)
Inventor
Toyofumi Takahashi
Michitaka Miyoshi
Masahiro Otake
Satoshi Nishiumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nintendo Co Ltd
Ricoh Co Ltd
Original Assignee
Nintendo Co Ltd
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=16418397&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=US5327158(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Nintendo Co Ltd, Ricoh Co Ltd filed Critical Nintendo Co Ltd
Assigned to RICOH CO, LTD., 3-6, NAKAMAGOME 1-CHOME, OTA-KU, TOKYO, JAPAN reassignment RICOH CO, LTD., 3-6, NAKAMAGOME 1-CHOME, OTA-KU, TOKYO, JAPAN ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: MIYOSHI, MICHITAKA, NISHIUMI, SATOSHI, OTAKE, MASAHIRO, TAKAHASHI, TOYOFUMI
Application granted granted Critical
Publication of US5327158A publication Critical patent/US5327158A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00—Geometric image transformations in the plane of the image
    • G06T3/02—Affine transformations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/391—Resolution modifying circuits, e.g. variable screen formats
    • A—HUMAN NECESSITIES
    • A63—SPORTS; GAMES; AMUSEMENTS
    • A63F—CARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F2300/00—Features of games using an electronically generated display having two or more dimensions, e.g. on a television screen, showing representations related to the game
    • A63F2300/60—Methods for processing data by generating or executing the game program
    • A63F2300/66—Methods for processing data by generating or executing the game program for rendering three dimensional images

Definitions

  • the present invention generally relates to a video processing apparatus for use with a television set or the like which can process and display not only moving picture character symbols but also a background picture (or a still picture).
  • FIG. 17 An exemplary such prior art system may be represented by the block diagram shown in FIG. 17.
  • a video RAM (referred to as "VRAM” hereinafter) 102 comprising a random access memory (referred to as “RAM” hereinafter) as well as a CPU 103 are connected to a picture processing unit 101.
  • a main memory 104 storing image data for a background picture, moving picture character symbols, and control data for displaying and controlling the image data, is connected to the CPU 103.
  • the image data stored in the main memory 104 are transferred to the VRAM 102 through the picture processing unit 101.
  • the picture processing unit 101 reads data from the VRAM 102 and outputs the data as a video signal to a display device 105.
  • Display device 105 displays an image according to the data. Addresses of the VRAM 102 correspond to positions in the horizontal and vertical directions of the image displayed on the display device 105.
  • the above described moving picture character symbol image data and/or the background picture data are stored in respective addresses of the VRAM 102.
  • the above-described conventional television video game system is capable of rotating, enlarging or reducing background pictures for display.
  • the CPU 103 calculates (during a vertical blanking period), a new horizontal position and a new vertical position on the basis of an original position in the horizontal direction (referred to as “horizontal position” hereinafter) and an original position in the vertical direction (referred to as “vertical position” hereinafter) on a display screen of the image data of the original background picture stored in the VRAM 102.
  • the CPU 103 then writes the image data of the original background picture into addresses of the VRAM 102 which corresponds to the new horizontal position and the new vertical position as calculated.
  • the picture processing unit 102 sequentially converts the data written in the VRAM 102 into a video signal and outputs the same to the display device 105.
  • the above-described prior art shown in FIG. 17 has the following disadvantage:
  • the CPU 103 When a background picture is to be rotated or enlarged or reduced and displayed, the CPU 103 must calculate the new horizontal and vertical positions.
  • the rotation processing or the enlargement or reduction processing of the background picture typically takes a relatively long time. Accordingly, the throughput of the CPU 103 is reduced since the CPU 103 cannot perform very much other video processing.
  • the image data of the background picture stored in the VRAM 102 is rewritten. Accordingly, the image data of the original background picture before rotation processing (or the enlargement or reduction processing) typically cannot be preserved. Therefore, for example, when the original background picture is repeatedly rotated through 30° at a time and consequently, the original background picture is rotated through a total of 360° (one rotation), any any computing errors at the time of respective rotations accumulate so that a background picture is displayed in coordinate positions different from that of the original background picture and may be displayed as a figure having a shape different from that of the original background picture. Since the original background picture is not preserved as described above, such prior art has the disadvantage in that a background picture having the same shape as that of the original background picture may not be displayed in the original exact position.
  • An important object of the present invention is to provide a video processing apparatus capable of displaying a background picture having the same shape as that of the original background picture without deformation after rotation.
  • Another object of the present invention is to provide a video processing apparatus capable of performing rotation, enlargement and/or reduction processing of a background picture at relatively high speed without burdening a CPU while reproducing the original background picture without deformation.
  • Still another object of the present invention is to provide a video processing apparatus capable of achieving enlargement or reduction processing while rotating a background picture.
  • the present invention provides a storage device for storing image data of a background picture in address locations corresponding to display positions of the background picture before rotation processing.
  • An operation means operates, on the basis of rotation processing control data, on an address of the storage device corresponding to a display position of the background picture after performing background picture rotation processing.
  • a reading arrangement reads image data stored in addresses of the storage device specified by the operation means.
  • Video signal generating means generates a video signal on the basis of the image data read by the reading arrangement.
  • a storage means for storing image data representing a background picture in address locations corresponding to display positions before rotation, enlargement and reduction processing.
  • Operation means operate, on the basis of control data for rotation, enlargement, or reduction processing.
  • the operating means operate on an address of the storage means corresponding to a display position of the background picture after rotation, enlargement or reduction processing of the background picture.
  • a reading means reads the image data stored in the address of the storage means which is operated upon by the operation means.
  • Video signal generating means generates a video signal on the basis of the image data read by the reading means.
  • the storage means stores, before rotation (and/or enlargement or reduction) processing of a picture, image data representing the picture in an address corresponding to a display position of the picture before rotation (and/or enlargement or reduction) processing.
  • the operation means operates on an address of the storage means corresponding to a display position of the picture after performing the rotation (and/or enlargement or reduction) processing on the basis of the control data for the rotation (and/or enlargement or reduction) processing.
  • the reading means then reads the image data stored in the address of the storage means which is operated on by the operation means, and the video signal generating means generates a video signal on the basis of the image data read by the reading means. Consequently, a video signal at the time of performing at least one of the rotation processing and the enlargement or reduction processing of the picture is obtained according to the image data stored in the storage means.
  • a background picture having the same shape as that of the original background picture can be displayed without deformation before and after rotation.
  • rotation and/or enlargement or reduction processing of the background picture can be achieved at high speed without burdening the CPU, and the original background picture is not deformed.
  • FIG. 1 is a block diagram of an exemplary presently preferred television gaming apparatus according to one embodiment provided by the present invention
  • FIG. 2 illustrates an exemplary relation between a VRAM area and a display screen area of background picture data stored in a VRAM 7 shown in FIG. 1;
  • FIG. 3 is a schematic diagram showing an exemplary bit configuration of coordinates x and y indicating a position in the VRAM area shown in FIG. 2;
  • FIG. 4 is an exemplary memory map diagram of the VRAM shown in FIG. 1;
  • FIG. 5 is a schematic diagram showing exemplary storing conditions of color data of a background picture stored in the VRAM shown in FIG. 1;
  • FIG. 6 is a schematic diagram showing exemplary bit configurations of addresses and data in a background picture character area and a background picture screen area in the VRAM shown in FIG. 1;
  • FIG. 7 is a graphical diagram helpful in explaining the rotation processing and enlargement or reduction processing of a background picture
  • FIGS. 8, 8A and 8B are a detailed circuit diagram showing an exemplary background picture address control circuit 2 as shown in FIG. 1;
  • FIGS. 9 and 10, 10A and 10B are timing charts showing an exemplary operation of the background picture address control circuit shown in FIGS. 8A-8B;
  • FIG. 11 is a schematic diagram showing an example of the display of an original background picture
  • FIGS. 12 to 16 are schematic diagrams respectively showing examples of the display of a background picture in a case where the original background picture is enlarged, rotated and reduced or processed in these combinations.
  • FIG. 17 is a block diagram showing an exemplary prior art television gaming apparatus.
  • a television gaming machine is described, it should be noted that the present invention is also applicable to various video processing apparatus such as a personal computer or the like having as its object processing other than a game which is connected to a raster scan type CRT display.
  • FIG. 1 is a schematic block diagram of an exemplary television gaming apparatus 100 according to a presently preferred exemplary embodiment provided by the present invention.
  • This embodiment may generate video signals for display by a conventional raster scan type CRT display 8 such as an RGB monitor or a standard television receiving set.
  • a conventional raster scan type CRT display 8 such as an RGB monitor or a standard television receiving set.
  • One screen or frame of such a display 8 is typically divided into 256 ⁇ 256 dots (pixels).
  • 224 dots excluding the lines from the number of dots in the vertical direction
  • the presently preferred embodiment television gaming apparatus independently controls background picture generation and moving picture generation.
  • a background picture (or a still picture) forms a background which cannot be individually changed by an operation of a player.
  • a moving picture can be moved by an operation of the player or by the control of a CPU 2.
  • a picture processing unit 1 outputs a video signal for display by CRT display 8.
  • the picture processing unit 1 composes (and generates video signals specifying) the background picture and the moving picture.
  • the picture processing unit 1 includes a background picture address control circuit 24 which evaluates a read address of a VRAM 7 storing image data of the background picture by operation processing at the time of rotation and/or enlargement or reduction processing of the background picture; and changes the read address without changing the image data to perform rotation and/or enlargement or reduction processing.
  • Television gaming machine 100 includes a read-only memory (ROM) 3, a RAM 4 and a keyboard (user controls) 5 connected (through an address bus 11, a data bus 12 and a control bus 13) to a CPU 2 for carrying out a variety of television gaming machine control operations.
  • ROM read-only memory
  • RAM 4 random access memory
  • keyboard 5 keyboard (user controls) 5 connected (through an address bus 11, a data bus 12 and a control bus 13) to a CPU 2 for carrying out a variety of television gaming machine control operations.
  • the ROM 3 in the preferred embodiment is used for storing program data for controlling the television gaming machine, data required to execute the program, and character data.
  • the ROM 3 is contained in, for example, a cartridge 3a attachable to and detachable from the television gaming machine 100.
  • This program data includes data for determining what type of moving character and/or background character is to be displayed, at what time the character is to be displayed, and in which coordinate position on a screen the character is to be displayed, as well as data for rotation, enlargement and reduction processing, etc. For each moving character to be displayed moving picture attribute data is associated with each character.
  • Such moving picture attribute data includes: horizontal position data (Hc: 8 bits) for designating the character horizontal position, vertical position data (Vc: 8 bits) for designating the character vertical position, a character code (9 bits) for designating the type of character, a pallet code (3 bits) for designating a color pallet, a flip code (2 bits) for specifying display of a character reversed in the vertical and/or horizontal directions, a size code (1 bit) for designating the dot size of a character, and priority data (2 bits) for designating priority over a background picture. For each background character to be displayed the following data is associated with each character: a character code (8 bits) for designating the type of character, color data (8 bits) for each of pixels constituting a character, etc.
  • a background character code corresponding to each address of the background picture is designated as data for displaying one background picture so as to determine which background character is to be written, in which address out of addresses in the vertical and horizontal directions in a VRAM area (as described later) the background character is to be written and consequently, whether or not the background character is to be displayed in a desired position (coordinates) on a screen corresponding to the address.
  • the RAM 4 is used as a working area by the above described CPU 2.
  • the keyboard 4 is used for player input for controlling moving characters.
  • a CPU interface circuit 21 included in the picture processing unit 1 is connected to the CPU 2 through the address bus 11, the data bus 12 and the control bus 13.
  • a reference signal generator 6, a VRAM 7 including two RAMS (7a, 7b), and a CRT display 8 such as an RGB monitor or a standard television receiving set are connected to the picture processing unit 1.
  • the picture processing unit 1 under the control of CPU 2, is used for transferring image data of moving picture character symbols and background picture character symbols to the VRAM 7 during a vertical blanking period or at a predetermined transfer time.
  • the picture processing unit 1 is also used for reading the image data of the moving picture and/or the background picture stored in the VRAM 7. Such reading may be without any modification, or by outputting image data obtained by performing rotation, enlargement and reduction processing.
  • PPU 1 converts the image data into an RGB signal and/or an NTSC color signal and outputs the same to display B.
  • Picture processing unit 1 includes the CPU interface 21, a moving picture address control circuit 22, a background picture address control circuit 24, a VRAM interface 27 and a color signal generating circuit 28 which are connected to the CPU interface 21 through a data bus 14.
  • An address bus 15 is connected to the moving picture address control circuit 22.
  • the address bus 15 and a further data bus 16 are connected to the background picture address control circuit 24 and the VRAM interface 27.
  • the address bus 15 and the data bus 16 respectively comprise dual address buses 15a and 15b and dual data buses 16a and 16b respectively corresponding to the two VRAMs 7a and 7b.
  • a moving picture data processing circuit 23 and a background picture data processing circuit 25 are together connected to the data bus 16.
  • Video processing relating to the moving picture character symbols is performed by the moving picture address control circuit 22 and the moving picture data processing circuit 23.
  • Video processing concerning the background picture character symbols is performed by the background picture address control circuit 24 and the background picture data processing circuit 25.
  • Outputs of the moving picture data processing circuit 23 and the background picture data processing circuit 25 are applied to a priority control circuit 26.
  • An output of the priority control circuit 26 is converted into an RGB signal by the color signal generator 28 and can be directly applied to the RGB monitor 8a.
  • the priority control circuit 26 above is also converted into an NTSC color television signal by an NTSC encoded 29 and output to the standard television receiving set 8b from an output terminal 43.
  • the picture processing unit 1 also includes a timing signal generator 30 and an HV counter 31.
  • the timing signal generator 30 generates various timing signals on the basis of a 21.447 MHz clock signal, a vertical synchronization signal and a horizontal synchronization signal output from the reference signal generator 6.
  • the HV counter 31 generates count data H c and V c for respectively designating the display positions in the horizontal and vertical directions within a display screen area 41 shown in FIG. 2 in response to the clock signal, the vertical synchronization signal and the horizontal synchronization signal from the reference signal generator 6.
  • FIG. 2 is a diagram showing the relation between a display screen area of the CRT display 8 and a background picture storage area of the VRAM 7.
  • a display screen area 41 of the CRT display 8 may be constituted by, for example, a rectangle comprising 32 characters in the horizontal direction (breadth; x) and 28 characters in the vertical direction (length; y).
  • a background picture storage area (referred to as "VRAM area” hereinafter) 40 has no image data of a background picture in a portion which is not visible on a screen when the screen is reduced and displayed, a portion other than the background picture which is actually visible is displayed in black so that a screen having no background appears.
  • the VRAM area 40 is provided having an area several times the display screen area 41 in the vertical and horizontal directions.
  • a background character code to be displayed is written in an address designated by respective coordinate data in the x and y directions.
  • xc and yc (7 bits each) indicating the position of a character in the VRAM area 40
  • xd and yd (3 bits each) indicating the position of a dot in one character 52, as shown in FIG. 3.
  • the VRAM 7 in the preferred embodiment comprises two VRAMs 7a and 7b respectively having the same storage capacity, as shown in FIG. 4.
  • Each of the VRAMs 7a and 7b has addresses 0 to 32K. 8-bits of data can be stored at each of the addresses.
  • the VRAMs 7a and 7b are respectively divided into four 16K areas 51 to 54.
  • the areas 51 and 52 having addresses 0 to 16K are used for storing data associated with a background picture, and the areas 53 and 54 (having addresses (16K+1) to 32K) are used for storing data associated with a moving picture.
  • a lot of moving character data can be displayed in a period during which the same background picture is stored in the VRAM area 40.
  • the area 51 in the VRAM 7a is used as a character area for storing color data for a maximum of 256 background characters. As shown in FIG. 5, one character has bits corresponding to 8 ⁇ 8 (length ⁇ breadth) dots and includes 8-bit color data for each dot. Accordingly, one character requires a storage capacity of 512 bits (64 bytes). A character code is determined for each character.
  • the area 52 in the VRAM 7b has bytes corresponding to 128 ⁇ 128 (length ⁇ breadth) cells of the VRAM area 40 shown in FIG. 2 and is used as a screen area for storing character codes for the background picture in addresses designated by coordinates in the vertical and horizontal directions. An example of the formats of data written in the areas 51 and 52 is shown in FIG. 6.
  • the CPU interface 21 transfers, to the VRAM interface 27, data associated with a background character and a moving character by direct memory access during the vertical blanking period (or by a predetermined transfer instruction which forces transfer at other times).
  • CPU interface 21 generates latch signals LA1 to LA4, LA11, LA12, LA14 and LA15 (to be explained in conjunction with FIGS. 8A-8B) for transferring control data for rotation, enlargement and reduction to the background picture address control circuit 24.
  • the data for the background character and the moving character are written in advance in the VRAM 7 by the VRAM interface 27.
  • the moving picture address control circuit 22 comprises a moving picture attribute memory, an in-range detecting circuit and a moving picture address data generating circuit.
  • the details of the motion picture attribute memory, in-range detecting circuit and moving picture address generating circuit are known and may, for example, be as shown and described in Japanese Patent Laid-Open Gazette No. 118184/1984, which corresponds to applicants' assignees' U.S. Pat. No. 4,824,106, which patent is incorporated herein by reference.
  • Attribute data for 128 moving characters are transferred to the moving picture attribute memory from the CPU 2 through the CPU interface 21 and the data bus 14 and stored therein during a certain vertical blanking period.
  • the in-range detecting circuit retrieves data to be displayed in the next horizontal scanning from the moving picture attribute memory for each scanning line.
  • the moving picture address data generating circuit generates an address of the VRAM 7 indicating a reversed position in the display screen area 41 and outputs the same through the address bus 15 when V-flip data of the in-range detected attribute data is at the "H" level.
  • it outputs an address of the VRAM 7 corresponding to the display screen area 41 of character data to the VRAM 7 through the address bus 15 without any modification when the V-flip data is at the "L" level.
  • the VRAM 7 is responsive to the address so as to apply, to the moving picture data processing circuit 23 through the data bus 16, the color data (4 bits per dot) of moving pictures stored in the moving picture character areas 53 and 54 which correspond to addresses output from the moving picture address data generating circuit in the moving picture address control circuit 22. Furthermore, the moving picture address data generating circuit directly applies to the moving picture data processing circuit 23 the H-flip data (1 bit), the color pallet data (3 bits) and the priority data (2 bits) out of the attribute data of the in-range detected moving characters.
  • the moving picture data processing circuit 23 temporarily stores data of the next scanning line which is input during the horizontal blanking period and then, temporarily stores data of 9 bits per dot (excluding the H-flip data included in the data) in the order reverse to the input order when the H-flip data is at the "H" level to perform H-flip processing. On the other hand, this circuit 23 temporarily stores the 9-bit data in the input order when the H-flip data is at the "L" level.
  • the temporarily stored moving picture data of one scanning line is output to the priority control circuit 26 in synchronization with horizontal scanning on the basis of the count data H c output from the HV counter 31.
  • the background picture address control circuit 24 calculates a read address (16 bits) of a character code previously stored in the screen area 52 in the VRAM 7b corresponding to a dot of the background picture. This read address is calculated on the basis of the offset data H p and V p on the screen; the control data (including the H-flip data HF and the V-flip data VF) which are applied from the CPU 2; and the count data H c and V c applied from the HV counter 31. The address control circuit 24 then applies the address to the VRAM 7b through the address bus 15b.
  • the background picture address control circuit 24 calculates a read address of a character code corresponding to a dot of the background picture at the time of rotation and enlargement or reduction on the basis of: the offset data H p and V p on the screen; the H-flip data HF; the V-flip data VF; and parameter data (including processing constants A, B, C and D at the time of rotation and enlargement or reduction which are applied from the CPU 2); and the count data H c and V c applied from the HV counter 31.
  • the address control circuit 24 then applies the address to the VRAM 7b.
  • the principle of the operation processing for rotation, enlargement and reduction will be described below with reference to FIG. 7.
  • the background picture address control circuit 24 calculates a character code read address corresponding to one dot of a background picture after performing scrolling processing of the screen on the basis of the offset data H p and V p on the screen applied from the CPU 2. At the same time, the background picture address control circuit 24 calculates a character code read address corresponding to one dot of the background picture after performing H-flip processing (when the H-flip data HF is at the "H" level), while calculating a read address of a character name corresponding to one dot of the background picture after performing V-flip processing (when the V-flip data VF is at the "H" level).
  • the most significant two bits of the 16-bit read address data calculated by the background picture address control circuit 24 are "00" and the last significant 14 bits thereof are position data xc and yc (7 bits each) of a character corresponding to a display position of the background picture, shown in FIG. 6.
  • the VRAM 7b applies a character code stored in the address applied from the background picture address control circuit 24 to the background picture address control circuit 24 through the data bus 15b.
  • the background picture address control circuit 24 applies to the VRAM 7a through the address bus 15a an address comprising the most significant two bits "00", a 8-bit character code and the position data yd (3 bits) and xd (3 bits) of a dot corresponding to a display position of the background picture.
  • the VRAM 7a reads the 8-bit color data stored in the address applied from the background picture address control circuit 24 and applies the same to the background picture data processing circuit 25 through the data bus 16a.
  • the background picture data processing circuit 25 latches the color data of 8 bits per dot as input and then, applies the 8-bit color data to the priority control circuit 26 on the basis of the count data H c output from the HV counter 31.
  • the priority control circuit 26 determines the priority between the 7-bit moving picture data input from the moving picture data processing circuit 23 and the 8-bit background picture data input from the background picture data processing circuit 25 on the basis of priority data, and outputs higher-priority data out of the moving picture data and the background picture data to the color signal generator 28. For example, the priority control circuit 26 outputs background picture data comprising the most significant three bits "000” and 8-bit color data to the color signal generator 28 when the priority data is "00", while outputting moving picture data of a total of 7 bits (comprising 3-bit color pallet data and 4-bit color data) to the color signal generator 28 when the priority data is "01".
  • the color signal generator 28 includes a color pallet table composed of a RAM having 8-bit addresses.
  • the color generator RAM stores color signal data applied from the CPU 2 in the color pallet table during the vertical blanking period.
  • the color signal generator 28 reads the color signal data stored in a corresponding address of the color pallet table on the basis of the 8-bit moving picture data or background picture data input from the priority control circuit 26 and then, converts the color signal data into an RGB signal of 5 bits for each color.
  • the color signal generator 28 directly outputs the RGB signal to the RGB monitor 8a in synchronization with the count data H c and V c applied from the HV counter 31 and at the same time, outputs the same to the NTSC encoder 29.
  • the NTSC encoder 29 carries out digital-to-analog conversion of the RGB signal for each color and then, converts the RGB signal into the NTSC color television signal and outputs the same to the standard television receiving set 8b from the output terminal 9.
  • FIG. 7 is a diagram for explaining the principle of rotation processing and the enlargement or reduction processing of a background picture performed by the background picture address control circuit 24.
  • x is a coordinate for each dot in the horizontal direction on the screen of the CRT display 8 and y is a coordinate for each dot in the vertical direction.
  • the y direction is reverse to that shown in FIG. 2 (i.e., increasing y is up toward the top of the page in FIG. 7).
  • P(X 1 , Y 1 ) be coordinates of the original background picture before the background picture address control circuit 24 performs rotation, enlargement or reduction processing
  • Q'(X 2 ', Y 2 ') be coordinates of the background picture in a case where the original background picture is rotated around coordinates R(X 0 , Y 0 ) through an angle ⁇ .
  • the coordinates P (X 1 , Y 1 ) of the original background picture are expressed by the following equations (13) and (14) if the above described offset data H p and V p in the VRAM area 40 shown in FIG. 2 and the count data H c and V c output from the VH counter 31 are used:
  • H c ⁇ A and H c ⁇ C are terms which are changed for each dot on the screen, and terms other than H c ⁇ A and H c ⁇ C (that is, terms in parenthesis) are terms which are not changed during one scanning line. Consequently, the terms H c ⁇ A and H c ⁇ C must be calculated for each dot in the horizontal scanning period. On the other hand, the terms other than H c ⁇ A and H c ⁇ C need not be calculated during the horizontal scanning period. It is rather difficult to calculate the terms during the very short time available for each dot of horizontal scanning.
  • the terms are collectively calculated before scanning of one line is started, (i.e., they are preliminarily processed). Therefore, in order to calculate terms to be preliminarily processed with the equations (15) and (16) using simple circuits, the equations are replaced with the following equations (17) to (24) and operated on in the following step-by-step manner:
  • FIGS. 8A and 8B are a detailed circuit diagram showing the background picture address control circuit 24.
  • This background picture address control circuit 24 evaluates coordinates (X 2 , Y 2 ) at the time of rotation and enlargement or reduction of a background picture by a matrix operation using the above described equation (1) and then, outputs its coordinate data as a read address of the screen area 52 and a read address of the character area 51.
  • the background picture address control circuit 24 includes registers FF1 to FF23 each composed of a plurality of delay-type (D-type) flip-flops. Each of the registers FF1 to FF23 latches data applied to its input terminal at a time when a latch signal is applied, and outputs the data to its input terminal.
  • inverted clock signals obtained by inverting a clock "10MCK” of 10.739 MHz output from the timing signal generator 30 are respectively input to the registers FF13 to FF19.
  • Inverted clock signals obtained by inverting a clock "5MCK” of 5.369 MHz output from the timing signal generator 30 are respectively input to the registers FF18, FF20, FF21, FF22 and FF23.
  • 16-bit constant data A, B, C and D applied from the CPU 2 through the CPU interface circuit 21 and the data bus 14 are respectively latched in the registers FF1 to FF4 at times when corresponding latch signals LA1 to LA4 are applied by CPU 2.
  • Their latched data are applied to input terminals a, b, c and d of a switching device SW1.
  • the switching device SW1 selects any one of the latched data input to the input terminals a, b, c and d and outputs the same to input terminals a of a multiplier MPY on the basis of an XS signal output from timing signal generator 30.
  • Count data H c output from the HV counter 31 is input to an exclusive OR circuit XOR1.
  • the register FF5 latches the 8-bit count data V c output from the HV counter 31 and outputs the same to an exclusive OR circuit XOR2.
  • the registers FF6 and FF7 respectively latch the 1-bit H-flip data HF and the 1-bit V-flip data VF applied from the CPU 2 on a leading edge of a machine clock of the CPU 2 and respectively output, to the exclusive OR circuits XOR1 and XOR2, 8 bits of data having the same level as the H-flip data HF; and 8 bits of data having the same level as V-flip data VF.
  • the exclusive OR circuits XOR1 and XOR2 respectively include eight exclusive OR gates each having first and second inputs. Respective bits of the count data H c are applied as respective first inputs of each of the eight exclusive OR gates included in the exclusive OR circuit XOR1, and corresponding bits of the data in the register FF6 are applied as the respective second inputs thereof. Respective bits of the count data V c are applied as respective first inputs of the eight exclusive OR gates included in the exclusive OR circuit XOR2, and corresponding bits of the data in the register FF7 are applied as the respective second inputs thereof.
  • the respective eight exclusive OR gates included in the exclusive OR circuits XOR1 and XOR2 perform an exclusive OR operation on their respective inputs, and apply 8-bit data which are the results of the operation to input terminals a and input terminals b of the switching device SW2 (directly or through the register FF8).
  • Input terminals a and b of switching device SW2 are 11 bits wide, and the most significant three bits of each of the input terminals a and b are connected to ground ("000").
  • the switching device SW2 includes input terminals c and d, and 11-bit data from the registers FF9 and FF10 are respectively input to the input terminals c and d.
  • the register FF9 latches data of the least significant 11 bits (E1) of 18-bit data applied from an adder ADD on a leading edge of a latch signal LA9 output from the timing signal generator 30 and applies its latching data to the input terminals c of the switching device SW2.
  • the register FF10 latches data of the least significant 11 bits (E2) of the 18-bit data applied from the adder ADD on the leading edge of a latch signal LA10 output from the timing signal generator 30 and applies its latched data to the input terminals d of the switching device SW2.
  • the switching device SW2 selects any one of the data input to the input terminals a, b, c and d on the basis of a YS signal output from the timing signal generator 30, and applies the same to input terminals b of the multiplier MPY.
  • the multiplier MPY multiplies any one of the data A to D input to the input terminals a by any one of the data E1, E2 and V c input to the input terminals b to calculate the second term in any one of the equations (19) to (24) and applies data which are the results of the multiplication to input terminals c of a switching device SW3 through the register FF13.
  • the register FF11 latches offset data H p (10 bits) in the x direction applied from the CPU 2 on the leading edge of the machine clock and applies the same to input terminals a of the switching device SW3.
  • the register FF12 latches offset data V p (10 bits) in the y direction applied from the CPU 2 on the leading edge of the machine clock and applies the same to input terminals b of the switching device SW3.
  • the most significant six bits and the least significant two bits of each of the input terminals a and b of the switching device SW3 are connected to ground.
  • the least significant two bits of the data input to each of the input terminals of the switching device SW3 correspond to data after the decimal point.
  • the switching device SW3 selects one of the data input to the input terminals a, b and c on the basis of an AS signal output from the timing signal generator 30 and applies the same to input terminals a of the adder ADD.
  • the register FF14 latches the position data x 0 in the x direction of the original background picture applied from the CPU 2 (the least significant eight bits of the data bus 14) on the leading edge of the machine clock and then, applies data of a total of 10 bits including the most significant two bits "00" and its latched data to input terminals a of a switching device SW4.
  • the register FF15 latches the position data Y 0 in the y direction of the original background picture applied from the CPU 2 (the most significant two bits from the above described data x 0 of the data bus 14) on the leading edge of the machine clock and then, applies data of a total of 10 bits (including the most significant eight bits "00000000" and its latched data) to input terminals b of the switching device SW4.
  • the most significant six bits and the least significant two bits of each of the input terminals a and b of the switching device SW4 are connected to ground.
  • the least significant two bits of the data input to each of the input terminals of the switching device SW4 correspond to data after the decimal point.
  • the register FF16 latches 18-bit data output from the adder ADD on a leading edge of a clock CK16 output from the timing signal generator 30 and applies the same to input terminal c of the switching device SW4.
  • the register FF17 latches 18-bit data output from the adder ADD on a leading edge of a clock CK17 output from the timing signal generator 30 and applies the same to input terminals d of the switching device SW4.
  • the switching device SW4 applies 18-bit data out of the data input to the input terminals a, b, c and d to an exclusive XOR circuit XOR3 on the basis of a signal BS output from the timing signal generator 30.
  • the exclusive OR circuit XOR3 includes 18 exclusive OR gates. Corresponding bits of the data in the switching device SW4 are applied as respective one inputs of the exclusive OR gates, and an ADS signal output from the timing signal generator 30 is applies as the respective other inputs thereof.
  • a certain bit of the ADS signal is input to a carry-in terminal of the adder ADD.
  • this bit of the ADS signal input to the carry-in terminal of the adder ADD is at the "H” level
  • the ADS signal input to the respective other input terminals of the exclusive OR gates in the exclusive OR circuit XOR3 is a signal in which all 18 bits are at the "H” level.
  • the bit of the ADS signal input to the carry-in terminal of the adder ADD is at the "L” level
  • the ADS signal input to the respective other input terminals of the exclusive OR gates in the exclusive OR circuit XOR3 is a signal in which all 18 bits are at the "L” level.
  • the exclusive OR circuit XOR3 operates in the same manner as the exclusive OR circuits XOR1 and XOR2. That is, the exclusive OR circuit XOR3 performs an exclusive OR operation of data input to one input terminal and data input to a corresponding other input terminal with respect to each bit and applies the results of the operation to input terminals b of the adder ADD.
  • the adder ADD adds both the data input to the input terminals a and b and further adds one of the results of the addition only when the ADS signal at the "H" level is input to the carry-in terminal. Thereafter, out of the results of the addition, 18-bit data is stored in the registers FF16 and FF17, data of the least significant 11 bits is stored in the registers FF9 and FF10, 10-bit data is stored in the registers FF18 and FF19, and data of the least significant eight bits is stored in the register FF21.
  • the multiplier MPY and the adder ADD repeatedly perform a multiplication operation or an addition operation of two data (coordinate data, constant data or data of the results of an operation obtained immediately before) applied by switching of the switching devices SW1 to SW4 in a time shared manner to sequentially perform operations expressed by the equations (17) to (24) and finally perform operations expressed by the equations (15) and (16).
  • the rotation and/or the enlargement or reduction processing can be achieved using a common circuit by changing the constant data.
  • the register FF18 latches the 10-bit data as input and then, outputs data yc of the most significant seven bits as address data of the third to eighth bits from the most significant bit of the address bus 15b through a tri-state buffer amplifier (referred to as "buffer amplifier” hereinafter) BA2 and applies data yd of the least significant three bits to the register FF22.
  • the register FF19 latches the 10-bit data as input and then, applies the same to the register FF20.
  • the register FF20 latches the 10-bit data as input and then, outputs data xc of the most significant seven bits as address data of the least significant seven bits of the address bus 15b through a buffer amplifier BA3 and applies data xd of the least significant three bits to the register FF22.
  • the register FF21 latches the 8-bit character code input from the VRAM 7b through the data bus 16b and then, outputs the same as address data of the third to seventh bits from the most significant bit of the address bus 15b through a buffer amplifier BA5.
  • the register FF22 latches the two 3-bit data yd and xd as input and then, outputs the data as address data of the least significant six bits of the address bus 15a through the register FF23 and a buffer amplifier BA6.
  • input terminals of two bits of the buffer amplifier BA1 are connected to ground, and output terminals (2 bits) of the buffer amplifier BA1 are connected to the most significant two bits of the address bus 15b.
  • Input terminals of two bits of the buffer amplifier BA4 are connected to ground, and output terminals (2 bits) of the buffer amplifier BA4 are connected to the most significant two bits of the address bus 15.
  • FIGS. 9 and 10A and 10B are timing charts for explaining an operation of the enlargement or reduction and/or the rotation processing of a background picture which characterizes this embodiment.
  • FIG. 9 shows one horizontal scanning period and horizontal blanking period
  • FIGS. 10A and 10B show the periods of preliminary processing and an example of a part of real-time processing in a case where an H count value is 9 to 17.5.
  • FIGS. 1 to 10 the detailed operation of the enlargement or reduction and/or the rotation processing of a background picture.
  • the constants A, B, C and D are calculated in the CPU 2 using the above described equations (2) to (5) on the basis of ⁇ , ⁇ and ⁇ as described above.
  • Data indicative of the previously calculated constants A, B, C and D are input to the flip-flops FF1 to FF4 from the CPU 2 through the CPU interface circuit 21 and the data bus 14 to be latched therein.
  • the above described offset data H p and V p on the screen, the data x 0 and Y 0 representing the above described reference coordinates, and the H-flip data HF and the V-flip data VF with respect to the background picture are respectively output from the CPU 2 and input to the flip-flops FF11, FF12, FF14, FF15, FF6 and FF7 through the CPU interface circuit 21 and the data bus 14 to be latched therein.
  • the data H c input from the HV counter 31 is reversed by the exclusive OR gate XOR1 and output to the input terminals a of the switching device SW2 when the H-flip data HF is at the "H" level.
  • the data H c input from the HV counter 31 is output to the input terminals a of the switching device SW2 through the exclusive OR gate XOR1 without any modification when the H-flip data HF is at the "L" level.
  • the data V c input from the HV counter 31 and latched in the flip-flop FF5 during processing of one scanning line is reversed by the exclusive OR gate XOR2 and input to the flip-flop FF8 to be latched therein when the V-flip data VF is at the "H" level.
  • the above data V c is input to the flip-flop FF8 through the exclusive OR gate XOR2 without any modification to be latched therein when the V-flip data VF is at the "L” level.
  • H-flip and V-flip operations of a background picture are respectively performed by reversing operations of the above described exclusive OR gates XOR1 and XOR2.
  • the data output from the above described exclusive OR gates XOR1 and XOR2 are respectively referred to as data H c and V c irrespective of whether or not they are reversed, for convenience of description.
  • the character name and the color data of the original background picture are stored in the background picture screen area 52 in the VRAM 7b and the background picture character area 51 in the VRAM 7a, respectively.
  • the times when a clock 10MCK of 10.739 MHz the symbol "/" in front of a symbol is used hereinafter in place of the conventional bar above the symbol which is used in FIG. 8B) output from the timing signal generator 30 rise are represented by t1, t2, t3, . . . , t20, . . . for convenience of description.
  • preliminary processing takes place from the time t1 to the time t9 and includes calculating constants E1 to E8 during the vertical blanking period before the period an image signal, i.e., a video signal is output from the picture processing unit 1.
  • Processing after the time t9 is real-time processing performed in synchronization with the generation and the display of an image signal which is a digital signal of RGB representative of a video signal.
  • Such real-time processing includes evaluating coordinates Q (X 2 , Y 2 ) of the background picture at the time of the rotation and the enlargement or reduction on the basis of the constants calculated in the preliminary processing and the count data H c and V c , outputting an address of the background picture screen area 52 in the VRAM 7b and then, outputting an address of the background picture character area 51 in the VRAM 7a on the basis of a character code read from the area 52.
  • both the switching devices SW3 and SW4 are switched to their input terminal a.
  • the data H p is input to the input terminals a of the adder ADD from the flip-flop FF11 through the switching device SW3.
  • the data x 0 is input to the input terminals b of the adder ADD from the flip-flop FF14 through the switching device SW4 and the exclusive OR gate XOR3.
  • the ADS signal is at the "H" level.
  • the data E1 is input to the flip-flop FF9 to be latched therein on the leading edge of the latch signal LA9 at the time t2.
  • the switching devices SW1 and SW2 are respectively switched to its input terminals a and its input terminals c.
  • the data A is input to the input terminals a of the multiplier MPY from the flip-flop FF1 through the switching device SW1.
  • the data E1 is input to the input terminals b of the multiplier MPY from the flip-flop FF9 through the switching device SW2.
  • the multiplier MPY performs an operation of data A ⁇ E1 and outputs the results of the operation.
  • the data A ⁇ E1 is input to the flip-flop FF13 to be latched therein on the leading edge of the clock/10MCK at the time t3.
  • both the switching devices SW3 and SW4 are switched to their input terminals b.
  • the data V p is input to the input terminals a of the adder ADD from the flip-flop FF11 through the switching device SW3.
  • the data Y 0 is input to the input terminals b of the adder ADD from the flip-flop FF15 through the switching device SW4 and the exclusive OR gate XOR3.
  • the ADS signal is at the "H" level.
  • the data E2 is input to the flip-flop FF10 to be latched therein on the leading edge of the latch signal LA10 at the time t3.
  • both the switching devices SW1 and SW2 are switched to their input terminals d.
  • the data D is input to the input terminals a of the multiplier MPY from the flip-flop FF4 through the switching device SW1.
  • the data E2 is input to the input terminals b of the multiplier MPY from the flip-flop FF10 through the switching device SW2.
  • the multiplier MPY performs an operation of data D ⁇ E2 and outputs the results of the operation.
  • the data D ⁇ E2 is input to the flip-flop FF13 to be latched therein on the leading edge of the clock /10MCK at the time t4.
  • the switching devices SW3 and SW4 are respectively switched to input terminal c and its input terminal a.
  • the data A ⁇ E1 is input to the input terminals a of the adder ADD from the flip-flop FF13 through the switching device SW3.
  • the data x 0 is input to the input terminals b of the adder ADD from the flip-flop FF14 through the switching device SW4 and the exclusive OR gate XOR3.
  • the ADS signal is at the "L" level.
  • the data E3 is input to the flip-flop FF16 to be latched therein on the leading edge of the clock 16CK at the time t4.
  • the switching devices SW1 and SW2 are respectively switched to input terminals b and input terminals d.
  • the data B is input to the input terminals a of the multiplier MPY from the flip-flop FF2 through the switching device SW1.
  • the data E2 is input to the input terminals b of the multiplier MPY from the flip-flop FF10 through the switching device SW2.
  • the multiplier MPY performs an operation of data B ⁇ E2 and outputs the results of the operation.
  • the data B ⁇ E2 is input to the flip-flop FF13 to be latched therein on the leading edge of the clock /10MCK at the time t5.
  • the switching devices SW3 and SW4 are respectively switched to input terminals c and input terminals b.
  • the data D ⁇ E2 is input to the input terminals a of the adder ADD from the flip-flop FF13 through the switching device SW3.
  • the data y 0 is input to the input terminals b of the adder ADD from the flip-flop FF15 through the switching device SW4 and the exclusive OR gate XOR3.
  • the ADS signal is at the "L" level.
  • the data E4 is input to the flip-flop FF17 to be latched therein on the leading edge of a clock 17CK at the time t5.
  • both the switching devices SW1 and SW2 are switched to their input terminals c.
  • the data C is input to the input terminals a of the multiplier MPY from the flip-flop FF3 through the switching device SW1.
  • the data E1 is input to the input terminals b of the multiplier MPY from the flip-flop FF9 through the switching device SW2.
  • the multiplier MPY performs an operation of data C ⁇ E1 and outputs the results of the operation.
  • the data C ⁇ E1 is input to the flip-flop FF13 to be latched therein on the leading edge of the clock /10MCK at the time t6.
  • both the switching devices SW3 and SW4 are switched to their input terminals c.
  • the data B ⁇ E2 is input to the input terminals a of the adder ADD from the flip-flop 13 through the switching device SW3
  • the data E3 is input to the input terminals b of the adder ADD from the flip-flop FF16 through the switching device SW4 and the exclusive OR gate XOR3.
  • the data E5 is input to the flip-flop FF16 to be latched therein on the leading edge of the clock 16CK at the time t6.
  • both the switching devices SW1 and SW2 are switched to their input terminals b.
  • the data B is input to the input terminals a of the multiplier MPY from the flip-flop FF2 through the switching device SW1.
  • the data V c is input to the input terminals b of the multiplier MPY from the flip-flop FF8 through the switching device SW2.
  • the multiplier MPY performs an operation of data B ⁇ V c and outputs the results of the operation.
  • the data B ⁇ V c is input to the flip-flop FF13 to be latched therein on the leading edge of the clock /10MCK at the time t7.
  • the switching devices SW3 and SW4 are respectively switched to its input terminals c and its input terminals d.
  • the data C ⁇ E1 is input to the input terminals a of the adder ADD from the flip-flop FF13 through the switching device SW3.
  • the data E4 is input to the input terminals b of the adder ADD from the flip-flop FF17 through the switching devices SW4 and the exclusive OR gate XOR3.
  • the data E6 is input to the flip flop FF17 to be latched therein on the leading edge of the clock 17CK at the time t7.
  • the switching device SW1 and SW2 are respectively switched to input terminals d and input terminals b.
  • the data D is input to the input terminals a of the multiplier MPY from the flip-flop FF4 through the switching device SW1.
  • the data V c is input to the input terminals b of the multiplier MPY from the flip-flop FF8 through the switching device SW2.
  • the multiplier MPY performs an operation of data D ⁇ V c and outputs the results of the operation.
  • the data D ⁇ Y c is input to the flip-flop FF13 to be latched therein on the leading edge of the clock/10MCK at the time t8.
  • both the switching devices SW3 and SW4 are switched to their input terminals c.
  • the data B ⁇ V c is input to the input terminals a of the adder ADD from the flip-flop 13 through the switching device SW3.
  • the data E5 is input to the input terminals b of the adder ADD from the flip-flop FF16 through the switching device SW4 and the exclusive OR gate XOR3.
  • the ADS signal is at the "L" level.
  • the data E7 is input to the flip-flop FF16 to be latched therein on the leading edge of the clock 16CK at the time t8.
  • both the switching devices SW1 and SW2 are switched to their input terminals a.
  • the data A is input to the input terminals a of the multiplier MPY from the flip-flop FF1 through the switching device SW1.
  • the data H c is input to the input terminals b of the multiplier MPY from the HV counter 31 through the exclusive OR gate XOR1 and the switching device SW2.
  • the multiplier MPY performs an operation of data A ⁇ H c and outputs the results of the operation.
  • the data A ⁇ H c is input to the flip-flop FF13 to be latched therein on the leading edge of the clock /10MCK at the time t9.
  • the switching devices SW3 and SW4 are respectively switched to its input terminals c and its input terminals d.
  • the data D ⁇ V c is input to the input terminals a of the adder ADD from the flip-flop FF13 through the switching device SW3.
  • the data E6 is input to the input terminals b of the adder ADD from the flip-flop FF17 through the switching device SW4 and the exclusive OR gate XOR3.
  • the ADS signal is at the "L" level.
  • the data E8 is input to the flip-flop FF17 to be latched therein on the leading edge of the clock 17CK at the time t9.
  • the preliminary preprocessing is terminated by the foregoing operations. Consequently, the data E7 is latched by the flip-flop FF16, and the data E8 is latched in the flip-flop FF17.
  • the switching devices SW1 and SW2 are respectively switched to input terminals c and input terminals a.
  • the data C is input to the input terminals a of the multiplier MPY from the flip-flop FF3 through the switching device SW1.
  • the data H c is input to the input terminals b of the multiplier MPY from the HV counter 31 through the exclusive OR gate XOR1 and the switching device SW2.
  • the multiplier MPY performs an operation of data C ⁇ H c and outputs the results of the operation.
  • the data C ⁇ H c is input to the flip-flop FF13 to be latched therein on the leading edge of the clock /10MCK at the time t10.
  • both the switching devices SW3 and SW4 are switched to their input terminals c.
  • the data A ⁇ H c is input to the input terminals a of the adder ADD from the flip-flop FF13 through the switching device SW3.
  • the data E7 is input to the input terminals b of the adder ADD from the flip-flop FF16 through the switching device SW4 and the exclusive OR gate XOR3.
  • the ADS signal is at the "L" level. Accordingly, the exclusive OR gate XOR3 and the adder ADD perform addition processing of (A ⁇ H c )+E7 and output the results of the operation as data x 2 .
  • the data x 2 is input to the flip-flop FF19 to be latched therein on the leading edge of the clock/10MCK and then, input to the flip-flop FF20 to be latched therein on the leading edge of the clock/5MCK at the time t11.
  • both the switching devices SW1 and SW2 are switched to their input terminals a.
  • the data A is input to the input terminals a of the multiplier MPY from the flip-flop FF1 through the switching device SW1.
  • the H c is input to the input terminals b of the multiplier MPY from the HV counter 31 through the exclusive OR gate XOR1 and the switching device SW2.
  • the multiplier MPY performs an operation of data A ⁇ H c and outputs the results of the operation.
  • the data A ⁇ H c is input to the flip-flop FF13 to be latched therein on the leading edge of the clock/10MCK at the time t11.
  • the switching devices SW3 and SW4 are respectively switched to its input terminals c and its input terminals d.
  • the data C ⁇ H c is input to the input terminals a of the adder ADD from the flip-flop FF13 through the switching device SW3.
  • the data E8 is input to the input terminals b of the adder ADD from the flip-flop FF17 through the switching device SW4 and the exclusive OR gate XOR3.
  • the ADS signal is at the "L" level.
  • the exclusive OR gate XOR3 and the adder ADD perform addition processing of (C ⁇ H c )+E8 and outputs the results of the operation as data y 2 .
  • the data y 2 is input to the flip-flop FF18 to be latched therein on the leading edge of the clock/5MCK at the time t11.
  • the data x 2 and y 2 in a case where the data H c is 1 to 255 are calculated in the same manner, to calculate the data x 2 and y 2 of one scanning line.
  • an AE signal output from the timing signal generator 30 falls to a low level.
  • the VRAM 7b inputs the address CAA0 at the time t13.
  • the data yd and xd of the respective least significant three bits of the data y 2 and x 2 in the case of H c 0, which are respectively latched in the flip-flops FF18 and FF20, are latched in the flip-flop FF23 through the flip-flop FF22.
  • addresses CAA1 to CAA255 including the data yc and xc in a case where the data H c is 1 to 255 are periodically repeated and output to the VRAM 7b through the address bus 15b for each period of the clock/5MCK. Furthermore, the data yd and xd corresponding to the respective values of the data H c are latched in the flip-flop FF23 through the flip-flop FF22 in the above described manner.
  • the VRAM 7b is responsive to the addresses CAA0 to CAA255 input from the background picture address control circuit 24 through the address bus 15b to output 8-bit character codes CA0 to CA255 stored in the respective addresses to the flip-flop FF21 in the background picture address control circuit 24 through the data bus 16b for each period of the clock/10MCK.
  • the 8-bit character codes CA0 to CA255 are latched in the flip-flop FF21.
  • the address CCA0 is input to the VRAM 7a at the time t17.
  • the addresses CCA1 to CCA255 in a period during which the data H c is 1 to 255 are output to the VRAM 7a from the background picture address control circuit 24 through the address bus 15a in the same manner.
  • the VRAM 7a is responsive to the addresses CCA0 to CCA255 input from the background picture address control circuit 24 through the address bus 15ato output the 8-bit color data CD0 to CD255 stored in the respective addresses to the background picture data processing circuit 25 through the data bus 16b for each period of the clock/10MCK.
  • the background picture address control circuit 24 calculates the addresses CAA0 to CAA255 in which character codes of a background picture at the time of rotation and enlargement or reduction are stored on the basis of the constant data A, B, C and D for rotation processing and enlargement or reduction processing which are input from the CPU2 and outputs the addresses.
  • the control circuit 24 outputs, in response to the addresses, the addresses CCA0 to CCA255 each comprising the character code (8 bits) output from the VRAM 7b and the data yd and xd, thereby to make it possible to output the color data of 8 bits per dot at the time of rotation processing and enlargement or reduction processing to the background picture data processing circuit 25 from the VRAM 7a. Thereafter, the color data (8 bits) of the background picture is latched in the background picture data processing circuit 25 and then, input to the priority control circuit 26.
  • the 7-bit moving picture data is input from the moving picture data processing circuit 23 to the priority control circuit 26.
  • the priority control circuit 26 is responsive to the moving picture data so as to determine the priority between the moving picture data and the background picture data on the basis of the 2-bit priority data included in the moving picture data and outputs higher-priority data of the moving picture data and the background picture data to the color signal generator 28.
  • the color generator 28 is responsive to the higher-priority data for converting the moving picture data or the background picture data as [inputted] input into a digital signal of RGB of 5 bits for each color and outputting the digital signal of RGB to the display device 8 and the NTSC encoder 29 on the basis of the count data H c and V c applied from the HV counter 31.
  • a three-dimensional background or a background which looks as if the road is curved as shown in each of FIGS. 12 to 16 can be displayed on the basis of one background picture data for displaying a two-dimensional background picture as shown in, for example, FIG. 11.
  • a background can be displayed which looks like a map viewed from the runway and the air which turns as an airplane takes off (moves away) and lands (approaches) by displaying the background screen in such a three-dimensional manner, thereby to make it possible to further improve the representation of the background picture.
  • the angle ⁇ of the parameter A in the equation (2) and (5) may be gradually changed by a constant value for each frame. In this case, however, the illustration of this state is difficult and thus, is omitted.
  • an address of the VRAM 7 in a case where the original background picture corresponding to the background picture data stored in the VRAM 7 is rotated and enlarged or reduced is calculated by the background picture address control circuit 24, the color data of the background picture at the time of the rotation processing and the enlargement or reduction processing is read from the VRAM 7 to generate a video signal, and the video signal is displayed on the display device 8.
  • the CPU 2 must only set constants but need not calculate respective positions of a picture which is rotated and enlarged or reduced. Accordingly, the CPU 2 can perform processing of another image or picture. Consequently, the present invention has the advantage that the throughput of the CPU can be improved, as compared with the prior art for rotation processing or enlargement or reduction processing.
  • an address of image data of a background picture in the VRAM 7 corresponding to the respective positions in the horizontal and vertical directions of the background picture which is rotated and enlarged or reduced is calculated by the hardware based background picture address control circuit 24 utilizing the switching devices SW1 and SW4, the multiplier MPY and the adder ADD as described above.
  • the rotation processing and the enlargement or reduction processing can be performed at higher speed, as compared with the prior art.
  • various circuits in one background picture address control circuit 24 achieve the rotation processing or the enlargement processing or the reduction processing in a time shared manner. Accordingly, the circuit configuration is simplified and the cost is lowered, as compared with a case where a dedicated circuit is provided for each processing.
  • the video processing unit 1 may be constructed to perform at least one of rotation processing and enlargement or reduction processing.
  • the construction of the background picture address control circuit 24 need not be changed.
  • the constants ⁇ and ⁇ calculated by the CPU 2 may be 0 if only the rotation processing is performed, and the constant ⁇ calculated by the CPU 2 may be 0 if only the enlargement or reduction processing is performed.
  • the present invention is not limited to the same. It should be noted that the present invention is applicable to a so-called dot map type video processing apparatus for designating an address for each dot to obtain color data using a VRAM having color data corresponding to the VRAM area 40.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Processing (AREA)
  • Adjustment Of Camera Lenses (AREA)
  • Saccharide Compounds (AREA)
  • Acyclic And Carbocyclic Compounds In Medicinal Compositions (AREA)
  • Polarising Elements (AREA)
  • Apparatus For Radiation Diagnosis (AREA)
  • Photoreceptors In Electrophotography (AREA)
  • Processing Or Creating Images (AREA)
  • Studio Circuits (AREA)
US07/651,265 1989-08-01 1990-07-26 Video processing apparatus Expired - Lifetime US5327158A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1-200073 1989-08-01
JP1200073A JP2725062B2 (ja) 1989-08-01 1989-08-01 画像処理装置
PCT/JP1990/000958 WO1991002345A1 (fr) 1989-08-01 1990-07-26 Unite de traitement d'images

Publications (1)

Publication Number Publication Date
US5327158A true US5327158A (en) 1994-07-05

Family

ID=16418397

Family Applications (1)

Application Number Title Priority Date Filing Date
US07/651,265 Expired - Lifetime US5327158A (en) 1989-08-01 1990-07-26 Video processing apparatus

Country Status (14)

Country Link
US (1) US5327158A (ko)
EP (1) EP0437630B1 (ko)
JP (1) JP2725062B2 (ko)
KR (1) KR960006527B1 (ko)
CN (1) CN1022351C (ko)
AT (1) ATE141707T1 (ko)
AU (2) AU643693B2 (ko)
CA (1) CA2037909C (ko)
DE (1) DE69028195T2 (ko)
ES (1) ES2090138T3 (ko)
HK (1) HK40797A (ko)
RU (1) RU2113727C1 (ko)
SG (1) SG82551A1 (ko)
WO (1) WO1991002345A1 (ko)

Cited By (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0631247A2 (en) 1993-06-24 1994-12-28 Nintendo Of America Inc. Video game and communications system to be used on an airplane accessible via an onboared distributed processing system
US5411272A (en) * 1992-11-20 1995-05-02 Sega Of America, Inc. Video game with spiral loop graphics
US5489989A (en) * 1991-10-30 1996-02-06 Canon Kabushiki Kaisha Color image processing apparatus
EP0709771A1 (en) 1994-10-31 1996-05-01 Nintendo Co., Ltd. Videographics program/video game fabricating system and method
EP0709772A1 (en) 1994-10-31 1996-05-01 Nintendo Co., Ltd. Video game/videographics program fabricating system and method with unit based program processing
EP0713174A1 (en) 1994-10-31 1996-05-22 Nintendo Co., Ltd. Video game/videographics program fabricating system and method with superimpose control
US5634850A (en) * 1993-05-21 1997-06-03 Sega Enterprises, Ltd. Image processing device and method
US5745098A (en) * 1993-11-26 1998-04-28 Fujitsu Limited Method and apparatus for scroll displaying an image on screen
US5784047A (en) * 1995-04-28 1998-07-21 Intel Corporation Method and apparatus for a display scaler
US5802107A (en) * 1996-09-13 1998-09-01 Zenith Electronics Corporation Symbol rotator
US5848201A (en) * 1993-06-30 1998-12-08 Sega Enterprises Image processing system and its method and electronic system having an image processing system
US5850540A (en) * 1993-07-02 1998-12-15 Sony Corporation Method and apparatus for time-sharing CPU system bus in image generation system
US6139433A (en) * 1995-11-22 2000-10-31 Nintendo Co., Ltd. Video game system and method with enhanced three-dimensional character and background control due to environmental conditions
US6147696A (en) * 1993-06-24 2000-11-14 Nintendo Co. Ltd. Electronic entertainment and communication system
US6184899B1 (en) 1997-03-31 2001-02-06 Treyarch Invention, L.L.C. Articulated figure animation using virtual actuators to simulate solutions for differential equations to display more realistic movements
US6200253B1 (en) 1995-10-09 2001-03-13 Nintendo Co., Ltd. Controller pack
US6241611B1 (en) 1995-05-10 2001-06-05 Nintendo Co., Ltd. Function expansion device and operating device using the function expansion device
US6267673B1 (en) 1996-09-20 2001-07-31 Nintendo Co., Ltd. Video game system with state of next world dependent upon manner of entry from previous world via a portal
US6307486B1 (en) 1995-11-10 2001-10-23 Nintendo Co., Ltd. Joystick device
US6325718B1 (en) 1995-10-09 2001-12-04 Nintendo Co., Ltd. Operation controlling device and video processing system used therewith
US6331146B1 (en) 1995-11-22 2001-12-18 Nintendo Co., Ltd. Video game system and method with enhanced three-dimensional character and background control
US6383079B1 (en) 1995-11-22 2002-05-07 Nintendo Co., Ltd. High performance/low cost video game system with multi-functional peripheral processing subsystem
US6421056B1 (en) 1995-10-09 2002-07-16 Nintendo Co., Ltd. Three-dimensional image processing apparatus
US6419582B1 (en) * 1995-05-19 2002-07-16 Sega Corporation Image processing device, image processing method, and game device storage medium using the same
US6461242B2 (en) 1995-05-10 2002-10-08 Nintendo Co., Ltd. Operating device for an image processing apparatus
US6491585B1 (en) 1996-09-24 2002-12-10 Nintendo Co., Ltd. Three-dimensional image processing apparatus with enhanced automatic and user point of view control
US6497618B1 (en) 1995-10-09 2002-12-24 Nintendo Co. Ltd. Video game system with data transmitting/receiving controller
US6679776B1 (en) 1997-07-17 2004-01-20 Nintendo Co., Ltd. Video game system
US6762733B2 (en) 1993-06-24 2004-07-13 Nintendo Co. Ltd. Electronic entertainment and communication system
US6810463B2 (en) 2000-05-24 2004-10-26 Nintendo Co., Ltd. Gaming machine that is usable with different game cartridge types
US20040224775A1 (en) * 2003-02-10 2004-11-11 Leapfrog Enterprises, Inc. Interactive handheld apparatus with stylus
US20050245313A1 (en) * 2004-03-31 2005-11-03 Nintendo Co., Ltd. Game console and memory card
US20060094512A1 (en) * 2004-03-31 2006-05-04 Nintendo Co., Ltd. Game console and emulator for the game console
US20060111190A1 (en) * 2004-03-31 2006-05-25 Nintendo Co., Ltd. Game console connector and emulator for the game console
US7126584B1 (en) 1995-10-09 2006-10-24 Nintendo Co., Ltd. Operating device and image processing system using same
US20070132783A1 (en) * 2005-12-13 2007-06-14 Samsung Electronics Co., Ltd. Method for displaying background image in mobile communication terminal
US7249950B2 (en) 2003-10-10 2007-07-31 Leapfrog Enterprises, Inc. Display apparatus for teaching writing
US7445551B1 (en) 2000-05-24 2008-11-04 Nintendo Co., Ltd. Memory for video game system and emulator using the memory
US7837558B2 (en) 2004-03-31 2010-11-23 Nintendo Co., Ltd. Game console and emulator for the game console
US11278793B2 (en) 2004-03-31 2022-03-22 Nintendo Co., Ltd. Game console

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0590966B1 (en) * 1992-09-30 2000-04-19 Hudson Soft Co., Ltd. Sound data processing
US5459485A (en) * 1992-10-01 1995-10-17 Hudson Soft Co., Ltd. Image and sound processing apparatus
US5596693A (en) * 1992-11-02 1997-01-21 The 3Do Company Method for controlling a spryte rendering processor
US5838389A (en) * 1992-11-02 1998-11-17 The 3Do Company Apparatus and method for updating a CLUT during horizontal blanking
US5572235A (en) * 1992-11-02 1996-11-05 The 3Do Company Method and apparatus for processing image data
US5481275A (en) * 1992-11-02 1996-01-02 The 3Do Company Resolution enhancement for video display using multi-line interpolation
US5752073A (en) * 1993-01-06 1998-05-12 Cagent Technologies, Inc. Digital signal processor architecture
CN1067785C (zh) * 1994-12-27 2001-06-27 联华电子股份有限公司 近似线性的影像缩小方法及装置
JP3776570B2 (ja) 1997-08-18 2006-05-17 富士写真フイルム株式会社 画像処理装置およびその処理方法
US6712703B2 (en) 1998-11-19 2004-03-30 Nintendo Co., Ltd. Video game apparatus and information storage medium for video game
US7512287B2 (en) * 2005-07-25 2009-03-31 Seiko Epson Corporation Method and apparatus for efficient image rotation
KR100827219B1 (ko) * 2006-07-13 2008-05-07 (주)씨앤에스 테크놀로지 저전력 구조를 갖는 영상 회전 장치 및 방법
DE102007042632A1 (de) * 2007-09-07 2009-03-12 Novomatic Ag Elektronisches Spielgerät
CN101447170B (zh) * 2007-11-27 2011-09-21 上海熙讯电子科技有限公司 一种兼容led显示屏复杂布局布线的方法
DE102008038420A1 (de) 2008-08-19 2010-02-25 Nechiporenko, Igor V. Vorrichtung zur Bildung der elektronischen Darstellung für die Durchführung eines elektronischen Spiels
CN102158026B (zh) * 2011-04-02 2013-03-13 浙江钱江摩托股份有限公司 一种双转子电机和用双转子电机作动力的混合动力车
CN103732300B (zh) * 2011-05-03 2016-01-27 邦吉有限公司 用于改善分布式交互模拟中的对象的呈现的装置和方法
RU2598790C2 (ru) * 2014-12-08 2016-09-27 Сурен Петросович Буюкян Видеопроцессор для видеоизмерений
KR20230170868A (ko) 2022-06-11 2023-12-19 김치형 무선 충전 팜레스트

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4026555A (en) * 1975-03-12 1977-05-31 Alpex Computer Corporation Television display control apparatus
EP0014045A1 (en) * 1979-01-15 1980-08-06 Atari Inc. Apparatus for controlling a display
US4398189A (en) * 1981-08-20 1983-08-09 Bally Manufacturing Corporation Line buffer system for displaying multiple images in a video game
EP0128789A1 (fr) * 1983-05-11 1984-12-19 Thomson-Csf Procédé pour réaliser une transformation géométrique sur une image vidéo, et dispositifs mettant en oeuvre ce procédé
US4580782A (en) * 1982-10-29 1986-04-08 Sega Enterprises, Ltd. Memory mapping scheme for one-dimensional memory storage system
US4593407A (en) * 1983-09-30 1986-06-03 International Business Machines Corporation Pattern processing system
US4602286A (en) * 1982-01-15 1986-07-22 Quantel Limited Video processing for composite images
US4672541A (en) * 1984-05-31 1987-06-09 Coleco Industries, Inc. Video game with interactive enlarged play action inserts
US4754270A (en) * 1984-02-16 1988-06-28 Nintendo Co., Ltd. Apparatus for varying the size and shape of an image in a raster scanning type display
US4824106A (en) * 1982-12-22 1989-04-25 Ricoh Co., Ltd. T.V. game system having reduced memory needs
US4850028A (en) * 1985-09-04 1989-07-18 Canon Kabushiki Kaisha Image processing method and apparatus therefor
US4895376A (en) * 1988-06-17 1990-01-23 Tigers Electronics, Inc. Interactive video game

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55108073A (en) * 1979-02-14 1980-08-19 Nec Corp Graph conversion unit
JPS58106592A (ja) * 1981-12-18 1983-06-24 日立電子株式会社 画像表示方法
JPS60217386A (ja) * 1984-04-13 1985-10-30 株式会社　アスキ− デイスプレイコントロ−ラ
JPS61208579A (ja) * 1985-03-14 1986-09-16 Nippon Telegr & Teleph Corp <Ntt> 幾何変換座標発生回路
JPS62139082A (ja) * 1985-12-13 1987-06-22 Canon Inc 画像処理装置
JPS62244095A (ja) * 1986-04-16 1987-10-24 セイコーインスツルメンツ株式会社 デイスプレイ装置
JPH0194388A (ja) * 1987-10-06 1989-04-13 Konami Co Ltd モニタ画面表示の制御方法
JP2664722B2 (ja) * 1988-05-06 1997-10-22 株式会社リコー 画像処理装置
JPH06292676A (ja) * 1993-04-12 1994-10-21 Olympus Optical Co Ltd 把持鉗子

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4026555A (en) * 1975-03-12 1977-05-31 Alpex Computer Corporation Television display control apparatus
EP0014045A1 (en) * 1979-01-15 1980-08-06 Atari Inc. Apparatus for controlling a display
US4398189A (en) * 1981-08-20 1983-08-09 Bally Manufacturing Corporation Line buffer system for displaying multiple images in a video game
US4602286A (en) * 1982-01-15 1986-07-22 Quantel Limited Video processing for composite images
US4580782A (en) * 1982-10-29 1986-04-08 Sega Enterprises, Ltd. Memory mapping scheme for one-dimensional memory storage system
US4824106A (en) * 1982-12-22 1989-04-25 Ricoh Co., Ltd. T.V. game system having reduced memory needs
EP0128789A1 (fr) * 1983-05-11 1984-12-19 Thomson-Csf Procédé pour réaliser une transformation géométrique sur une image vidéo, et dispositifs mettant en oeuvre ce procédé
US4593407A (en) * 1983-09-30 1986-06-03 International Business Machines Corporation Pattern processing system
US4754270A (en) * 1984-02-16 1988-06-28 Nintendo Co., Ltd. Apparatus for varying the size and shape of an image in a raster scanning type display
US4672541A (en) * 1984-05-31 1987-06-09 Coleco Industries, Inc. Video game with interactive enlarged play action inserts
US4850028A (en) * 1985-09-04 1989-07-18 Canon Kabushiki Kaisha Image processing method and apparatus therefor
US4895376A (en) * 1988-06-17 1990-01-23 Tigers Electronics, Inc. Interactive video game

Cited By (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5489989A (en) * 1991-10-30 1996-02-06 Canon Kabushiki Kaisha Color image processing apparatus
US5411272A (en) * 1992-11-20 1995-05-02 Sega Of America, Inc. Video game with spiral loop graphics
US5634850A (en) * 1993-05-21 1997-06-03 Sega Enterprises, Ltd. Image processing device and method
US6147696A (en) * 1993-06-24 2000-11-14 Nintendo Co. Ltd. Electronic entertainment and communication system
US20060208959A1 (en) * 1993-06-24 2006-09-21 Nintendo, Co., Ltd. Electronic entertainment and communication system
US7417600B2 (en) 1993-06-24 2008-08-26 Nintendo Co., Ltd. Electronic entertainment and communication system
EP0631247A2 (en) 1993-06-24 1994-12-28 Nintendo Of America Inc. Video game and communications system to be used on an airplane accessible via an onboared distributed processing system
US6762733B2 (en) 1993-06-24 2004-07-13 Nintendo Co. Ltd. Electronic entertainment and communication system
US6559812B1 (en) 1993-06-24 2003-05-06 Nintendo Co., Ltd. Airline-based video game and communications system
US5872872A (en) * 1993-06-30 1999-02-16 Sega Enterprises Image processing system and its method and electronic system having an image processing system
US5848201A (en) * 1993-06-30 1998-12-08 Sega Enterprises Image processing system and its method and electronic system having an image processing system
US5850540A (en) * 1993-07-02 1998-12-15 Sony Corporation Method and apparatus for time-sharing CPU system bus in image generation system
US5745098A (en) * 1993-11-26 1998-04-28 Fujitsu Limited Method and apparatus for scroll displaying an image on screen
EP0713174A1 (en) 1994-10-31 1996-05-22 Nintendo Co., Ltd. Video game/videographics program fabricating system and method with superimpose control
EP0709772A1 (en) 1994-10-31 1996-05-01 Nintendo Co., Ltd. Video game/videographics program fabricating system and method with unit based program processing
EP0709771A1 (en) 1994-10-31 1996-05-01 Nintendo Co., Ltd. Videographics program/video game fabricating system and method
US5784047A (en) * 1995-04-28 1998-07-21 Intel Corporation Method and apparatus for a display scaler
US6241611B1 (en) 1995-05-10 2001-06-05 Nintendo Co., Ltd. Function expansion device and operating device using the function expansion device
US6489946B1 (en) 1995-05-10 2002-12-03 Nintendo Co., Ltd. Operating device with analog joystick
US6461242B2 (en) 1995-05-10 2002-10-08 Nintendo Co., Ltd. Operating device for an image processing apparatus
US20070155492A1 (en) * 1995-05-19 2007-07-05 Sega Corporation Image processing device, image processing method, and game device and storage medium using the same
US6419582B1 (en) * 1995-05-19 2002-07-16 Sega Corporation Image processing device, image processing method, and game device storage medium using the same
US7207884B2 (en) 1995-05-19 2007-04-24 Sega Corporation Image processing device, image processing method, and game device and storage medium using the same
US20020151361A1 (en) * 1995-05-19 2002-10-17 Sega Corporation Image processing device, image processing method, and game device and storage medium using the same
US6778190B1 (en) 1995-10-09 2004-08-17 Nintendo Co., Ltd. Three-dimensional image processing apparatus
US6421056B1 (en) 1995-10-09 2002-07-16 Nintendo Co., Ltd. Three-dimensional image processing apparatus
US20050174328A1 (en) * 1995-10-09 2005-08-11 Nintendo Co., Ltd. User controlled graphics object movement based on a amount of joystick angular rotation and point of view angle
US6917356B1 (en) 1995-10-09 2005-07-12 Nintendo Co. Ltd. User controlled graphics object movement based on amount of joystick angular rotation and point of view angle
US6332840B1 (en) 1995-10-09 2001-12-25 Ninetendo Co., Ltd. Operation controlling device and video processing system used therewith
US7126584B1 (en) 1995-10-09 2006-10-24 Nintendo Co., Ltd. Operating device and image processing system using same
US6200253B1 (en) 1995-10-09 2001-03-13 Nintendo Co., Ltd. Controller pack
US6497618B1 (en) 1995-10-09 2002-12-24 Nintendo Co. Ltd. Video game system with data transmitting/receiving controller
US6325718B1 (en) 1995-10-09 2001-12-04 Nintendo Co., Ltd. Operation controlling device and video processing system used therewith
US6590578B2 (en) 1995-10-09 2003-07-08 Nintendo Co., Ltd. Three-dimensional image processing apparatus
US6676520B2 (en) 1995-10-09 2004-01-13 Nintendo Co., Ltd. Video game system providing physical sensation
US7102618B2 (en) 1995-10-09 2006-09-05 Nintendo Co., Ltd. User controlled graphics object movement based on a amount of joystick angular rotation and point of view angle
US7594854B2 (en) 1995-10-09 2009-09-29 Nintendo Co., Ltd. Video game system with data transmitting/receiving controller
US6307486B1 (en) 1995-11-10 2001-10-23 Nintendo Co., Ltd. Joystick device
US6331146B1 (en) 1995-11-22 2001-12-18 Nintendo Co., Ltd. Video game system and method with enhanced three-dimensional character and background control
US6383079B1 (en) 1995-11-22 2002-05-07 Nintendo Co., Ltd. High performance/low cost video game system with multi-functional peripheral processing subsystem
US6454652B2 (en) 1995-11-22 2002-09-24 Nintendo Co., Ltd. Video game system and method with enhanced three-dimensional character and background control due to environmental conditions
US6139433A (en) * 1995-11-22 2000-10-31 Nintendo Co., Ltd. Video game system and method with enhanced three-dimensional character and background control due to environmental conditions
US5802107A (en) * 1996-09-13 1998-09-01 Zenith Electronics Corporation Symbol rotator
US6267673B1 (en) 1996-09-20 2001-07-31 Nintendo Co., Ltd. Video game system with state of next world dependent upon manner of entry from previous world via a portal
US6491585B1 (en) 1996-09-24 2002-12-10 Nintendo Co., Ltd. Three-dimensional image processing apparatus with enhanced automatic and user point of view control
US6184899B1 (en) 1997-03-31 2001-02-06 Treyarch Invention, L.L.C. Articulated figure animation using virtual actuators to simulate solutions for differential equations to display more realistic movements
US6679776B1 (en) 1997-07-17 2004-01-20 Nintendo Co., Ltd. Video game system
US7070507B2 (en) 1997-07-17 2006-07-04 Nintendo Co., Ltd. Video game system
US20090069083A1 (en) * 2000-05-24 2009-03-12 Satoru Okada Portable video game system
US20040268042A1 (en) * 2000-05-24 2004-12-30 Nintendo Co., Ltd. Information processing device and peripheral devices used therewith
US7445551B1 (en) 2000-05-24 2008-11-04 Nintendo Co., Ltd. Memory for video game system and emulator using the memory
US9205326B2 (en) 2000-05-24 2015-12-08 Nintendo Co., Ltd. Portable video game system
US8821287B2 (en) * 2000-05-24 2014-09-02 Nintendo Co., Ltd. Video game display system
US6810463B2 (en) 2000-05-24 2004-10-26 Nintendo Co., Ltd. Gaming machine that is usable with different game cartridge types
US8025505B2 (en) 2003-02-10 2011-09-27 Leapfrog Enterprises, Inc. Interactive hand held apparatus with stylus
US20050037327A1 (en) * 2003-02-10 2005-02-17 Lepfrog Enterprises,Inc. Interactive hand held apparatus with stylus
US20060188861A1 (en) * 2003-02-10 2006-08-24 Leapfrog Enterprises, Inc. Interactive hand held apparatus with stylus
US20090179873A1 (en) * 2003-02-10 2009-07-16 Wood Michael C Interactive hand held apparatus with stylus
US7553160B2 (en) 2003-02-10 2009-06-30 Leapfrog Enterprises, Inc. Interactive hand held apparatus with stylus
US7083420B2 (en) 2003-02-10 2006-08-01 Leapfrog Enterprises, Inc. Interactive handheld apparatus with stylus
US20040224775A1 (en) * 2003-02-10 2004-11-11 Leapfrog Enterprises, Inc. Interactive handheld apparatus with stylus
US7529519B2 (en) 2003-02-10 2009-05-05 Leapfrog Enterprises, Inc. Interactive handheld educational apparatus with stylus
US8025504B2 (en) 2003-10-10 2011-09-27 Leapfrog Enterprises, Inc. Display apparatus for teaching writing
US20080048991A1 (en) * 2003-10-10 2008-02-28 Leapfrog Enterprises, Inc. Display apparatus for teaching writing
US7249950B2 (en) 2003-10-10 2007-07-31 Leapfrog Enterprises, Inc. Display apparatus for teaching writing
US8016681B2 (en) 2004-03-31 2011-09-13 Nintendo Co., Ltd. Memory card for a game console
US8267780B2 (en) 2004-03-31 2012-09-18 Nintendo Co., Ltd. Game console and memory card
US7771280B2 (en) 2004-03-31 2010-08-10 Nintendo Co., Ltd. Game console connector and emulator for the game console
US7837558B2 (en) 2004-03-31 2010-11-23 Nintendo Co., Ltd. Game console and emulator for the game console
US20110092285A1 (en) * 2004-03-31 2011-04-21 Hiroshi Yoshino Game console and emulator for the game console
US7988556B2 (en) 2004-03-31 2011-08-02 Nintendo Co., Ltd. Game console and emulator for the game console
US20090305792A1 (en) * 2004-03-31 2009-12-10 Nintendo Co., Ltd. Game console and memory card
US11278793B2 (en) 2004-03-31 2022-03-22 Nintendo Co., Ltd. Game console
US20050245313A1 (en) * 2004-03-31 2005-11-03 Nintendo Co., Ltd. Game console and memory card
US20090305783A1 (en) * 2004-03-31 2009-12-10 Nintendo Co., Ltd. Game console
US8337304B2 (en) 2004-03-31 2012-12-25 Nintendo Co., Ltd. Game console
US20060094512A1 (en) * 2004-03-31 2006-05-04 Nintendo Co., Ltd. Game console and emulator for the game console
US8972658B2 (en) 2004-03-31 2015-03-03 Nintendo Co., Ltd. Game console and memory card
US20060111190A1 (en) * 2004-03-31 2006-05-25 Nintendo Co., Ltd. Game console connector and emulator for the game console
US10173132B2 (en) 2004-03-31 2019-01-08 Nintendo Co., Ltd. Game console
US10722783B2 (en) 2004-03-31 2020-07-28 Nintendo Co., Ltd. Game console
US20070132783A1 (en) * 2005-12-13 2007-06-14 Samsung Electronics Co., Ltd. Method for displaying background image in mobile communication terminal

Also Published As

Publication number Publication date
JP2725062B2 (ja) 1998-03-09
HK40797A (en) 1997-04-11
ATE141707T1 (de) 1996-09-15
CN1022351C (zh) 1993-10-06
ES2090138T3 (es) 1996-10-16
AU2975992A (en) 1993-02-11
AU6046790A (en) 1991-03-11
CA2037909C (en) 1994-02-01
AU643693B2 (en) 1993-11-25
JPH0363695A (ja) 1991-03-19
CN1049729A (zh) 1991-03-06
KR960006527B1 (ko) 1996-05-17
DE69028195D1 (de) 1996-09-26
RU2113727C1 (ru) 1998-06-20
EP0437630B1 (en) 1996-08-21
EP0437630A4 (en) 1993-02-24
WO1991002345A1 (fr) 1991-02-21
SG82551A1 (en) 2001-08-21
DE69028195T2 (de) 1997-01-23
CA2037909A1 (en) 1991-02-02
AU652868B2 (en) 1994-09-08
KR920701938A (ko) 1992-08-12
EP0437630A1 (en) 1991-07-24

Similar Documents

Publication Publication Date Title
US5327158A (en) Video processing apparatus
US5615322A (en) Image synthesizing system for producing three-dimensional images
EP0013813B1 (en) Programmable graphics generator and data processing system using such generator
US8144158B2 (en) Display system having floating point rasterization and floating point framebuffering
KR910009101B1 (ko) 화상합성장치
EP0121311A2 (en) Raster display smooth line generation
EP0715277A2 (en) Method of producing image data, image data processing apparatus, and recording medium
US4827445A (en) Image buffer having logic-enhanced pixel memory cells and method for setting values therein
US5363119A (en) Scaling processor for raster images
US6342883B1 (en) Image display method and image display apparatus
US5838298A (en) Image processing apparatus and method for smoothing stairway-like portions of a contour line of an image
US6515661B1 (en) Anti-aliasing buffer
JP2664722B2 (ja) 画像処理装置
JP3252359B2 (ja) 画像処理装置
JP4244444B2 (ja) データ処理装置、除算回路および画像処理装置
JP2822672B2 (ja) 図形描画方法および装置
JP3514763B6 (ja) スクロール画面表示回路
JPS61875A (ja) 図形処理方法とその装置
JPS61240380A (ja) 図形表示装置
JPS62125475A (ja) カラ−モニタにおけるシステムライン着色方式
JPH0667648A (ja) 疑似３次元画像合成装置
JPS584193A (ja) デイスプレイ装置

Legal Events

Date Code Title Description
AS Assignment

Owner name: RICOH CO, LTD., 3-6, NAKAMAGOME 1-CHOME, OTA-KU, T

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:TAKAHASHI, TOYOFUMI;MIYOSHI, MICHITAKA;OTAKE, MASAHIRO;AND OTHERS;REEL/FRAME:005681/0235

Effective date: 19910409

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12