US20220310546A1 - Multi-layer sheet for mold underfill encapsulation, method for mold underfill encapsulation, electronic component mounting substrate, and production method for electronic component - Google Patents

Multi-layer sheet for mold underfill encapsulation, method for mold underfill encapsulation, electronic component mounting substrate, and production method for electronic component Download PDF

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US20220310546A1
US20220310546A1 US17/633,598 US202017633598A US2022310546A1 US 20220310546 A1 US20220310546 A1 US 20220310546A1 US 202017633598 A US202017633598 A US 202017633598A US 2022310546 A1 US2022310546 A1 US 2022310546A1
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layer
electronic component
layer sheet
epoxy resin
sheet
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Daisuke Mori
Masahiro ASAHARA
Katsushi Kan
Eiichi Nomura
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Nagase Chemtex Corp
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Nagase Chemtex Corp
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Assigned to NAGASE CHEMTEX CORPORATION reassignment NAGASE CHEMTEX CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KAN, KATSUSHI, ASAHARA, MASAHIRO, MORI, DAISUKE, NOMURA, EIICHI
Publication of US20220310546A1 publication Critical patent/US20220310546A1/en
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    • B32—LAYERED PRODUCTS
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    • B32B27/00—Layered products comprising a layer of synthetic resin
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Definitions

  • the present invention relates to a multi-layer sheet for mold underfill encapsulation and a method for mold underfill encapsulation.
  • Electronic components have been subjected to encapsulation using an encapsulation resin or the like in order to block external dust, moisture, and the like, and the encapsulation of an electronic component connected by the flip-chip connection method is commonly carried out by methods of underfilling the gaps between electronic components and a package substrate with a liquid or slurry-like encapsulant material with fluidity and then overmolding the electronic components and the package substrate with another liquid or slurry-like encapsulant material or an encapsulant film.
  • Patent Document 1 a mold underfill material with which underfilling and overmolding can be carried out at the same time.
  • an object of the present invention is to provide a multi-layer sheet for mold underfill encapsulation having satisfactory infiltrability between electrodes.
  • a multi-layer sheet comprising an (A)-layer formed from a resin composition having a specific tan ⁇ (loss tangent) as an outermost layer can solve the above-described problems, thus completing the present invention.
  • the present invention is the following multi-layer sheet.
  • the multi-layer sheet of the present invention for solving the above-described problems comprises an (A)-layer formed from a resin composition having a local maximum value of tan ⁇ (loss tangent) of 3 or more at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds, as an outermost layer.
  • the tan ⁇ (loss tangent) represents the proportion of the elastic properties and the viscous properties in a resin composition.
  • a resin composition In the case of carrying out underfilling for an electronic component such as a semiconductor chip where the distance between electrodes is narrower, just by having a low viscosity, a resin composition exhibits insufficient infiltrability into the deepest parts.
  • elastic force which is a force for pushing the infiltrated material from behind, is also required.
  • the multi-layer sheet of the present invention which contains an (A)-layer formed from a resin composition with a specified local maximum value of tan ⁇ (loss tangent), can exhibit excellent infiltrability when performing mold underfill for an electronic component having a narrower distance between electrodes.
  • the multi-layer sheet has a sheet shape, a step of injecting a resin that is liquid or the like is not needed in mold underfill encapsulation. Therefore, an electronic component mounting substrate having fewer voids can be produced, as compared with mold underfill encapsulation by a transfer molding method.
  • the (A)-layer contains a filler, and the maximum particle size of the filler is 20 ⁇ m or less.
  • the (A)-layer contains a curing accelerator whose median diameter (D50) at a cumulative volume of 50% in the volume particle size distribution (hereinafter, referred to as “median diameter”) is 10 ⁇ m or less.
  • the thickness of the (A)-layer is 10 to 500 ⁇ m.
  • the multi-layer sheet comprises a (B)-layer formed from a resin composition that satisfies the following Formula (1).
  • ⁇ represents the coefficient of thermal expansion ⁇ [ppm/K] at 80° C. or lower of a thermoset product obtained after subjecting the resin composition to a thermosetting treatment at 175° C. for one hour.
  • E′ represents the storage modulus E′ [GPa] at 25° C. of the thermoset product.
  • An electronic component may undergo a shape change due to heat at the time of resin curing; however, a multi-layer sheet comprising a (B)-layer formed from a resin composition that satisfies Formula (1) can conform to the shape change of the electronic component and can suppress warpage while exhibiting superior infiltrability.
  • the coefficient of thermal expansion represents the proportion at which the length of the sheet changes in accordance with an increase in temperature
  • the storage modulus represents the rigidity of the sheet.
  • the coefficient of thermal expansion a when the coefficient of thermal expansion a is large, the storage modulus E′ becomes smaller, and the rigidity of the sheet can be made smaller. Then, the sheet can conform to a shape change of an electronic component, and the heat-induced stress of the electronic component can be relieved. As a result, warpage of the electronic component can be suppressed.
  • the multi-layer sheet comprises a (B)-layer containing 70% by mass or more of a filler, and the ratio (B/A) of the thickness of the (B)-layer to the thickness of the (A)-layer is 1.0 to 80.
  • the method for mold underfill encapsulation of the present invention for solving the above-described problems is a method for mold underfill encapsulation of an electronic component mounting substrate, the method comprising a step of preparing a substrate on which an electronic component provided with electrodes having an electrode height (h) of 5 to 250 ⁇ m and a width (w) between electrodes of 5 to 500 ⁇ m is flip-chip mounted; a step of preparing a multi-layer sheet having an (A)-layer as an outermost layer; a step of placing the multi-layer sheet such that the (A)-layer comes into contact with the electronic component and the substrate; and a step of heating and compressing the placed multi-layer sheet.
  • the A-layer is a layer formed from a resin composition having a local maximum value of tan ⁇ (loss tangent) of 3 or more at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds.
  • the multi-layer film can be caused to infiltrate more efficiently between electrodes of an electronic component mounting substrate, and superior encapsulation method can be provided.
  • the (A)-layer contains a filler, and the maximum particle size of the filler is equal to or less than the electrode height (h) and the width (w) between electrodes.
  • the maximum particle size of the filler in the (A)-layer is equal to or less than the electrode height (h) and the width (w) between electrodes, a multi-layer film containing the (A)-layer can be caused to infiltrate more efficiently between electrodes on an electronic component mounting substrate, and warpage of the electronic component mounting substrate can be suppressed.
  • the mold underfill encapsulation is encapsulated by a multi-layer sheet comprising an (A)-layer as an outermost layer.
  • the A-layer is a layer formed from a resin composition having a local maximum value of tan ⁇ (loss tangent) of 3 or more at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds.
  • the multi-layer sheet comprising the (A)-layer is caused to infiltrate more efficiently between electrodes on an electronic component mounting substrate where electronic components are mounted, an electronic component mounting substrate having excellent heat resistance and moisture resistance can be provided.
  • a method for producing an electronic component mounting substrate of the present invention comprises a step of preparing a substrate on which an electronic component is flip-chip mounted; a step of preparing a multi-layer sheet having an (A)-layer as an outermost layer; a step of placing the multi-layer sheet such that the (A)-layer comes into contact with the electronic component and the substrate; and a step of heating and compressing the placed multi-layer sheet.
  • the A-layer is a layer formed from a resin composition having a local maximum value of tan ⁇ (loss tangent) of 3 or more at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds.
  • the multi-layer sheet comprising the (A)-layer can be caused to infiltrate more efficiently between electrodes of an electronic component mounting substrate, a method for producing an electronic component mounting substrate having excellent heat resistance and moisture resistance can be provided.
  • a multi-layer sheet for mold underfill encapsulation having satisfactory infiltrability between electrodes can be provided.
  • FIG. 1 is a schematic explanatory diagram of a multi-layer sheet of the present invention
  • FIG. 2 is a schematic explanatory diagram of an electronic component mounting substrate
  • FIG. 3 is a schematic explanatory diagram of a state in which the multi-layer sheet of the present invention is placed on the electronic component mounting substrate;
  • FIG. 4 is a schematic explanatory diagram of an electronic component mounting substrate that has been subjected to mold underfill encapsulation with the multi-layer sheet of the present invention.
  • the multi-layer sheet for mold underfill encapsulation of the present invention comprises an (A)-layer formed from a resin composition having a local maximum value of tan ⁇ (loss tangent) of 3 or more at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds, as an outermost layer.
  • the multi-layer sheet of the present invention comprises an (A)-layer formed from a resin composition having a local maximum value of tan ⁇ (loss tangent) of 3 or more at a measurement temperature of 125° for a measurement time of 0 to 100 seconds, as an outermost layer.
  • the multi-layer film of the present invention comprising an (A)-layer formed from a resin composition having a specified local maximum value of tan ⁇ (loss tangent) as an outermost layer can exhibit excellent infiltrability when performing mold underfilling for an electronic component having a narrower distance between electrodes.
  • the outermost layer refers to a layer that is on the outermost side in a multi-layer sheet and refers to a layer that is in contact with, for example, the atmosphere such as air.
  • a release film or a sheet is not referred to as outermost layer.
  • the (A)-layer of the present invention is a layer that is placed so as to come into direct contact with the electronic components and the substrate in the mold underfill encapsulation.
  • the multi-layer sheet comprises the (A)-layer as the outermost layer, excellent encapsulation performance can be exhibited by placing the multi-layer sheet such that the (A)-layer comes into contact with the electronic components and the substrate and then performing encapsulation.
  • the local maximum value of tan ⁇ (loss tangent) is preferably 5 or more, and more preferably 7 or more. There is no particular upper limit to the local maximum value of tan ⁇ (loss tangent); however, the upper limit is preferably 60 or less, and more preferably 50 or less.
  • the local maximum value of tan ⁇ of the resin composition that constitutes the (A)-layer can be controlled by the content of a filler or the type of a thermosetting resin or a curing agent. For example, when the content of the filler is increased, the local maximum value is decreased so that the local maximum value can be increased by reducing the content of the filler. Furthermore, by using a crystalline epoxy resin, a liquid epoxy resin, or the like, all of which have lower viscosity when heated, as a thermosetting resin, and by using a low-viscosity curing agent such as a low-molecular weight phenol, a crystalline acid anhydride, or liquid phenol, the local maximum value of tan ⁇ can be adjusted to be 3 or more.
  • the local maximum value of tan ⁇ of the resin composition constituting the (A)-layer according to the present invention is a value measured for a test specimen having a diameter of 25 mm ⁇ using a viscoelasticity measuring apparatus (for example, ARES-LS2 manufactured by TA Instruments, Inc.) under the conditions of a measurement temperature of 125° C., a measurement time of 0 to 100 seconds, and a frequency of 1 Hz.
  • a viscoelasticity measuring apparatus for example, ARES-LS2 manufactured by TA Instruments, Inc.
  • the (A)-layer preferably contains a filler.
  • the filler used for the (A)-layer is not particularly limited, and examples include silica such as fused silica or crystalline silica, alumina, talc, calcium carbonate, titanium white, red iron oxide, silicon carbide, boron nitride (BN), and glass beads. These may be used singly, or two or more kinds thereof may be used in combination.
  • a silica powder From the viewpoint of enhancing infiltrability between electrodes, it is preferable to use a silica powder, and it is more preferable to use a fused silica powder among silica powders.
  • the fused silica powder include a spherical fused silica powder and a crushed fused silica powder; however, from the viewpoint of fluidity, it is particularly preferable to use a spherical fused silica powder, and a spherical fused silica powder with a higher degree of sphericity is more preferred.
  • a filler having its surface reacted in advance with a silane coupling agent can also be used.
  • a filler having its surface reacted with a silane coupling agent dispersibility in a resin composition can be enhanced.
  • the mixing amount in the case of using a silane coupling agent is preferably 0.05 to 5 parts by mass, and more preferably 0.1 to 3 parts by mass, with respect to 100 parts by mass of the filler.
  • the content of the filler is preferably 30% by mass or more.
  • the lower limit value is more preferably 73% by mass or more, and even more preferably 76% by mass or more.
  • the upper limit value is more preferably 93% by mass or less, and even more preferably 85% by mass or less.
  • the median diameter of the filler is, for example, preferably 0.1 to 30 ⁇ m.
  • the lower limit value is more preferably 0.1 ⁇ m or more, and even more preferably 0.5 ⁇ m or more.
  • the upper limit value is more preferably 20 ⁇ m or less, and even more preferably 10 ⁇ m or less.
  • the maximum particle size of the filler is smaller than, for example, the electrode height or the width of an electrode, and the maximum particle size is preferably 20 ⁇ m or less.
  • the upper limit value is more preferably 15 ⁇ m or less, and even more preferably 10 ⁇ m or less.
  • the median diameter and the maximum particle size are values that can be derived by making measurement using, for example, a sample arbitrarily extracted from a population and using a laser diffraction scattering type particle size distribution analyzer.
  • the material constituting the (A)-layer is not particularly limited; however, the material is preferably a resin, and more preferably a thermosetting resin.
  • thermosetting resin examples include an epoxy resin, a (meth)acrylic resin, a phenol resin, a melamine resin, a silicone resin, a urea resin, a urethane resin, a vinyl ester resin, an unsaturated polyester resin, a diallyl phthalate resin, and a polyimide resin. These may be used singly, or two or more kinds thereof may be used in combination.
  • the epoxy resin is not particularly limited; however, examples include bisphenol type epoxy resins such as a bisphenol A type epoxy resin, a bisphenol F type epoxy resin, a bisphenol AD type epoxy resin, a hydrogenated bisphenol A type epoxy resin, a hydrogenated bisphenol F type epoxy resin, a biphenyl type or tetramethylbiphenyl type epoxy resin, a phenol novolac type epoxy resin, a naphthalene type epoxy resin, and alicyclic aliphatic epoxy resins such as a dicyclopentadiene type epoxy resin; glycidylamine type epoxy resins, and glycidyl ethers of organic carboxylic acids. These may be used singly, or two or more kinds thereof may be used in combination.
  • bisphenol type epoxy resins such as a bisphenol A type epoxy resin, a bisphenol F type epoxy resin, a bisphenol AD type epoxy resin, a hydrogenated bisphenol A type epoxy resin, a hydrogenated bisphenol F type epoxy resin, a biphenyl
  • the epoxy resin may be a prepolymer or may be a copolymer with another polymer, such as a polyether-modified type epoxy resin or a silicone-modified type epoxy resin.
  • a polyether-modified type epoxy resin such as a polyether-modified type epoxy resin or a silicone-modified type epoxy resin.
  • preferred examples include a bisphenol type epoxy resin, a biphenyl type epoxy resin, a dicyclopentadiene type epoxy resin, a glycidylamine type epoxy resin, a naphthalene type epoxy resin, and a polyether-modified type epoxy resin.
  • the epoxy resin can include about 0.1% to 30% by mass of a monofunctional epoxy resin having one epoxy resin in the molecule with respect to the total amount of epoxy resins, for the purpose of regulating the viscosity of the resin composition.
  • a monofunctional epoxy resin phenyl glycidyl ether, 2-ethylhexyl glycidyl ether, ethyl diethylene glycol glycidyl ether, dicyclopentadiene glycidyl ether, 2-hydroxyethyl glycidyl ether, or the like can be used. These may be used singly, or two or more kinds thereof may be used in combination.
  • the content of the thermosetting resin is not particularly limited; however, the content is preferably 5% to 50% by mass.
  • the content of the epoxy resin is not particularly limited; however, the content is from 5% by mass to 50% by mass.
  • the lower limit value is preferably 5% by mass or more, and more preferably 10% by mass or more.
  • the upper limit value is preferably 40% by mass or less, or more preferably 30% by mass or less.
  • the (A)-layer may include a curing agent for the thermosetting resin, and although the type of the curing agent is not particularly limited, examples include a phenol-based curing agent such as solid phenol, solid phenol novolac, or liquid phenol novolac; a dicyandiamide-based curing agent (dicyandiamide or the like); a urea-based curing agent; an organic acid hydrazide-based curing agent; a polyamine salt-based curing agent; an amine adduct-based curing agent; an acid anhydride-based curing agent such as a solid acid anhydride or a liquid acid anhydride; and an imidazole-based curing agent.
  • a phenol-based curing agent such as solid phenol, solid phenol novolac, or liquid phenol novolac
  • a dicyandiamide-based curing agent dicyandiamide or the like
  • a urea-based curing agent an organic acid hydrazide-based
  • a low-viscosity curing agent such as liquid phenol novolac or a liquid acid anhydride. These may be used singly, or two or more kinds thereof may be used in combination.
  • the type of the curing agent can be appropriately selected in accordance with the thermosetting resin.
  • the amount of the curing agent varies depending on the type of the curing agent.
  • a curing agent in an amount such that the equivalent number of functional groups of the curing agent is 0.001 to 2 equivalents, and more preferably 0.005 to 1.5 equivalents, per 1 equivalent of the epoxy group.
  • the (A)-layer contains a curing accelerator.
  • the curing accelerator include an amine compound such as an imidazole compound, a phosphorus compound and basic compounds such as an organometallic compound, and a microcapsule type curing accelerator.
  • imidazole compound examples include imidazole; 2-methylimidazole, 2-ethylimidazole, 2-substituted imidazole compounds such as 1-isobutyl-2-methylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-phenyl-4-methylimidazole, 1-benzyl-2-methylimidazole, 1-benzyl-2-phenylimidazole, 1,2-dimethylimidazole, 1-cyanoethyl-2-methylimidazole, 1-cyanoethyl-2-ethyl-4-methylimidazole, 1-cyanoethyl-2-undecylimidazole, and 1-cyanoethyl-2-phenylimidazole; trimellitic acid salts such as 1-cyanoethyl-2-undecylimidazolium trimellitate and 1-cyanoethyl-2-phenylimidazolium trimellitate; tria
  • Examples of the phosphorus compound include trialkylphosphine-based compounds such as tributylphosphine; and triarylphosphine-based compounds such as triphenylphosphine.
  • Examples of the amine compound also include 2,4,6-tris(dimethylaminomethyl)phenol, diethylamine, triethylamine, diethylenetetramine, triethylenetetramine, and 4,4-dimethylaminopyridine.
  • the amine compound may be an amine adduct.
  • organometallic compound examples include zinc naphthenate, cobalt naphthenate, tin octylate, cobalt octylate, bis(acetylacetonato)cobalt(II), and tris(acetylacetonato)cobalt(III).
  • a microparticle composition in which an amine-based compound powder is dispersed in an epoxy resin, or the like can be used.
  • the amine-based compound may be selected from those that will be listed below as examples, based on the desired thickening factor.
  • Examples of the amine-based compound include an aliphatic primary amine, an alicyclic primary amine, an aromatic primary amine, an aliphatic secondary amine, an alicyclic secondary amine, an aromatic secondary amine, an imidazole compound, an imidazoline compound, and reaction products of these compounds with carboxylic acids, sulfonic acids, isocyanates, epoxies, and the like.
  • the amine-based compound powder has a melting point or a softening point of 60° C. or higher, from the viewpoint of suppressing thickening at 25° C.
  • the curing accelerator contained in the (A)-layer is preferably such that the median diameter is 10 ⁇ m or less.
  • the median diameter is 10 ⁇ m or less.
  • the upper limit value of the median diameter of the curing accelerator is more preferably 5 ⁇ m or less, and more preferably 3 ⁇ m or less.
  • the lower limit value is preferably 0.1 ⁇ m or more.
  • the content of the curing accelerator is, for example, from 0.1 parts by mass to 40 parts by mass with respect to 100 parts by mass of the thermosetting resin.
  • the lower limit value is preferably 1 part by mass or more, and more preferably 5 parts by mass or more.
  • the upper limit value is preferably 30 parts by mass or less, and more preferably 20 parts by mass or less.
  • the content of the curing accelerator is, for example, from 0.1 parts by mass to 40 parts by mass with respect to 100 parts by mass of the epoxy resin.
  • the lower limit value is preferably 1 part by mass or more, and more preferably 5 parts by mass or more.
  • the upper limit value is preferably 30 parts by mass or less, and more preferably 20 parts by mass or less.
  • additives can be used as long as the purpose of the present invention is not impaired.
  • additives include a thermoplastic resin, a silane coupling agent, carbon black, and an ion scavenger.
  • thermoplastic resin examples include silicone oils such as a non-reactive silicone oil and a reactive silicone oil, an acrylic resin, a phenoxy resin, a polyolefin, a polyurethane, a blocked isocyanate, a polyether, a polyester, a polyimide, a polyvinyl alcohol, a butyral resin, a polyamide, vinyl chloride, cellulose, a thermoplastic epoxy resin, and a thermoplastic phenol resin.
  • silicone oils such as a non-reactive silicone oil and a reactive silicone oil
  • an acrylic resin such as a phenoxy resin, a polyolefin, a polyurethane, a blocked isocyanate
  • a polyether such as a non-reactive silicone oil and a reactive silicone oil
  • an acrylic resin such as a phenoxy resin, a polyolefin, a polyurethane, a blocked isocyanate
  • a polyether such as a polyether, a polyester, a polyimide,
  • non-reactive silicone oil examples include a polysiloxane, a polyether-modified silicone oil, and an alkyl-modified silicone oil.
  • reactive silicone oil examples include an epoxy-modified silicone oil, a carboxyl-modified silicone oil, and an amino-modified silicone oil.
  • silane coupling agent examples include 3-glycidoxypropyltrimethoxysilane, 3-glycidoxypropyltriethoxysilane, 2-(3,4-epoxycyclohexyl)ethyltrimethoxysilane, 2-(3,4-epoxycyclohexyl) ethyltriethoxysilane, vinyltrimethoxysilane, and vinyltriethoxysilane.
  • the above-described silane coupling agents can be appropriately incorporated even in the case of using a silica having its surface reacted in advance with a silane coupling agent.
  • the content of the silane coupling agent is preferably 0.1% to 10% by mass, and more preferably 2% to 6% by mass, in the (A)-layer.
  • the content of the carbon black is preferably 0.1% to 5% by mass, and more preferably 0.5% to 3% by mass, in the (A)-layer.
  • the ion scavenger is an agent having an ability to scavenge impurity ions in the encapsulating composition and is desirably an agent that can enhance reliability of an encapsulated electronic component.
  • Examples of the ion scavenger include an inorganic ion exchanger.
  • the content in the case of containing an ion scavenger is not particularly limited; however, the content is preferably 0.05% by mass or more, and more preferably 3% by mass or less, in the (A)-layer.
  • the thickness of the (A)-layer in the multi-layer sheet of the present invention is preferably 10 to 500 ⁇ m.
  • the lower limit value is more preferably 20 ⁇ m or more, and even more preferably 40 ⁇ m or more.
  • the upper limit value is more preferably 400 ⁇ m or less, and even more preferably 300 ⁇ m or less.
  • the thickness of the (A)-layer By adjusting the thickness of the (A)-layer to be in the above-described range, warpage of an electronic component can be suppressed. Furthermore, the resin can easily infiltrate under an electronic component, and superior infiltrability can be exhibited.
  • the multi-layer sheet of the present invention can preferably comprise a (B)-layer in addition to the (A)-layer.
  • the multi-layer sheet of the present invention comprises the (B)-layer, the occurrence of warpage in the multi-layer sheet can be suppressed.
  • the (B)-layer is preferably an outermost layer on the opposite surface of the (A)-layer, or an intermediate layer. Furthermore, even in this case, a release film or a sheet is not considered to be the outermost layer.
  • the multi-layer sheet of the present invention is such that even if the (B)-layer is an outermost layer, the (B)-layer does not have to be placed so as to come into direct contact with the electronic components and the substrate in the mold underfill encapsulation.
  • the (B)-layer is preferably a layer containing a filler.
  • the type of the filler is not particularly limited; however, fillers similar to those described in the section for the (A)-layer can be used.
  • the content of the filler is preferably 70% by mass or more.
  • the lower limit value is more preferably 75% by mass or more, and even more preferably 80% by mass or more.
  • the upper limit value is preferably 93% by mass or less, and more preferably 90% by mass or less.
  • the median diameter of the filler is preferably 0.1 to 30 ⁇ m.
  • the lower limit value is more preferably 1 ⁇ m or more, and even more preferably 3 ⁇ m or more.
  • the upper limit value is more preferably 20 ⁇ m or less, and even more preferably 15 ⁇ m or less.
  • the coefficient of thermal expansion of the filler is not particularly limited; however, the coefficient of thermal expansion is preferably 1 ppm/K or more, and more preferably 2 ppm/K or more.
  • the upper limit value is preferably 15 ppm/K or less, and more preferably 10 ppm/K or less.
  • the coefficient of thermal expansion of the (B)-layer at 80° C. or lower can be controlled.
  • the material constituting the (B)-layer is not particularly limited; however, the material is preferably a resin, and more preferably a thermosetting resin.
  • the thermosetting resin a resin similar to those described in the section for the (A)-layer can be used, and the thermosetting resin is preferably an epoxy resin.
  • the epoxy resin is not particularly limited, and examples include bisphenol type epoxy resins such as a bisphenol A type epoxy resin, a bisphenol F type epoxy resin, a bisphenol AD type epoxy resin, a hydrogenated bisphenol A type epoxy resin, a hydrogenated bisphenol F type epoxy resin, and a bisphenol-modified type epoxy resin; a biphenyl type or tetramethylbiphenyl type epoxy resin, a phenol novolac type epoxy resin, a naphthalene type epoxy resin, an alicyclic aliphatic epoxy resin, a phenolphthalein type epoxy resin, and a glycidyl ether of an organic carboxylic acid. These may be used singly, or two or more kinds thereof may be used in combination.
  • bisphenol type epoxy resins such as a bisphenol A type epoxy resin, a bisphenol F type epoxy resin, a bisphenol AD type epoxy resin, a hydrogenated bisphenol A type epoxy resin, a hydrogenated bisphenol F type epoxy resin, and a bisphenol-modified type epoxy
  • the epoxy resin may be a prepolymer or may be a copolymer with a polymer other than an epoxy resin, such as a polyether-modified type epoxy resin or a silicone-modified type epoxy resin.
  • an epoxy resin such as a polyether-modified type epoxy resin or a silicone-modified type epoxy resin.
  • a biphenyl type epoxy resin, a phenol novolac type epoxy resin, a phenolphthalein type epoxy resin, or a bisphenol-modified type epoxy resin all of which are epoxy resins having a rigid skeleton.
  • the coefficient of thermal expansion of the (B)-layer at 80° C. or lower can be reduced.
  • the storage modulus E′ at 25° C. of the (B)-layer can be reduced by using a polyether-modified type epoxy resin or the like having a flexible skeleton.
  • the epoxy resin can include about 0.1% to 30% by mass of a monofunctional epoxy resin having one epoxy group in the molecule with respect to the total amount of the epoxy resin, for the purpose of regulating the viscosity of the resin composition.
  • a monofunctional epoxy resin phenyl glycidyl ether, 2-ethylhexyl glycidyl ether, ethyl diethylene glycol glycidyl ether, dicyclopentadiene glycidyl ether, 2-hydroxyethyl glycidyl ether, or the like can be used. These may be used singly, or two or more kinds thereof may be used in combination.
  • the content of the thermosetting resin is not particularly limited; however, the content is preferably 2% to 30% by mass.
  • the content of the epoxy resin is not particularly limited; however, the content is from 2% by mass to 30% by mass.
  • the lower limit value is preferably 3% by mass or more, and more preferably 5% by mass or more.
  • the upper limit value is preferably 25% by mass or less, and more preferably 20% by mass or less.
  • the (B)-layer may include a curing agent and a curing accelerator for the thermosetting resin, and regarding the types of the curing agent and the curing accelerator, the same ones as those described in the section for the (A)-layer can be used.
  • the amount of the curing agent varies depending on the type of the curing agent.
  • a curing agent in an amount such that the equivalent number of functional groups of the curing agent is 0.001 to 2 equivalents, and more preferably 0.005 to 1.5 equivalents, per 1 equivalent of the epoxy group.
  • the storage modulus of the (B)-layer can be reduced by using a phenol-based curing agent such as a solid phenol novolac resin, and preferably a biphenyl type phenol novolac resin.
  • the content of the curing accelerator in the (B)-layer is preferably from 0.1 parts by mass to 40 parts by mass with respect to 100 parts by mass of the thermosetting resin.
  • the lower limit value is more preferably 1 part by mass or more, and even more preferably 5 parts by mass or more.
  • the upper limit value is more preferably 30 parts by mass or less, and even more preferably 20 parts by mass or less.
  • the content of the curing accelerator is preferably from 0.1 parts by mass to 40 parts by mass with respect to 100 parts by mass of the epoxy resin.
  • the lower limit value is more preferably 1 part by mass or more, and even more preferably 5 parts by mass or more.
  • the upper limit value is more preferably 30 parts by mass or less, and even more preferably 20 parts by mass or less.
  • additives can be used as long as the purpose of the present invention is not impaired.
  • the same additives as those described in the section for the (A)-layer can be used, and examples include a thermoplastic resin, a silane coupling agent, carbon back, and an ion scavenger.
  • thermoplastic resin examples include silicone oils such as a non-reactive silicone oil and a reactive silicone oil, an acrylic resin, a phenoxy resin, a polyolefin, a polyurethane, a blocked isocyanate, a polyether, a polyester, a polyimide, a polyvinyl alcohol, a butyral resin, a polyamide, vinyl chloride, cellulose, a thermoplastic epoxy resin, and a thermoplastic phenol resin.
  • silicone oils such as a non-reactive silicone oil and a reactive silicone oil
  • an acrylic resin a phenoxy resin
  • a polyolefin a polyolefin
  • a polyurethane a blocked isocyanate
  • a polyether a polyester, a polyimide, a polyvinyl alcohol, a butyral resin, a polyamide, vinyl chloride, cellulose, a thermoplastic epoxy resin, and a thermoplastic phenol resin.
  • a resin such as a polyester, an acrylic resin, a
  • silane coupling agent examples include 3-glycidoxypropyltrimethoxysilane, 3-glycidoxypropyltriethoxysilane, 2-(3,4-epoxycyclohexyl)ethyltrimethoxysilane, 2-(3,4-epoxycyclohexyl) ethyltriethoxysilane, vinyltrimethoxysilane, and vinyltriethoxysilane.
  • the above-described silane coupling agents can be appropriately incorporated even in the case of using a silica having its surface reacted in advance with a silane coupling agent.
  • the content of the silane coupling agent is preferably 0.1% to 10% by mass, and more preferably 2% to 6% by mass, in the (B)-layer.
  • the content of the carbon black is preferably 0.1% to 5% by mass, and more preferably 0.5% to 3% by mass, in the (B)-layer.
  • the ion scavenger is an agent having an ability to scavenge impurity ions in the encapsulating composition and is desirably an agent that can enhance reliability of an encapsulated electronic component.
  • Examples of the ion scavenger include an inorganic ion exchanger.
  • the content in the case of containing an ion scavenger is not particularly limited; however, the content is preferably 0.05% by mass or more, and more preferably 3% by mass or less, in the (B)-layer.
  • the thickness of the (B)-layer in the multi-layer sheet of the present invention is preferably 50 to 800 ⁇ m.
  • the lower limit value is more preferably 100 ⁇ m or more, and even more preferably 200 ⁇ m or more.
  • the upper limit value is more preferably 700 ⁇ m or less, and even more preferably 600 ⁇ m or less.
  • the (B)-layer of the multi-layer sheet of the present invention comprises a (B)-layer formed from a resin composition in which the coefficient of thermal expansion ⁇ [ppm/K] at 80° C. or lower and the storage modulus E′ [GPa] at 25° C. of the thermoset product satisfy the following Formula (1).
  • the lower limit value of ⁇ E′ of the (B)-layer is more preferably 40000 or more, and even more preferably 50000 or more.
  • the upper limit value is more preferably 220000 or less, and even more preferably 180000 or less.
  • the multi-layer sheet of the present invention can relieve heat-induced stress at the time of curing by comprising a (B)-layer formed from a resin composition that satisfies the above-described Formula (1), warpage of an electronic component can be suppressed.
  • the lower limit value of the coefficient of thermal expansion ⁇ at 80° C. or lower of the resin composition constituting the (B)-layer is preferably 3 ppm/K or higher, and more preferably 5 ppm/K or higher.
  • the upper limit value is preferably 15 ppm/K or lower, and more preferably 10 ppm/K or lower.
  • the sheet can conform to a shape change of an electronic component.
  • the coefficient of thermal expansion of the resin composition constituting the (B)-layer can be controlled by the coefficient of thermal expansion of the filler to be added, the amount of addition of the filler, the chemical structure of the thermosetting resin, and the glass transition temperature.
  • the coefficient of thermal expansion can be made small by charging a filler having a small coefficient of thermal expansion to a high level or by using an epoxy resin or the like having a rigid skeleton.
  • the coefficient of thermal expansion at a temperature equal to or lower than the glass transition temperature can be lowered by increasing the glass transition temperature of the (B)-layer.
  • a resin sheet composed only of the (B)-layer is subjected to a thermosetting treatment at 150° C. for one hour, and then a measurement sample having a size of 20 mm in length ⁇ 5 mm in width ⁇ 5 ⁇ m in thickness is prepared from the thermoset product.
  • the measurement sample is placed on a jig for compression measurement of a thermomechanical analyzer (TMA7100), and then the coefficient of thermal expansion ⁇ in the temperature range of ⁇ 50° C. to 300° C. is calculated from the expansion rate at 50° C. to 70° C. under the conditions of a load of 5 g and a rate of temperature increase of 2.5° C./min.
  • the lower limit value of the storage modulus E′ at 25° C. of the resin composition constituting the (B)-layer is preferably 3 GPa or higher, and more preferably 10 GPa or higher.
  • the upper limit value is preferably 50 GPa or lower, and more preferably 30 GPa or lower.
  • the storage modulus of the resin composition constituting the (B)-layer can be controlled by the amount of addition of the filler, the skeletons of the thermosetting resin and the curing agent, and the type of the thermoplastic resin.
  • the storage modulus can be made small by increasing the amount of addition of the filler, by using an epoxy resin, a biphenyl type phenol novolac resin, or the like, all of which have a skeleton with flexibility, such as a polyether structure, or by incorporating a thermoplastic resin such as an acrylic resin.
  • the method for measuring the storage modulus E′ is carried out by the following procedure.
  • thermosetting treatment at 150° C. for one hour, and then a measurement sample having a size of 50 mm in length ⁇ 10 mm in width ⁇ 2 mm in thickness is prepared from the thermoset product.
  • the measurement sample is placed on a jig for flexural measurement, and the flexural storage modulus in the temperature range of ⁇ 50° C. to 300° C. is measured using a viscoelasticity analyzer (DMA6100, manufactured by Hitachi High-Tech Science Corporation) under the conditions of a frequency of 1 Hz and a rate of temperature increase of 2.5° C./min.
  • DMA6100 manufactured by Hitachi High-Tech Science Corporation
  • the resin composition that constitutes the (B)-layer of the multi-layer sheet of the present invention is preferably such that the glass transition temperature of the thermoset product obtained by subjecting the resin composition to a thermosetting treatment at 175° C. for one hour is 80° C. or higher. Since the glass transition temperature of the thermoset product after the thermosetting treatment at 175° C. for one hour is 80° C. or higher, an encapsulation product encapsulated with the multi-layer sheet can have excellent thermal stability.
  • the rigidity of the thermoset product may be enhanced, and for example, it is preferable to increase the content of epoxy groups in the epoxy resin or to increase the number of reactive groups in the curing agent.
  • the thickness of the entirety of the multi-layer sheet of the present invention is not particularly limited; however, the thickness is preferably 100 ⁇ m or more.
  • the lower limit value is more preferably 150 ⁇ m or more, and even more preferably 200 ⁇ m or more.
  • the upper limit value is more preferably 1000 ⁇ m or less, and even more preferably 800 ⁇ m or less.
  • the ratio (B/A) of the thickness of the (B)-layer to the thickness of the (A)-layer is preferably 1.0 to 80, and more preferably 2.0 to 10.
  • the multi-layer sheet can exhibit superior encapsulation performance for an electronic component having a narrower distance between electrodes, and at the same time, low warpage characteristics can be further exhibited for an encapsulated electronic component.
  • the multi-layer sheet of the present invention may also comprise another layer in addition to the (A)-layer and the (B)-layer.
  • the other layer preferably includes the thermosetting resin described in the sections for the (A)-layer and the (B)-layer and may also contain a filler and the like.
  • the other layer may be a single layer or may be a larger number of layers.
  • the multi-layer sheet of the present invention includes another layer, for example, when the other layer is referred to as a (C)-layer, a configuration of (A)-layer/(C)-layer/(B)-layer or a configuration of (A)-layer/(B)-layer/(C)-layer can be adopted.
  • the multi-layer sheet of the present invention is preferably such that the local maximum value of tan ⁇ (loss tangent) of the resin composition constituting the (A)-layer at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds is equal to or less than the local maximum value of tan ⁇ (loss tangent) of the resin composition constituting a layer other than the (A)-layer at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds.
  • the (A)-layer and the (B)-layer can be prevented from melting and then mixing, and underfill and overmold encapsulation can be efficiently carried out.
  • the local maximum value of tan ⁇ (loss tangent) of the resin composition constituting the (A)-layer at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds is made equal to or less than the local maximum value of tan ⁇ (loss tangent) of the (C)-layer at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds.
  • the (A)-layer and the layer other than the (A)-layer can be prevented from melting and then mixing, and underfill and overmold encapsulation can be efficiently carried out.
  • FIG. 1 A schematic explanatory diagram of the multi-layer sheet of the present invention is shown in FIG. 1 .
  • the multi-layer sheet shown in FIG. 1 is a multi-layer sheet having two layers consisting of an (A)-layer 11 and a (B)-layer 12 .
  • the multi-layer sheet shown in FIG. 1 is a sheet comprising the (A)-layer 11 and the (B)-layer 12 as the outermost layers, respectively; however, the multi-layer sheet can also be produced into a multi-layer sheet comprising another layer in addition to the (A)-layer and the (B)-layer as described above.
  • a multi-layer sheet may be produced by individually forming each of the layers by, for example, a calender film-forming method, a casting film-forming method, an inflation extrusion method, a T-die extrusion method, a dry lamination method, or the like, and subsequently sticking the layers together, or by using a co-extrusion method or the like.
  • a multi-layer sheet can be formed on a base material, and at the time of use, the multi-layer sheet can be used after peeling off the base material.
  • the base material is not particularly limited; however, examples include a plastic film, paper, a nonwoven fabric, and a metal.
  • the plastic film include a polyolefin-based film, a vinyl halide polymer-based film, an acrylic resin-based film, a rubber-based film, a cellulose-based film, a polyester-based film, a polycarbonate-based film, a polystyrene-based film, a polyphenylene sulfide-based film, and a cycloolefin polymer-based film.
  • a base material that has been release-treated with silicone or the like can also be used.
  • the thickness of the base material is not particularly limited; however, the thickness is preferably 500 ⁇ m or less.
  • the method for mold underfill encapsulation of an electronic component mounting substrate of the present invention comprises a step of preparing a substrate on which an electronic component provided with electrodes having an electrode height (h) of 5 to 250 ⁇ m and a width (w) between electrodes of 5 to 500 ⁇ m is flip-chip mounted; a step of preparing a multi-layer sheet having an (A)-layer as an outermost layer, the (A)-layer having a local maximum value of tan ⁇ (loss tangent) of 3 or more at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds; a step of placing the multi-layer sheet such that the (A)-layer comes into contact with the electronic component and the substrate; and a step of heating and compressing the placed multi-layer sheet.
  • Examples of the electronic component include semiconductor chips such as an integrated circuit (IC) in which transistors, capacitors, resistors, and the like are integrated on a single chip, and a large-scale integrated circuit (LSI) in which the degree of integration of IC is further increased, and 1000 or more elements are housed in a single chip.
  • semiconductor chips such as an integrated circuit (IC) in which transistors, capacitors, resistors, and the like are integrated on a single chip, and a large-scale integrated circuit (LSI) in which the degree of integration of IC is further increased, and 1000 or more elements are housed in a single chip.
  • IC integrated circuit
  • LSI large-scale integrated circuit
  • the shape of the electrode is not particularly limited, and examples include a ball, a pillar, a post, and a column.
  • the material of the electrode is not particularly limited, and examples include Sn—Pb-based, Pb—Sn—Sb-based, Sn—Sb-based, Sn—Pb—Bi-based, lead-free Sn—Ag-based, Sn—Ag—Cu-based, Bi—Sn-based, Sn—Cu-based, Sn—Ag—Bi—In-based, SN—Zn—Bi-based solders; gold-based metal materials, copper-based metal materials, and copper-based alloys.
  • the electrode height (h) is 5 to 250 ⁇ m
  • the width (w) between the electrodes is 5 to 500 ⁇ m.
  • Examples of the substrate include a printed wiring board having a circuit printed thereon.
  • FIG. 2 is a schematic explanatory diagram of an electronic component mounting substrate (mounting substrate) 20 on which electronic components 21 and a substrate 22 are connected by electrodes 23 .
  • the electronic components 21 and the substrate 22 are conducted by the electrodes 23 .
  • the height (h) between electrodes is 5 to 250 ⁇ m
  • the width (w) is 5 to 500 ⁇ m.
  • the diameter of the electrodes is preferably 10 ⁇ m to 1000 ⁇ m.
  • FIG. 3 is a schematic explanatory diagram of a state in which a multi-layer sheet 10 is placed on the electronic component mounting substrate (mounting substrate) 20 such that an (A)-layer comes into contact with the electronic component 21 and the substrate 22 .
  • the maximum particle size of the filler included in the multi-layer film is preferably equal to or less than the height (h) and width (w) between the electrodes.
  • the electronic component mounting substrate can be subjected to mold underfill encapsulation by heating and compressing the multi-layer sheet 10 .
  • the heating temperature at this time is not particularly limited; however, the heating temperature is preferably 70° C. to 150° C.
  • the lower limit value is more preferably 80° C. or higher, and even more preferably 90° C. or higher.
  • the upper limit value is more preferably 140° C. or lower, and even more preferably 130° C. or lower.
  • the compression pressure is not particularly limited; however, the pressure is preferably 0.5 to 10 MPa.
  • the lower limit value is more preferably 1 MPa or higher, and even more preferably 1.5 MPa or higher.
  • the upper limit value is more preferably 8 MPa or lower, and even more preferably 6 MPa or lower.
  • the method for heating and compression is not particularly limited; however, a method of pressing the multi-layer sheet while heating, by means of a press plate or the like may be mentioned. Furthermore, at the time of heating and compression, heating and compression can be achieved under reduced pressure conditions.
  • thermosetting resin is contained as a material of the multi-layer film
  • a post-curing step is a step of curing by heating.
  • the heating temperature is preferably 90° C. to 200° C.
  • the lower limit value is more preferably 120° C. or higher, and even more preferably 140° C. or higher.
  • the heating time is preferably 30 to 240 minutes, and more preferably 60 to 180 minutes.
  • FIG. 4 is a schematic explanatory diagram of an electronic component mounting substrate that has been subjected to mold underfill encapsulation with the multi-layer sheet 10 .
  • the multi-layer sheet 10 contains an (A)-layer having a local maximum value of tan ⁇ (loss tangent) of 3 or more at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds, the multi-layer sheet 10 can more efficiently infiltrate between the electrodes of an electronic component mounting substrate, and therefore, the multi-layer sheet 10 is an electronic component mounting substrate having excellent heat resistance and moisture resistance.
  • An epoxy resin, a curing agent, a filler (fused silica FB501MDX1: manufactured by DENKA Co., Ltd.), carbon black (particle size 24 nm), a silane coupling agent (KBM503: manufactured by Shin-Etsu Silicone Co., Ltd.), an ion scavenger (inorganic ion exchanger), and a curing accelerator were mixed according to each blend shown in Table 1-1 to Table 1-4, the mixture was heated by a roll kneading machine at 120° C. for 30 minutes and then melt-kneaded, and a kneading product was prepared.
  • the numerical values in the tables are all in parts by mass.
  • the kneaded product thus obtained was applied on a release-treated film by a T-die extrusion method under the conditions of 100° C. to form into a sheet shape, and an (A)-layer having a thickness of 20 to 300 ⁇ m, a length of 500 mm, and a width of 500 mm was produced.
  • a silicone release-treated polyethylene terephthalate film having a thickness of 50 ⁇ m was used as the release treatment film.
  • a biphenyl type epoxy resin 50 parts by mass of a solid phenol novolac resin, 1360 parts by mass of a filler (fused silica FB501MDX: manufactured by DENKA Co., Ltd.), 2 parts by mass of carbon black (particle size 24 nm), 2 parts by mass of a silane coupling agent (KBM503: manufactured by Shin-Etsu Silicone Co., Ltd.), 5 parts by mass of an ion scavenger (inorganic ion exchanger), and 10 parts by mass of a curing accelerator (triarylphosphine-based compound) were blended, the blend was heated by a roll kneading machine at 120° C.
  • a kneading product was prepared.
  • the obtained kneading product was applied on a release-treated film by a T-die extrusion method under the conditions of 100° C. to form a sheet shape, and a (B)-layer having a thickness of 50 to 800 ⁇ m, a length of 500 mm, and a width of 500 mm was produced.
  • a release-treated film a silicone release-treated polyethylene terephthalate film having a thickness of 50 ⁇ m was used.
  • the (A)-layer and the (B)-layer produced as described above were laminated so as to be in contact with each other, the layers were stuck together by a laminator at a temperature of 60° C., and a mold underfill encapsulated sheet was produced.
  • tan ⁇ was measured. Measurement was carried out with a test specimen having a diameter of 25 mm ⁇ by using a viscoelasticity analyzer (manufactured by TA Instruments, Inc., ARES-LS2) under the conditions of a measurement temperature of 125° C., a measurement time of 0 to 100 seconds, and a frequency of 1 Hz. The measurement results are shown in Table 1-1 to Table 1-4.
  • the mold underfill encapsulated sheet produced as described above was placed such that the (A)-layer came into contact with the chip for test, and the assembly was pre-cured at a molding pressure of 3 MPa at 125° C. for 10 minutes and then was post-cured at 150° C. for 60 minutes.
  • the evaluation of infiltrability was carried out according to the following criteria, by making direct observation of the assembly through the back surface of the glass plate.
  • the size of an uninfiltrated part is 500 ⁇ m or less.
  • the size of the uninfiltrated part is larger than 500 ⁇ m and 1000 ⁇ m or less.
  • the size of the uninfiltrated part is larger than 1000 ⁇ m.
  • Example 1 and Example 9 were compared, it was found that a sheet produced using a curing accelerator having a median diameter of 10 ⁇ m or less exhibits superior infiltrability between electrodes.
  • a kneading product was prepared.
  • the obtained kneading product was applied on a release-treated film by a T-die extrusion method under the conditions of 100° C. to form into a sheet shape, and a (B)-layer having a thickness of 200 to 800 ⁇ m, a length of 500 mm, and a width of 500 mm was produced.
  • a release-treated film a silicone release-treated polyethylene terephthalate film having a thickness of 50 ⁇ m was used.
  • the (A)-layer and the (B)-layer of the blends used in Example 1 of Table 1-1 were laminated so as to be in contact with each other, the layers were stuck together by a laminator at a temperature of 60° C., and a mold underfill encapsulated sheet was produced.
  • the mold underfill encapsulated sheet was placed and was subjected to pre-curing at a molding pressure of 3 MPa at 125° C. for 10 minutes followed by post-curing at 150° C. for 60 minutes.
  • the mold underfill encapsulated sheet was cooled to room temperature, and the amount of warpage was evaluated according to the following criteria.
  • the measurement method the average of the difference in height between the substrate side center part of the silicon wafer and the two end points of the wafer was measured using a laser displacement meter, the value was designated as the amount of warpage, and an evaluation was carried out according to the following criteria.
  • the warpage is 12 mm or less.
  • the warpage is larger than 12 mm.
  • Example 29 and Example 30 were compared, it was found that when the thickness of the (A)-layer is 500 ⁇ m or less, an excellent effect of low warpage is exhibited. On the other hand, it was found that when the thickness of the (A)-layer is more than 500 ⁇ m, an effect of low warpage cannot be exhibited.
  • the multi-layer sheet for mold underfill encapsulation of the present invention narrow gap filling and overall encapsulation in a flip-chip process can be carried out all at once.
  • the multi-layer sheet can be utilized for the encapsulation of integrated circuits and large-scale integrated circuits, which are utilized for IOT, automated driving, and the like.

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220020603A1 (en) * 2020-07-20 2022-01-20 Disco Corporation Sheet and protective member forming method

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116888714A (zh) * 2021-02-01 2023-10-13 长濑化成株式会社 电子部件安装基板的密封方法及热固化性片材
WO2024024883A1 (ja) * 2022-07-29 2024-02-01 ナガセケムテックス株式会社 モールドアンダーフィル封止用シートおよびこれを用いる電子部品実装基板の封止方法

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030112986A1 (en) * 2000-07-06 2003-06-19 Osamu Furukawa Surface acoustic wave device and method of manufacturing the device
US20030159276A1 (en) * 2000-04-20 2003-08-28 Wakefield Elwyn Paul Michael Process for forming electrical/mechanical connections
US20070018539A1 (en) * 2003-05-29 2007-01-25 Ryota Nagashima Piezoelectric device
US20080272858A1 (en) * 2005-03-03 2008-11-06 Tetsuya Furihata Surface Acoustic Wave Device
US20110241203A1 (en) * 2008-12-10 2011-10-06 Mayumi Nakasato Semiconductor module, method for manufacturing semiconductor module, and portable apparatus
US20130082367A1 (en) * 2011-09-30 2013-04-04 Samsung Electro-Mechanics Co., Ltd. Semiconductor package and method of manufacturing the same
US20200127635A1 (en) * 2017-06-23 2020-04-23 Murata Manufacturing Co., Ltd. Acoustic wave device, front-end circuit, and communication apparatus
US20200207915A1 (en) * 2017-09-07 2020-07-02 Toray Industries, Inc. Resin composition, method of producing resin film, and method of producing electronic device
US20200273839A1 (en) * 2017-12-29 2020-08-27 Intel Corporation Microelectronic assemblies
US20200299476A1 (en) * 2017-11-14 2020-09-24 Toray Industries, Inc. Prepreg and fiber reinforced composite material
US20200312783A1 (en) * 2019-04-01 2020-10-01 Samsung Electronics Co., Ltd. Semiconductor package
US20200388509A1 (en) * 2017-12-04 2020-12-10 Nagase Chemtex Corporation Manufacturing method of mounting structure
US20210187923A1 (en) * 2019-10-29 2021-06-24 Showa Denko Materials Co., Ltd. Fluororesin substrate laminate
US20210296544A1 (en) * 2020-03-18 2021-09-23 Nikkiso Co., Ltd. Semiconductor light-emitting device
US20220037221A1 (en) * 2019-02-21 2022-02-03 Panasonic Intellectual Property Management Co., Ltd. Semiconductor encapsulation material and semiconductor device
US20220189907A1 (en) * 2020-12-11 2022-06-16 Samsung Electronics Co., Ltd. Semiconductor package
US20220293138A1 (en) * 2021-03-09 2022-09-15 Kioxia Corporation Semiconductor device
US20220365456A1 (en) * 2019-10-25 2022-11-17 Hewlett-Packard Development Company, L.P. Toner particle with thermally expandable capsule

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3632684B2 (ja) * 2002-08-26 2005-03-23 株式会社日立製作所 半導体素子及び半導体パッケージ
JP5223657B2 (ja) * 2008-12-24 2013-06-26 株式会社村田製作所 電子部品の製造方法及び製造装置
JP2012054363A (ja) * 2010-08-31 2012-03-15 Kyocera Chemical Corp 電子部品の封止方法
JP5349432B2 (ja) * 2010-09-06 2013-11-20 日東電工株式会社 電子部品装置の製法およびそれに用いる電子部品封止用樹脂組成物シート
JP6303373B2 (ja) 2013-10-02 2018-04-04 住友ベークライト株式会社 圧縮成形用モールドアンダーフィル材料、半導体パッケージ、構造体および半導体パッケージの製造方法
WO2015098842A1 (ja) * 2013-12-26 2015-07-02 日東電工株式会社 半導体装置の製造方法
JP2015216230A (ja) * 2014-05-09 2015-12-03 日東電工株式会社 半導体装置の製造方法
JP6422296B2 (ja) * 2014-10-09 2018-11-14 新日本無線株式会社 電子部品およびその製造方法
JP6894076B2 (ja) * 2017-03-31 2021-06-23 ナガセケムテックス株式会社 実装構造体の製造方法およびこれに用いられる積層シート

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030159276A1 (en) * 2000-04-20 2003-08-28 Wakefield Elwyn Paul Michael Process for forming electrical/mechanical connections
US20030112986A1 (en) * 2000-07-06 2003-06-19 Osamu Furukawa Surface acoustic wave device and method of manufacturing the device
US20070018539A1 (en) * 2003-05-29 2007-01-25 Ryota Nagashima Piezoelectric device
US20080272858A1 (en) * 2005-03-03 2008-11-06 Tetsuya Furihata Surface Acoustic Wave Device
US20110241203A1 (en) * 2008-12-10 2011-10-06 Mayumi Nakasato Semiconductor module, method for manufacturing semiconductor module, and portable apparatus
US20130082367A1 (en) * 2011-09-30 2013-04-04 Samsung Electro-Mechanics Co., Ltd. Semiconductor package and method of manufacturing the same
US20200127635A1 (en) * 2017-06-23 2020-04-23 Murata Manufacturing Co., Ltd. Acoustic wave device, front-end circuit, and communication apparatus
US20200207915A1 (en) * 2017-09-07 2020-07-02 Toray Industries, Inc. Resin composition, method of producing resin film, and method of producing electronic device
US20200299476A1 (en) * 2017-11-14 2020-09-24 Toray Industries, Inc. Prepreg and fiber reinforced composite material
US20200388509A1 (en) * 2017-12-04 2020-12-10 Nagase Chemtex Corporation Manufacturing method of mounting structure
US20200273839A1 (en) * 2017-12-29 2020-08-27 Intel Corporation Microelectronic assemblies
US20220037221A1 (en) * 2019-02-21 2022-02-03 Panasonic Intellectual Property Management Co., Ltd. Semiconductor encapsulation material and semiconductor device
US20200312783A1 (en) * 2019-04-01 2020-10-01 Samsung Electronics Co., Ltd. Semiconductor package
US20220365456A1 (en) * 2019-10-25 2022-11-17 Hewlett-Packard Development Company, L.P. Toner particle with thermally expandable capsule
US20210187923A1 (en) * 2019-10-29 2021-06-24 Showa Denko Materials Co., Ltd. Fluororesin substrate laminate
US20210296544A1 (en) * 2020-03-18 2021-09-23 Nikkiso Co., Ltd. Semiconductor light-emitting device
US20220189907A1 (en) * 2020-12-11 2022-06-16 Samsung Electronics Co., Ltd. Semiconductor package
US20220293138A1 (en) * 2021-03-09 2022-09-15 Kioxia Corporation Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220020603A1 (en) * 2020-07-20 2022-01-20 Disco Corporation Sheet and protective member forming method

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