US20150162296A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
US20150162296A1
US20150162296A1 US14/406,997 US201314406997A US2015162296A1 US 20150162296 A1 US20150162296 A1 US 20150162296A1 US 201314406997 A US201314406997 A US 201314406997A US 2015162296 A1 US2015162296 A1 US 2015162296A1
Authority
US
United States
Prior art keywords
metal film
opening
pad opening
semiconductor device
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/406,997
Other languages
English (en)
Inventor
Tomomitsu Risaki
Shoji Nakanishi
Hitomi Sakurai
Koichi Shimazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ablic Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Assigned to SEIKO INSTRUMENTS INC. reassignment SEIKO INSTRUMENTS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NAKANISHI, SHOJI, RISAKI, TOMOMITSU, SAKURAI, HITOMI, SHIMAZAKI, KOICHI
Publication of US20150162296A1 publication Critical patent/US20150162296A1/en
Assigned to SII SEMICONDUCTOR CORPORATION reassignment SII SEMICONDUCTOR CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SEIKO INSTRUMENTS INC.
Priority to US15/879,364 priority Critical patent/US10497662B2/en
Assigned to ABLIC INC. reassignment ABLIC INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: SII SEMICONDUCTOR CORPORATION
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05012—Shape in top view
    • H01L2224/05013—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05012—Shape in top view
    • H01L2224/05014—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05096—Uniform arrangement, i.e. array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05555—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H01L2224/78302—Shape
    • H01L2224/78303—Shape of the pressing surface, e.g. tip or head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects

Definitions

  • the present invention relates to a semiconductor device having a pad structure.
  • wire bonding is used to connect a pad of the semiconductor device to an external connection terminal through a metal wire to exchange electrical signals with the outside. Since the wire bonding is a mechanical process of bonding a wire formed of gold or the like to the pad of the semiconductor device with use of heat, ultrasound, or weight, the semiconductor device may thereby receive damage. Detail is described with reference to FIGS. 11( a ) and 11 ( b ).
  • a balled wire 15 formed at a tip of a bonding wire 14 is press-fitted to a topmost layer metal film 3 in a pad opening formed in the semiconductor device, becoming a crushed ball 16 , and the bonding wire 14 is thus bonded to the topmost layer metal film 3 in the pad opening. At this time, a crack 18 may develop in an insulating film 5 formed under the pad opening, which affects reliability of the semiconductor device.
  • Patent Literature 1 describes that, by devising a capillary structure of a ball bonding apparatus for the purpose of preventing a crack, bonding damage is inhibited, and development of a crack can be inhibited.
  • Patent Literature 2 in order to keep strength against bonding so as to prevent a crack, there is formed a thick metal film in the pad opening in direct contact with the bonding wire.
  • the metal film itself absorbs the bonding damage, inhibiting a crack and enhancing the crack resistance of the pad structure itself.
  • Patent Literature 3 as illustrated in FIG. 12 , there is disclosed a pad structure in which an effective thickness of an insulating film formed under a pad opening 9 that receives the bonding damage is increased.
  • a second metal film 2 is not formed under the topmost layer metal film 3 in the pad opening 9 .
  • a thickness of insulating films between a first metal film 1 and the topmost layer metal film 3 is a sum of a thickness of a second insulating film 4 and a thickness of a third insulating film 5 , and an effective thickness of the insulating films formed under the pad opening 9 that receives the bonding damage is increased.
  • the thick insulating film absorbs the bonding damage, inhibiting a crack. Arrangement of wiring and the like of the first metal film 1 under the pad opening 9 can reduce the chip size.
  • Patent Literature 1 when the strength against bonding is reduced, a disadvantage in that the wire bonding is liable to be disconnected may easily occur.
  • Patent Literature 2 the topmost layer metal film in the pad structure becomes thick, and processing of the metal film becomes difficult. As a result, the wiring width of the metal film cannot be sufficiently reduced, and the chip size increases.
  • Patent Literature 3 in order to reduce a parasitic resistance to an element in a semiconductor device of the pad structure so as not to affect electrical characteristics of an IC, as illustrated in FIG. 13( a ), a distance d1 from an opening edge of the pad opening 9 to an edge of the topmost layer metal film 3 of the pad structure is increased, or alternatively, as illustrated in FIG. 13( b ), a distance d2 from an edge of the topmost layer metal film 3 of the pad structure to an edge of the second metal film 2 is increased, to thereby enable a large number of vias to be arranged.
  • the larger pad structure as illustrated in sectional views of FIG. 13 accordingly increases the chip size.
  • the present invention has been made in view of the drawback that the chip size increases as described above, and an object of the present invention is to provide a semiconductor device that inhibits a crack under a pad opening without increasing a chip size.
  • a semiconductor device having a pad structure including: a metal film having a rectangular opening under a pad opening, the metal film having a rectangular donut shape, the metal film protruding to an inner side of the pad opening by a predetermined distance, being absent under a beveled corner at a tip of a capillary for a ball bonder in ball bonding; an insulating film formed on the metal film; a topmost layer metal film formed on the insulating film; a via for electrically connecting the metal film and the topmost layer metal film, being absent under the pad opening; and a protective film formed on the topmost layer metal film, the protective film having a rectangular pad opening that exposes a part of the topmost layer metal film.
  • the metal film under the topmost layer metal film in the pad opening exists not only on an outer side of the pad opening but also on the inner side of the pad opening except for a portion under the beveled corner at the tip of the capillary for the ball bonder in ball bonding.
  • the area of the metal film under the topmost layer metal film in the pad opening accordingly becomes larger, reducing the parasitic resistance to the element in the semiconductor device without enlarging the pad structure.
  • absence of the metal film under the topmost layer metal film in the pad opening inside the pad opening under the beveled corner at the tip of the capillary for the ball bonder in ball bonding increases an effective thickness of the insulating film formed under the pad opening that receives bonding damage under the beveled corner.
  • the thick insulating film absorbs the bonding damage, thus inhibiting a crack.
  • FIG. 1 are views illustrating a pad structure of the present invention.
  • FIG. 2 is a view when ball bonding to the pad structure is performed.
  • FIG. 3 are views illustrating a pad structure of the present invention.
  • FIG. 4 is a view when ball bonding to the pad structure is performed.
  • FIG. 5 is a view illustrating a pad structure of the present invention.
  • FIG. 6 is a view illustrating a pad structure of the present invention.
  • FIG. 7 are views illustrating a pad structure of the present invention.
  • FIG. 8 is a view illustrating a pad structure of the present invention.
  • FIG. 9 is a view illustrating a pad structure of the present invention.
  • FIG. 10 is a view illustrating a pad structure of the present invention.
  • FIG. 11 are views illustrating bonding damage in ball bonding.
  • FIG. 12 is a view illustrating a related-art pad structure.
  • FIG. 13 are views illustrating a related-art pad structure.
  • FIG. 1( a ) is a perspective view
  • FIG. 1( b ) is a sectional view
  • FIG. 1( c ) is a plan view for illustrating a relationship between a second metal film and a pad opening, and a topmost layer metal film 3 is omitted in FIG. 1( c ).
  • An element (not shown) is formed in a semiconductor substrate 11 .
  • a first insulating film 10 is formed on the semiconductor substrate 11 , and a first metal film 1 is formed on the first insulating film 10 .
  • the element and the first metal film 1 are electrically connected to each other through contacts 12 .
  • a second insulating film 4 is formed on the first metal film 1 , and a second metal film 2 is formed on the second insulating film 4 .
  • the first metal film 1 and the second metal film 2 are electrically connected to each other through first vias 7 formed in the second insulating film 4 .
  • a third insulating film 5 is formed on the second metal film 2 , and the topmost layer metal film 3 is formed on the third insulating film 5 .
  • the second metal film 2 and the topmost layer metal film 3 are electrically connected to each other through second vias 8 that are not arranged under a pad opening 9 .
  • a protective film 6 is formed on the topmost layer metal film 3 .
  • the protective film 6 includes the pad opening 9 that exposes a part of the topmost layer metal film 3 .
  • the pad opening 9 is rectangular, and further, in this case, square, having an opening width of d0.
  • the second metal film 2 has an opening under the pad opening 9 . This opening is also rectangular, in this case, square, having an opening width of d4.
  • a distance between an opening edge of the protective film 6 and an opening edge of the second metal film 2 is d3.
  • the second metal film 2 has a square donut shape, and protrudes to an inner side of the pad opening 9 by the distance d3.
  • the distance d3 is an amount of the protrusion of the second metal film 2 .
  • the second metal film 2 only needs to have a donut shape. Absence of the second metal film 2 at a place immediately below the pad opening 9 to the topmost layer metal film 3 increases the effective thickness of the insulating film under the pad opening 9 .
  • FIG. 11 are views illustrating bonding damage in ball bonding.
  • the cracks 18 develop due to the bonding damage, the cracks 18 do not develop under edges of a crushed ball 16 but develop under a beveled corner 13 at a tip of a capillary for a ball bonder.
  • the cracks 18 develop so as to have a width r1 of the beveled corners illustrated in FIG. 11( a ), not a width r2 of the crushed ball 16 .
  • the opening width d0 of the pad opening 9 is set to be larger than the width r2 (d0>r2). Further, the opening width d4 of the second metal film 2 under the pad opening 9 is set to be larger than the width r1 of the beveled corners (d4>r1). Developed bonding damage 17 travels from the beveled corner 13 at the tip of the capillary for the ball bonder to the topmost layer metal film 3 in the pad opening 9 .
  • the second metal film 2 does not exist under the beveled corner 13 at the tip of the capillary for the ball bonder in the ball bonding, a sum of the thickness of the second insulating film 4 and the thickness of the third insulating film 5 becomes the thickness of insulating films between the first metal film 1 and the topmost layer metal film 3 , which receives the bonding damage 17 .
  • the second metal film 2 under the topmost layer metal film 3 in the pad opening 9 exists not only on an outer side of the pad opening 9 but also on the inner side of the pad opening 9 except for a portion under the beveled corner 13 at the tip of the capillary for the ball bonder in the ball bonding.
  • the area of the metal film 2 under the topmost layer metal film 3 in the pad opening 9 becomes larger accordingly.
  • the number of the vias between the second metal film and the topmost layer metal film and the number of the vias between the first metal film and the second metal film can thus be increased without enlarging the pad structure, which reduces a parasitic resistance to the element in the semiconductor device due to the pad structure.
  • the respective metal films can be reduced in size by the protrusion of the second metal film to the inner side.
  • absence of the second metal film 2 under the topmost layer metal film 3 in the pad opening 9 under the beveled corner 13 at the tip of the capillary for the ball bonder in the ball bonding inside the pad opening 9 under the beveled corner 13 increases the effective thickness of the insulating film formed under the pad opening 9 that receives the bonding damage 17 .
  • the thick insulating film absorbs the bonding damage 17 , inhibiting a crack.
  • the element under the pad opening 9 is an ESD protection element
  • increase in an area of the second metal film 2 accordingly permits arrangement of a larger number of the first vias 7 on the second metal film 2 , reducing the parasitic resistance between the pad structure and the ESD protection element.
  • concentration of current reduces and an ESD tolerance of the ESD protection element becomes higher.
  • an element such as an ESD protection element exists under the pad opening 9
  • the present invention is not limited thereto.
  • the element such as an ESD protection element may be formed away from the pad, in which the element and the pad are electrically connected to each other through the first metal film, the second metal film, and the like.
  • the semiconductor device is manufactured using a three-layer metal process, but the present invention is not limited thereto.
  • the semiconductor device may be manufactured using a two-layer metal process.
  • both the pad opening 9 formed in the protective film 6 and the opening formed in the second metal film 2 are square, but the present invention is not limited thereto. Insofar as the relationship between the lengths expressed by the inequality used in the description is satisfied, the two openings may be rectangular or circular. Various kinds of combinations are possible.
  • FIG. 3 illustrate another pad structure of the present invention.
  • FIG. 3( a ) is a sectional view
  • FIG. 3 ( b ) is a plan view mainly for illustrating a relationship between the second metal film and the pad opening.
  • FIG. 4 is a view illustrating a case in which ball bonding to the pad structure is performed.
  • this case is different in that the second part of the second metal film 19 is formed rectangular under the pad opening 9 so as not to be held in contact with the first part of the second metal film 2 having a rectangular donut shape and formed under the pad opening 9 . It is necessary that, as illustrated in FIG. 4 , a width d5 of the second part of the second electrode film 19 be smaller than the width r1 of the beveled corners (d5 ⁇ r1).
  • the second part of the second metal film 19 is formed so as not to be directly below the beveled corner 13 and so as to be completely within the width r1 of the beveled corners.
  • the thick insulating film absorbs the bonding damage 17 , inhibiting a crack.
  • the second part of the second metal film 19 may be circular as illustrated in FIG. 5 . Further, the second part of the second metal film 19 may be a combination including a plurality of rectangles as illustrated in FIG. 6 . Further, the second part of the second metal film 19 may be a combination including a plurality of circles (not shown).
  • FIG. 7 are views illustrating a pad structure of the present invention.
  • FIG. 7( a ) is a sectional view
  • FIG. 7( b ) is a plan view mainly for illustrating a relationship between the second metal film and the pad opening.
  • this case is different in that the second part of the second metal film 19 is electrically connected to the topmost layer metal film 3 through the second vias 8 . Further, the second part of the second metal film 19 is also electrically connected to the first metal film 1 through the first vias 7 .
  • the second part of the second metal film 19 may be circular and the second vias 8 may be arranged therein.
  • the second part of the second metal film 19 may be a pattern including rectangles and the second vias 8 may be arranged therein.
  • FIG. 10 is a view illustrating a pad structure of the present invention.
  • this case is different in that the second metal film 2 having a rectangular donut shape, which is formed under the pad opening 9 , includes a slit 30 as illustrated in FIG. 10 .
  • the second metal film 2 may be U-shaped, L-shaped, or other shape (not shown) under constraints of a layout pattern.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
US14/406,997 2012-06-15 2013-05-21 Semiconductor device Abandoned US20150162296A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/879,364 US10497662B2 (en) 2012-06-15 2018-01-24 Semiconductor device and ball bonder

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2012-136288 2012-06-15
JP2012136288A JP6008603B2 (ja) 2012-06-15 2012-06-15 半導体装置
PCT/JP2013/063999 WO2013187187A1 (fr) 2012-06-15 2013-05-21 Dispositif à semi-conducteurs

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/063999 A-371-Of-International WO2013187187A1 (fr) 2012-06-15 2013-05-21 Dispositif à semi-conducteurs

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/879,364 Continuation US10497662B2 (en) 2012-06-15 2018-01-24 Semiconductor device and ball bonder

Publications (1)

Publication Number Publication Date
US20150162296A1 true US20150162296A1 (en) 2015-06-11

Family

ID=49758019

Family Applications (2)

Application Number Title Priority Date Filing Date
US14/406,997 Abandoned US20150162296A1 (en) 2012-06-15 2013-05-21 Semiconductor device
US15/879,364 Active US10497662B2 (en) 2012-06-15 2018-01-24 Semiconductor device and ball bonder

Family Applications After (1)

Application Number Title Priority Date Filing Date
US15/879,364 Active US10497662B2 (en) 2012-06-15 2018-01-24 Semiconductor device and ball bonder

Country Status (7)

Country Link
US (2) US20150162296A1 (fr)
EP (1) EP2863419B1 (fr)
JP (1) JP6008603B2 (fr)
KR (1) KR102010224B1 (fr)
CN (1) CN104350586B (fr)
TW (1) TWI588959B (fr)
WO (1) WO2013187187A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170062313A1 (en) * 2015-08-28 2017-03-02 Renesas Electronics Corporation Semiconductor device and method for manufacturing the same
US10923437B2 (en) 2014-04-14 2021-02-16 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US11251122B2 (en) 2019-10-30 2022-02-15 Kioxia Corporation Semiconductor device having a bonding pad area of a first wiring layer overlaps a bonding pad electrode of a second wiring layer
US11355467B2 (en) 2020-01-15 2022-06-07 Samsung Electronics Co., Ltd. Semiconductor devices including thick pad
US11404357B2 (en) * 2017-07-24 2022-08-02 Murata Manufacturing Co., Ltd. Semiconductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020103875A1 (fr) 2018-11-21 2020-05-28 Changxin Memory Technologies, Inc. Structure de couche de distribution et son procédé de fabrication, et structure de plot de connexion
US11887949B2 (en) * 2021-08-18 2024-01-30 Macronix International Co., Ltd. Bond pad layout including floating conductive sections
US12009327B2 (en) * 2021-08-30 2024-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313537B1 (en) * 1997-12-09 2001-11-06 Samsung Electronics Co., Ltd. Semiconductor device having multi-layered pad and a manufacturing method thereof
US6448641B2 (en) * 1999-03-19 2002-09-10 Industrial Technology Research Institute Low-capacitance bonding pad for semiconductor device
US20060065969A1 (en) * 2004-09-30 2006-03-30 Antol Joze E Reinforced bond pad for a semiconductor device
US20060125118A1 (en) * 2004-12-10 2006-06-15 Elpida Memory, Inc. Semiconductor device having a bonding pad structure including an annular contact
US20080001296A1 (en) * 2005-04-18 2008-01-03 Chao-Chun Tu Bond pad structures and semiconductor devices using the same
US20080079168A1 (en) * 2006-09-29 2008-04-03 Infineon Technologies Ag Semiconductor element comprising a supporting structure and production method
US8148797B2 (en) * 2008-06-26 2012-04-03 Taiwan Semiconductor Manufacturing Co., Ltd. Chip pad resistant to antenna effect and method

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0469942A (ja) 1990-07-11 1992-03-05 Hitachi Ltd キャピラリー及び半導体装置及びワイヤーボンディング方法
JP3086158B2 (ja) * 1995-07-26 2000-09-11 株式会社日立製作所 超音波ボンディング方法
JP3482779B2 (ja) * 1996-08-20 2004-01-06 セイコーエプソン株式会社 半導体装置およびその製造方法
JP4502173B2 (ja) * 2003-02-03 2010-07-14 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP2005005565A (ja) * 2003-06-13 2005-01-06 Matsushita Electric Ind Co Ltd 半導体装置
JP2005019493A (ja) * 2003-06-24 2005-01-20 Renesas Technology Corp 半導体装置
US7385297B1 (en) * 2005-11-14 2008-06-10 National Semiconductor Corporation Under-bond pad structures for integrated circuit devices
US7253531B1 (en) * 2006-05-12 2007-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor bonding pad structure
JP5329068B2 (ja) * 2007-10-22 2013-10-30 ルネサスエレクトロニクス株式会社 半導体装置
US8138616B2 (en) * 2008-07-07 2012-03-20 Mediatek Inc. Bond pad structure
US8183663B2 (en) * 2008-12-18 2012-05-22 Samsung Electronics Co., Ltd. Crack resistant circuit under pad structure and method of manufacturing the same
JP5250018B2 (ja) 2010-12-13 2013-07-31 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313537B1 (en) * 1997-12-09 2001-11-06 Samsung Electronics Co., Ltd. Semiconductor device having multi-layered pad and a manufacturing method thereof
US6448641B2 (en) * 1999-03-19 2002-09-10 Industrial Technology Research Institute Low-capacitance bonding pad for semiconductor device
US20060065969A1 (en) * 2004-09-30 2006-03-30 Antol Joze E Reinforced bond pad for a semiconductor device
US7115985B2 (en) * 2004-09-30 2006-10-03 Agere Systems, Inc. Reinforced bond pad for a semiconductor device
US20060125118A1 (en) * 2004-12-10 2006-06-15 Elpida Memory, Inc. Semiconductor device having a bonding pad structure including an annular contact
US20080001296A1 (en) * 2005-04-18 2008-01-03 Chao-Chun Tu Bond pad structures and semiconductor devices using the same
US20080079168A1 (en) * 2006-09-29 2008-04-03 Infineon Technologies Ag Semiconductor element comprising a supporting structure and production method
US8148797B2 (en) * 2008-06-26 2012-04-03 Taiwan Semiconductor Manufacturing Co., Ltd. Chip pad resistant to antenna effect and method

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10923437B2 (en) 2014-04-14 2021-02-16 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US11482498B2 (en) 2014-04-14 2022-10-25 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US11810869B2 (en) 2014-04-14 2023-11-07 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US20170062313A1 (en) * 2015-08-28 2017-03-02 Renesas Electronics Corporation Semiconductor device and method for manufacturing the same
US9941236B2 (en) * 2015-08-28 2018-04-10 Renesas Electronics Corporation Semiconductor device having wire bonding connection and method for manufacturing the same
US11404357B2 (en) * 2017-07-24 2022-08-02 Murata Manufacturing Co., Ltd. Semiconductor device
US11251122B2 (en) 2019-10-30 2022-02-15 Kioxia Corporation Semiconductor device having a bonding pad area of a first wiring layer overlaps a bonding pad electrode of a second wiring layer
US11355467B2 (en) 2020-01-15 2022-06-07 Samsung Electronics Co., Ltd. Semiconductor devices including thick pad
US11652076B2 (en) 2020-01-15 2023-05-16 Samsung Electronics Co., Ltd. Semiconductor devices including thick pad

Also Published As

Publication number Publication date
TWI588959B (zh) 2017-06-21
EP2863419B1 (fr) 2022-05-11
US20180294243A1 (en) 2018-10-11
TW201411795A (zh) 2014-03-16
CN104350586A (zh) 2015-02-11
CN104350586B (zh) 2017-05-31
WO2013187187A1 (fr) 2013-12-19
KR102010224B1 (ko) 2019-08-13
JP6008603B2 (ja) 2016-10-19
US10497662B2 (en) 2019-12-03
EP2863419A1 (fr) 2015-04-22
KR20150020313A (ko) 2015-02-25
JP2014003097A (ja) 2014-01-09
EP2863419A4 (fr) 2016-11-23

Similar Documents

Publication Publication Date Title
US10497662B2 (en) Semiconductor device and ball bonder
US10141278B2 (en) Chip mounting structure
JP2010135391A (ja) 半導体装置及び半導体装置の製造方法
JP2010050177A (ja) 半導体装置
JP2006294976A (ja) 半導体装置およびその製造方法
JP4293563B2 (ja) 半導体装置及び半導体パッケージ
JP2007005452A (ja) 半導体装置
US20080128826A1 (en) Semiconductor integrated circuit and fabrication method for the same
US8564100B2 (en) Semiconductor device
JP4165460B2 (ja) 半導体装置
JP3897749B2 (ja) 半導体装置
US8847391B2 (en) Non-circular under bump metallization (UBM) structure, orientation of non-circular UBM structure and trace orientation to inhibit peeling and/or cracking
JP4045261B2 (ja) 半導体装置
JP2007059867A (ja) 半導体装置
US7521778B2 (en) Semiconductor device and method of manufacturing the same
JP2008098251A (ja) 配線基板
JP2009060000A (ja) 半導体装置
US20050161792A1 (en) Junction member and multichip package using same
US10910330B2 (en) Pad structure and integrated circuit die using the same
US9508639B2 (en) Package-in-substrate, semiconductor device and module
JP4784229B2 (ja) 半導体装置
JP5265932B2 (ja) 半導体装置
JP2007019538A (ja) 半導体装置
KR20180041811A (ko) 반도체 소자
TW201123323A (en) Aligning bonding method for semiconductor package

Legal Events

Date Code Title Description
AS Assignment

Owner name: SEIKO INSTRUMENTS INC., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RISAKI, TOMOMITSU;NAKANISHI, SHOJI;SAKURAI, HITOMI;AND OTHERS;REEL/FRAME:034482/0473

Effective date: 20141126

AS Assignment

Owner name: SII SEMICONDUCTOR CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SEIKO INSTRUMENTS INC.;REEL/FRAME:038058/0892

Effective date: 20160105

AS Assignment

Owner name: ABLIC INC., JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:SII SEMICONDUCTOR CORPORATION;REEL/FRAME:045567/0927

Effective date: 20180105

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION