TWI588959B - 半導體裝置 - Google Patents
半導體裝置 Download PDFInfo
- Publication number
- TWI588959B TWI588959B TW102119166A TW102119166A TWI588959B TW I588959 B TWI588959 B TW I588959B TW 102119166 A TW102119166 A TW 102119166A TW 102119166 A TW102119166 A TW 102119166A TW I588959 B TWI588959 B TW I588959B
- Authority
- TW
- Taiwan
- Prior art keywords
- metal film
- pad
- semiconductor device
- opening
- film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 34
- 239000002184 metal Substances 0.000 claims description 123
- 229910052751 metal Inorganic materials 0.000 claims description 123
- 230000001681 protective effect Effects 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 210000001503 joint Anatomy 0.000 description 13
- 230000003071 parasitic effect Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 238000005336 cracking Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 230000005226 mechanical processes and functions Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05012—Shape in top view
- H01L2224/05013—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05012—Shape in top view
- H01L2224/05014—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
- H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
- H01L2224/05096—Uniform arrangement, i.e. array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05555—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
- H01L2224/78302—Shape
- H01L2224/78303—Shape of the pressing surface, e.g. tip or head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
本發明係關於具有焊墊構造之半導體裝置。
為了取得半導體裝置與外部電訊號往來,使用打線接合技術,以金屬之導線連結半導體裝置之焊墊和外部連接端子。打線接合技術因係使用熱、超音波、加重而將以金等所形成之導線接合於半導體裝置之焊墊的機械性工程,故有半導體裝置受損之情形。使用第11圖之(a)及(b)說明其樣子。被形成在接合線14之前端的球化導線15,被壓接於被設置在半導體裝置之焊墊開口部最上層金屬膜3,成為被壓潰之焊球16,接合線14被接合在焊墊開口部之最上層金屬膜3。此時,在焊墊開口部之下方的絕緣膜5產生龜裂18,有對半導體裝置之可靠性產生影響之情形。
在專利文獻1中,記載著為了防止龜裂,藉由球焊裝置之毛細管(capillary)構造的加工,抑制接合損壞,可以抑制產生龜裂。
在專利文獻2之先前技術中,記載著為了保持接合強
度防止龜裂,將與接合線直接接觸之焊墊開口部之金屬膜形成較厚。因其金屬膜本身吸收接合損壞,故龜裂被抑制,焊墊構造本身之龜裂耐性變高。
再者,在專利文獻3中,如第12圖所示般,表示增加受到接合損壞之焊墊開口部9之下方的絕緣膜之實效膜厚之厚度的焊墊構造。在焊墊開口部9之最上層金屬膜3之下方不設置第二金屬膜2,第一金屬膜1和最上層金屬膜3之間的絕緣膜之厚度成為第二絕緣膜4和第三絕緣膜5之厚度的合計,受到接合損壞之焊墊開口部9之下方的絕緣膜之實效膜厚變厚。因其厚的絕緣膜吸收接合損壞,故龜裂被抑制。因可以將第一金屬膜1之配線等配置在焊墊開口部9之下方,故可以縮小晶片尺寸。
[專利文獻1]日本特開平04-069942號公報
[專利文獻2]日本特開2011-055006號公報
[專利文獻3]日本特開平11-186320號公報
於專利文獻1之情形,當降低接合強度時,容易產生打線接合易脫離之缺陷。
於專利文獻2之情形,焊墊構造之最上層之金屬膜變
厚,其金屬膜之加工變得困難。其結果,無法使該金屬膜之配線之寬度充分變細,晶片尺寸變大。
在第12圖所示之專利文獻3之構造中,為了縮小焊墊構造中之半導體裝置內部之元件的寄生電阻,而不對IC之電特性造成影響,藉由如第13圖(a)所示般,增長從焊墊開口部9之開口端至焊墊構造之最上層金屬膜3之端為止之距離d1,或是如第13圖(b)所示般,增長從焊墊構造之最上層金屬膜3之端至第二金屬膜2之端為止之距離d2,使可以配置更多之通孔。但是,其部分如第13圖之剖面圖般,因焊墊構造變大,故晶片尺寸變大。
本發明係鑒於如上述般增大晶圓尺寸的弱點而創作出,其課題係提供抑制焊墊開口部之下方的龜裂且不會增大晶片尺寸之半導體裝置。
本發明為了解決上述課題,提供一種半導體裝置,屬於具有焊墊構造之半導體裝置,其特徵為具備:金屬膜,其係在焊墊開口部之下方具有矩形之開口部,為矩形環狀,在球焊時之球形接合器用毛細管前端之倒角之下方不存在,僅特定距離突出於上述焊墊開口部之內側;絕緣膜,其係被設置在上述金屬膜之上方;最上層金屬膜,其係被設置在上述絕緣膜之上方;通孔,其係在上述焊墊開口部之下方不存在,用以電性連接上述金屬膜和上述最上層金屬膜;及保護膜其係被配置在上述最上層金屬膜之上方,
具有一部分之上述最上層金屬膜露出的矩形焊墊開口部。
在本發明之焊墊構造中,焊墊開口部之最上層金屬膜之下方的金屬膜不僅在焊墊開口部之外側,也存在於除球焊時之球形接合器用毛細管前端之倒角之下方之外的焊墊開口部之內側。藉此,焊墊開口部之最上層金屬膜之下方的金屬膜之面積變寬,即使不增大焊墊構造,半導體裝置內部之元件的寄生電阻也變小。
再者,在本發明之焊墊構造中,焊墊開口部之最上層金屬膜之下方的金屬膜因在焊墊開口部之內側,不存在於球焊時之球形接合器用毛細管前端之倒角之下方,故在其倒角之下方,受到接合損壞之焊墊開口部之下方的絕緣膜之實效膜厚變厚。因其厚的絕緣膜吸收接合損壞,故龜裂被抑制。
1‧‧‧第一金屬膜
2‧‧‧第二金屬膜
3‧‧‧最上層金屬膜
4‧‧‧第二絕緣膜
5‧‧‧第三絕緣膜
6‧‧‧保護膜
7‧‧‧第一通孔
8‧‧‧第二通孔
9‧‧‧焊墊開口部
10‧‧‧第一絕緣膜
11‧‧‧半導體基板
12‧‧‧接觸件
13‧‧‧球形接和用毛細管前端之倒角
14‧‧‧接合線
15‧‧‧球化導線
16‧‧‧被壓潰之焊球
17‧‧‧接合損壞
18‧‧‧龜裂
19‧‧‧第二金屬膜
第1圖為表示發明之焊墊構造的圖示。
第2圖為對焊墊構造進行球焊之時的圖示。
第3圖為表示本發明之焊墊構造的圖示。
第4圖為對焊墊構造進行球焊之時的圖示。
第5圖為表示本發明之焊墊構造的圖示。
第6圖為表示本發明之焊墊構造的圖示。
第7圖為表示本發明之焊墊構造的圖示。
第8圖為表示本發明之焊墊構造的圖示。
第9圖為表示本發明之焊墊構造的圖示。
第10圖為表示本發明之焊墊構造的圖示。
第11圖為表示球焊之接合損壞的圖示。
第12圖為以往之焊墊構造的圖示。
第13圖為以往之焊墊構造的圖示。
以下,針對本發明之實施形態,參照圖面予以說明。
首先,針對本發明之半導體裝置之焊墊構造,使用第1圖予以說明。第1圖(a)為斜視圖,(b)為剖面圖,(c)為用以說明第二金屬膜和焊墊開口部之關係的俯視圖,無描繪最上層金屬膜3。
在半導體基板11設置有無圖示之元件。在半導體基板11上設置第一絕緣膜10,在第一絕緣膜10上設置第一金屬膜1。元件和第一金屬膜1係藉由接觸件12而電性連接。在第一金屬膜1上設置第二絕緣膜4,在第二絕緣膜4上設置第二金屬膜2。第一金屬膜1和第二金屬膜2係藉由被設置在第二絕緣膜4之第一通孔7而電性連接。在第二金屬膜2上設置第三絕緣膜5,在第三絕緣膜5上設置最上層金屬膜3。第二金屬膜2和最上層金屬膜3係藉由不配置在焊墊開口部9之下方的第二通孔8而電性連接。在最上層金屬膜3之上方設置保護膜6。
保護膜6具有最上層金屬膜3之一部分露出的焊墊開
口部9。該焊墊開口部9為矩形,又在此為正方形,開口寬為d0。第二金屬膜2在焊墊開口部9之下方具有開口部。該開口部也為矩形,在此為正方形,開口寬為d4。保護膜6之開口端和第二金屬膜2之開口端之距離為d3。第二金屬膜2為正方形之環形狀,在焊墊開口部9之內側僅距離d3突出。距離d3為第二金屬膜2之突出量。長度之間有d0=d3×2+d4,或者,d3=(d0-d4)/2之關係。一般而言,第二金屬膜2為環形狀即可。因在最上層金屬膜3之焊墊開口部9之正下方並無第二金屬膜2,故焊墊開口部9之下方的絕緣膜之實效膜厚變厚。
如先前說明般,第11圖為表示球焊之接合損壞之圖示,藉由接合損壞產生龜裂18之時,其龜裂18在被壓潰之焊球16之邊端下不產生,在球形接合器用毛細管前端之倒角13之下方產生。即是,在第11圖(b)中,龜裂18不產生被壓潰之焊球16之寬度r2,而係產生具有第11圖(a)所示之倒角彼此之寬度r1。
如第2圖所示般,因被壓潰之焊球16擴散至寬度r2,故焊墊開口部9之開口寬度d0較寬度r2寬(d0>r2)。再者,焊墊開口部9之下方的第二金屬膜2之開口寬d4,較倒角彼此之寬度r1寬(d4>r1)。所產生之接合損壞17從球形接合器用毛細管前端之倒角13傳到焊墊開口部9之最上層金屬膜3。因球焊時之球形接合器用毛細管前端之倒角13之下方無第二金屬膜2,故第二絕緣膜4和第三絕緣膜5之厚度合計成為第一金屬膜1和最上層金屬
膜3之間的絕緣膜之厚度,在此停住接合損壞17。
如上述般,在焊墊構造中,焊墊開口部9之最上層金屬膜3之下方的第二金屬膜2不僅在焊墊開口部9之外側,也存在於除球焊時之球形接合器用毛細管前端之倒角13之下方之外的焊墊開口部9之內側。藉此,焊墊開口部9之最上層金屬膜3之下方的金屬膜2之面積變寬。依此,不會增大焊墊構造,可增多第二金屬膜和最上層金屬膜之間的通孔之數量及第一金屬膜和第二金屬膜之間的通孔之數量,焊墊構造中之半導體裝置內部之元件的寄生電阻變小。或是,藉由保持通孔之數量,將寄生電阻之值保持與以往相同之狀態下,第二金屬膜突出至內側,依此可縮小各個金屬膜。
再者,在焊墊構造中,焊墊開口部9之最上層金屬膜3之下方的第二金屬膜2,在焊墊開口部9之內側,不存在於球焊時之球形接合器用毛細管前端之倒角13之下方。依此,在其倒角13之下方,受到接合損壞17之焊墊開口部9之下方之絕緣膜之實效膜厚變厚。因其厚的絕緣膜吸收接合損壞17,故龜裂被抑制。
再者,焊墊開口部9之下方的元件為ESD保護元件之時,當第二金屬膜2之面積變寬時,藉此因可以在第二金屬膜2配置較多的第一通孔7,故焊墊構造和ESD保護元件之間的寄生電阻變少。依此,電流之集中變少,ESD
保護元件之ESD耐量變高。
並且,在上述說明中,雖然敘述在焊墊開口部9之下方存在ESD保護元件等之元件之時,但是並不限定於此。ESD保護元件等之元件即使配置成與焊墊間隔開亦可,此時隔著第一金屬膜及第二金屬膜等而電性連接元件和焊墊。
再者,在上述說明中,雖然以3層金屬製程製造半導體裝置,但是並不限定於此。即使以2層金屬製程製造半導體裝置亦可。
再者,在先前說明中,雖然將設置在保護膜6之焊墊開口部9及設置在第二金屬膜2之開口部之形狀皆設為正方形,但是並不限定於此。若可以滿足以說明中使用之不等式所表示之長度之間的關係時,即使為長方形亦可,即使為圓形亦可。可做各種組合。
[變形例1]第3圖表示本發明之其他焊墊構造。(a)為剖面圖,(b)為主要用以說明第二金屬膜和焊墊開口部之關係的俯視圖。第4圖為表示對焊墊構造施予球焊之情形的圖示。
當與上述實施形態做比較之時,在此將矩形之第二的第二金屬膜19以不與焊墊開口部9之下方的矩形環形狀之第一的第二金屬膜2接觸之方式配置在焊墊開口部9之下方之點為不同。第二的第二電極膜19之寬度d5如第4圖所示般,必須較倒角彼此之寬度r1窄(d5<r1)。
如第4圖所示般,接合損壞17因從球形接合器用毛
細管前端之倒角13產生在焊墊開口部9之最上層金屬膜3,故第二的第二金屬膜19被配置成避開其倒角13之下方而完全收在倒角彼此所形成之寬度r1中。依此,受到接合損壞17之焊墊開口部9之下方的絕緣膜之實效膜厚仍厚。因其厚的絕緣膜吸收接合損壞17,故龜裂被抑制。
並且,第二的第二金屬膜19係如第5圖所示般,以可以設為圓形。再者,第二的第二金屬膜19係如第6圖所示般,即使為由複數之矩形所構成之點圖案亦可。再者,第二的第二金屬膜19雖然無圖示,即使為由複數之圓形所構成之點圖案亦可。
[變形例2]第7圖為表示本發明之焊墊構造之圖示,(a)為剖面圖,(b)為主要用以說明第二金屬膜和焊墊開口部之關係的俯視圖。
當與變形例1做比較時,在此第二的第二金屬膜19藉由第二通孔8而與最上層金屬膜3連接之點不同。再者,第二的第二金屬膜19係藉由第一通孔7而也與第一金屬膜1電性連接。
在焊墊構造中,因第一通孔7和第二通孔8和第二金屬膜19又有助於電傳導,故焊墊構造所具有之寄生電阻變小。
並且,如第8圖所示般,與第5圖相同將第二的第二金屬膜19設為圓形,亦可在其中配置第二通孔8。再者,如第9圖所示般,與第6圖相同將第二的第二金屬膜
19設為矩形的點圖案,可在其中配置第二通孔8。
[變形例3]第10圖為表示本發明之焊墊構造的圖示。
當與上述實施形態做比較時,在此焊墊開口部9之下方之矩形環形狀之第二金屬膜2如第10圖所示般,包含有縫隙30之點不同。
並且,第二金屬膜2雖然無圖示,亦可隨著佈局圖案之限制,設為U字形或L字形的形狀等。
1‧‧‧第一金屬膜
2‧‧‧第二金屬膜
3‧‧‧最上層金屬膜
4‧‧‧第二絕緣膜
5‧‧‧第三絕緣膜
6‧‧‧保護膜
7‧‧‧第一通孔
8‧‧‧第二通孔
9‧‧‧焊墊開口部
10‧‧‧第一絕緣膜
11‧‧‧半導體基板
12‧‧‧接觸件
Claims (10)
- 一種半導體裝置,具有由多層之金屬膜所構成的焊墊構造,該半導體裝置之特徵為:由下述構件所構成半導體基板;第一絕緣膜,其係被設置在上述半導體基板之表面;第一金屬膜,其係被設置在上述第一絕緣膜上;第二絕緣膜,其係被設置在上述第一金屬膜上;第一的第二金屬膜,其係被設置在上述第二絕緣膜上;第一通孔,其係用以連接被設置在上述第二絕緣膜之上述第一金屬膜和上述第一的第二金屬膜;第三絕緣膜,其係被設置在上述第一的第二金屬膜上;最上層金屬膜,其係被設置在上述第三絕緣膜上;第二通孔,其係用以連接被設置在上述第三絕緣膜之上述第一的第二金屬膜和上述最上層金屬膜;及保護膜,其係被設置在上述最上層金屬膜之上,具有用以使上述最上層金屬膜之表面之一部分露出之焊墊開口部,上述第一的第二金屬膜為環形狀,在上述焊墊開口部之下方具有開口部,上述開口部位於球焊所使用之球形接合器用毛細管(capillary)前端之倒角的外側,並且上述第一的第二金屬膜僅以特定突出量突出至上述焊墊開口部之內側。
- 如申請專利範圍第1項所記載之半導體裝置,其中上述焊墊開口部及上述開口部皆為正方形。
- 如申請專利範圍第2項所記載之半導體裝置,其中上述突出量係當將上述突出量設為d3時,將上述焊墊開口部之一邊之長度設為d0,將成為與上述一邊相同之方向的上述第一的第二金屬膜之上述開口部之一邊的長度設為d4時,則滿足d3=(d0-d4)/2之關係。
- 如申請專利範圍第2項所記載之半導體裝置,其中當將上述焊墊開口部之一邊的長度設為d0,及將位於上述第一的第二金屬膜之上述開口部之一邊之下的一邊之長度設為d4,將被壓潰之焊球的寬度設為r2,將倒角彼此的寬度設為r1時,則滿足d0>r2及d4>r1之關係。
- 如申請專利範圍第1項所記載之半導體裝置,其中又具備剖面為矩形或圓形之第二的第二金屬膜,其係在球焊時之上述倒角之下方為不存在,以不與上述焊墊開口部之下方的環形狀之上述第一的第二金屬膜相接之方式被設置在上述焊墊開口部之下方。
- 如申請專利範圍第1項所記載之半導體裝置,其中又具備剖面為複數之矩形或具有屬於圓形之集合的點圖案之第二的第二金屬膜,其係在球焊時之上述倒角之下方為不存在,以不與上述焊墊開口部之下方的環形狀之上述第一的第二金屬膜相接之方式被設置在上述焊墊開口部之下方。
- 如申請專利範圍第5或6項所記載之半導體裝置, 其中上述矩形或圓形之上述第二的第二金屬膜係藉由上述第二通孔電性連接於上述最上層金屬膜。
- 如申請專利範圍第1項所記載之半導體裝置,其中上述第一的第二金屬膜具有縫隙。
- 如申請專利範圍第1項所記載之半導體裝置,其中又具備被設置在上述焊墊開口部之下方的元件。
- 如申請專利範圍第9項所記載之半導體裝置,其中上述元件為ESD保護元件。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012136288A JP6008603B2 (ja) | 2012-06-15 | 2012-06-15 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201411795A TW201411795A (zh) | 2014-03-16 |
TWI588959B true TWI588959B (zh) | 2017-06-21 |
Family
ID=49758019
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW102119166A TWI588959B (zh) | 2012-06-15 | 2013-05-30 | 半導體裝置 |
Country Status (7)
Country | Link |
---|---|
US (2) | US20150162296A1 (zh) |
EP (1) | EP2863419B1 (zh) |
JP (1) | JP6008603B2 (zh) |
KR (1) | KR102010224B1 (zh) |
CN (1) | CN104350586B (zh) |
TW (1) | TWI588959B (zh) |
WO (1) | WO2013187187A1 (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6215755B2 (ja) | 2014-04-14 | 2017-10-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2017045910A (ja) * | 2015-08-28 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
WO2019021789A1 (ja) * | 2017-07-24 | 2019-01-31 | 株式会社村田製作所 | 半導体装置 |
WO2020103875A1 (en) | 2018-11-21 | 2020-05-28 | Changxin Memory Technologies, Inc. | Distribution layer structure and manufacturing method thereof, and bond pad structure |
JP2021072341A (ja) | 2019-10-30 | 2021-05-06 | キオクシア株式会社 | 半導体装置 |
KR20210091910A (ko) | 2020-01-15 | 2021-07-23 | 삼성전자주식회사 | 두꺼운 패드를 갖는 반도체 소자들 |
US11887949B2 (en) * | 2021-08-18 | 2024-01-30 | Macronix International Co., Ltd. | Bond pad layout including floating conductive sections |
US12009327B2 (en) * | 2021-08-30 | 2024-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6313537B1 (en) * | 1997-12-09 | 2001-11-06 | Samsung Electronics Co., Ltd. | Semiconductor device having multi-layered pad and a manufacturing method thereof |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0469942A (ja) | 1990-07-11 | 1992-03-05 | Hitachi Ltd | キャピラリー及び半導体装置及びワイヤーボンディング方法 |
JP3086158B2 (ja) * | 1995-07-26 | 2000-09-11 | 株式会社日立製作所 | 超音波ボンディング方法 |
JP3482779B2 (ja) * | 1996-08-20 | 2004-01-06 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
TW430935B (en) * | 1999-03-19 | 2001-04-21 | Ind Tech Res Inst | Frame type bonding pad structure having a low parasitic capacitance |
JP4502173B2 (ja) * | 2003-02-03 | 2010-07-14 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP2005005565A (ja) * | 2003-06-13 | 2005-01-06 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2005019493A (ja) * | 2003-06-24 | 2005-01-20 | Renesas Technology Corp | 半導体装置 |
US7115985B2 (en) * | 2004-09-30 | 2006-10-03 | Agere Systems, Inc. | Reinforced bond pad for a semiconductor device |
JP4517843B2 (ja) * | 2004-12-10 | 2010-08-04 | エルピーダメモリ株式会社 | 半導体装置 |
US7646087B2 (en) * | 2005-04-18 | 2010-01-12 | Mediatek Inc. | Multiple-dies semiconductor device with redistributed layer pads |
US7385297B1 (en) * | 2005-11-14 | 2008-06-10 | National Semiconductor Corporation | Under-bond pad structures for integrated circuit devices |
US7253531B1 (en) * | 2006-05-12 | 2007-08-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor bonding pad structure |
DE102006046182B4 (de) * | 2006-09-29 | 2010-11-11 | Infineon Technologies Ag | Halbleiterelement mit einer Stützstruktur sowie Herstellungsverfahren |
JP5329068B2 (ja) * | 2007-10-22 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8148797B2 (en) * | 2008-06-26 | 2012-04-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chip pad resistant to antenna effect and method |
US8138616B2 (en) * | 2008-07-07 | 2012-03-20 | Mediatek Inc. | Bond pad structure |
US8183663B2 (en) * | 2008-12-18 | 2012-05-22 | Samsung Electronics Co., Ltd. | Crack resistant circuit under pad structure and method of manufacturing the same |
JP5250018B2 (ja) | 2010-12-13 | 2013-07-31 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
-
2012
- 2012-06-15 JP JP2012136288A patent/JP6008603B2/ja active Active
-
2013
- 2013-05-21 KR KR1020147035015A patent/KR102010224B1/ko active IP Right Grant
- 2013-05-21 EP EP13804750.1A patent/EP2863419B1/en active Active
- 2013-05-21 US US14/406,997 patent/US20150162296A1/en not_active Abandoned
- 2013-05-21 CN CN201380029681.8A patent/CN104350586B/zh active Active
- 2013-05-21 WO PCT/JP2013/063999 patent/WO2013187187A1/ja active Application Filing
- 2013-05-30 TW TW102119166A patent/TWI588959B/zh active
-
2018
- 2018-01-24 US US15/879,364 patent/US10497662B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6313537B1 (en) * | 1997-12-09 | 2001-11-06 | Samsung Electronics Co., Ltd. | Semiconductor device having multi-layered pad and a manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
US20150162296A1 (en) | 2015-06-11 |
WO2013187187A1 (ja) | 2013-12-19 |
US20180294243A1 (en) | 2018-10-11 |
KR20150020313A (ko) | 2015-02-25 |
JP2014003097A (ja) | 2014-01-09 |
EP2863419A4 (en) | 2016-11-23 |
US10497662B2 (en) | 2019-12-03 |
JP6008603B2 (ja) | 2016-10-19 |
CN104350586A (zh) | 2015-02-11 |
EP2863419A1 (en) | 2015-04-22 |
CN104350586B (zh) | 2017-05-31 |
KR102010224B1 (ko) | 2019-08-13 |
EP2863419B1 (en) | 2022-05-11 |
TW201411795A (zh) | 2014-03-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI588959B (zh) | 半導體裝置 | |
US7298051B2 (en) | Semiconductor element and manufacturing method thereof | |
JP2008218442A (ja) | 半導体集積回路装置及びその製造方法 | |
JP2007234933A (ja) | 半導体ウエハ、半導体装置及び半導体装置の製造方法 | |
TW201530758A (zh) | 半導體裝置及半導體裝置之製造方法 | |
TWI550740B (zh) | 半導體裝置及其製造方法 | |
JP2009099838A (ja) | 半導体装置およびその製造方法 | |
JP2010050177A (ja) | 半導体装置 | |
JP2008108886A (ja) | 樹脂封止半導体装置 | |
JP2017045910A (ja) | 半導体装置および半導体装置の製造方法 | |
US9185807B2 (en) | Integrated circuit structures having off-axis in-hole capacitor | |
TW201411793A (zh) | 半導體裝置及其製造方法 | |
TW201804545A (zh) | 導電墊形成方法 | |
US8247903B2 (en) | Semiconductor device | |
JP2007059867A (ja) | 半導体装置 | |
JP2008066440A (ja) | 半導体装置およびその製造方法 | |
US20180211930A1 (en) | Semiconductor device and method for manufacturing the same | |
JP2005302941A (ja) | 半導体装置の製造方法 | |
JP6250788B2 (ja) | 半導体装置 | |
JP2005116562A (ja) | 半導体装置 | |
JP2009266998A (ja) | 半導体装置及びその製造方法 | |
JP2006120893A (ja) | 半導体装置及びその製造方法 | |
JP2006013276A (ja) | 半導体装置及びその製造方法 | |
JP2008071979A (ja) | 半導体装置および半導体装置の製造方法 | |
JPH042130A (ja) | 半導体装置 |