US20100089629A1 - Electronic component device and method for producing the same - Google Patents

Electronic component device and method for producing the same Download PDF

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Publication number
US20100089629A1
US20100089629A1 US12/629,990 US62999009A US2010089629A1 US 20100089629 A1 US20100089629 A1 US 20100089629A1 US 62999009 A US62999009 A US 62999009A US 2010089629 A1 US2010089629 A1 US 2010089629A1
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Prior art keywords
melting point
point metal
metal layer
high melting
low melting
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US12/629,990
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English (en)
Inventor
Yuji Kimura
Hiroki Horiguchi
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Assigned to MURATA MANUFACTURING CO., LTD. reassignment MURATA MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HORIGUCHI, HIROKI, KIMURA, YUJI
Publication of US20100089629A1 publication Critical patent/US20100089629A1/en
Priority to US13/181,614 priority Critical patent/US8794498B2/en
Abandoned legal-status Critical Current

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00—Assembling of devices or systems from individually processed components
    • B81C3/001—Bonding of two components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0109—Bonding an individual cap on the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0172—Seals
    • B81C2203/019—Seals characterised by the material or arrangement of seals between parts
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/03—Bonding two components
    • B81C2203/033—Thermal bonding
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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Definitions

  • the present invention relates to an electronic component device and a method for producing the same, and particularly to an electronic component device that includes conductor films including high melting point metals that are bonded to each other using a low melting point metal, and a method for producing the same.
  • FIGS. 7-1 to 7 - 4 A known method for producing an electronic component device is illustrated in FIGS. 7-1 to 7 - 4 .
  • FIGS. 7-1 to 7 - 4 illustrate a process for bonding a first component 1 and a second component 2 to each other that are to be provided in an electronic component device. Such a process is described in, for example, Japanese Unexamined Patent Application Publication No. 2002-110726.
  • the first component 1 illustrated in FIGS. 7-1 to 7 - 4 is, for example, a semiconductor chip as described in Japanese Unexamined Patent Application Publication No. 2002-110726 and the second component 2 is, for example, a substrate on which a semiconductor chip is mounted.
  • a first conductor film 3 is formed on the first component 1 and a second conductor film 4 is formed on the second component 2 as illustrated in FIG. 7-1 .
  • the first and second conductor films 3 and 4 include high melting point metals, such as Cu, for example.
  • an oxidation preventing film 5 including, for example, Au is formed on the first conductor film 3 .
  • the oxidation preventing film 5 prevents oxidation of the Cu when the first conductor film 3 includes Cu as described above.
  • a low melting point metal layer 6 including a low melting point metal having a melting point less than that of the high melting point metal is formed.
  • the low melting point metal layer 6 functions as a bonding material, and includes, for example, Sn.
  • heating is performed at a temperature between the melting point of the high melting point metals defining the conductor films 3 and 4 and the melting point of the low melting point metal defining the low melting point metal layer 6 while arranging the first conductor film 3 and the second conductor film 4 so as to face each other with the low melting point metal layer 6 being interposed therebetween as illustrated in FIG. 7-1 .
  • Au defining the oxidation preventing film 5 dissolves in the low melting point metal layer 6 , whereby the state illustrated in FIG. 7-2 is achieved.
  • the high melting point metals defining the first and second conductor film 3 and 4 are diffused in the low melting point metal layer 6 to form an intermetallic compound of the high melting point metals and the low melting point metal.
  • intermetallic compound layers 7 are formed between each of the first and second conductor films 3 and 4 and the low melting point metal layer 6 .
  • the low melting point metal layer 6 disappears, and a bonding portion 8 in which the first conductor film 3 and the second conductor film 4 are bonded to each other through the intermetallic compound layer 7 is formed as illustrated in FIG. 7-4 .
  • the low melting point metal layer 6 has a function of compensating for variations in the spacing between the first conductor film 3 and the second conductor film 4 . Therefore, the low melting point metal layer 6 must have a thickness greater than a minimum thickness. However, as the thickness of the low melting point metal layer 6 increases, the time required to diffuse the high melting point metal in the low melting point metal layer 6 increases, which results in a problem of reduced productivity.
  • the intermetallic compound formed in the intermetallic compound layer 7 is relatively hard and fragile as compared to pure metals.
  • intermetallic compounds produced by combining Cu and Sn, Cu 6 Sn 5 , Cu 3 Sn, etc. are mentioned.
  • Cu 6 Sn 5 which is particularly fragile among the intermetallic compounds listed above, is likely to be produced.
  • a stress caused by, for example, thermal expansion differences occurs between the first component 1 and the second component 2 , the distortion cannot be absorbed, and thus, cracking occurs in a portion at which Cu 6 Sn 5 is produced, which sometimes causes poor conduction.
  • FIG. 8 is a figure corresponding to FIG. 7-1 .
  • components that are equivalent to those illustrated in FIGS. 7-1 to 7 - 4 are designated by the same reference characters, and the duplicate descriptions thereof are omitted.
  • the first conductor film 3 is formed on the first component 1 , and a first low melting point metal layer 6 a is formed on the first conductor film 3 .
  • the second conductor film 4 is formed on the second component 2 , and a second low melting point metal layer 6 b is formed on the second conductor film 4 .
  • a metal powder 9 including a high melting point metal is provided on, for example, the first low melting point metal layer 6 a.
  • the first and second low melting point metal layers 6 a and 6 b are arranged with the metal powder 9 interposed therebetween and then the first conductor film 3 and the second conductor film 4 are arranged to face each other with the low melting point metal layers 6 a and 6 b interposed therebetween.
  • the high melting point metal is diffused in each of the low melting point metal layers 6 a and 6 b not only from the first and second conductor films 3 and 4 , but also from the metal powder to form an intermetallic compound. Therefore, the time required to diffuse the high melting point metal throughout the low melting point metal layers 6 a and 6 b can be reduced.
  • preferred embodiments of the present invention provide a method for producing an electronic component device in which a fragile intermetallic compound is not produced and an electronic component device produced by the method.
  • a method for producing an electronic component device includes a step of individually preparing a first component on which a first conductor film including a first high melting point metal is formed and a second component on which a second conductor film including a second high melting point metal is formed, a step of forming a low melting point metal layer including a low melting point metal having a melting point less than that of the first and second high melting point metals on at least one of the first and second conductor films, and a heat bonding step of, while the first conductor film and the second conductor film are facing each other with the low melting point metal layer being interposed therebetween, performing heating at a temperature between the melting points of the first and second high melting point metals and the melting point of the low melting point metal to form an intermetallic compound of the first and second high melting point metals and the low melting point metal, thereby forming a bonding portion in which the first conductor film and the second conductor film are bonded to each other.
  • a preferred embodiment of the present invention has the following features.
  • the method for producing an electronic component device preferably further includes a step of forming a high melting point metal layer including the same or substantially the same high melting point metal as either one of the first and second high melting point metals so as to contact the low melting point metal layer.
  • the low melting point metal layer forming step described above the low melting point metal layer is formed such that the high melting point metal layer is sandwiched between the low melting point metal layers in the thickness direction in the heat bonding step described above.
  • the high melting point metal layer formed in the high melting point metal layer forming step preferably has a thickness such that the high melting point metal is supplied in an amount greater than the amount consumed during the formation of the intermetallic compound.
  • the heat bonding step is preferably performed so that the intermetallic compound is produced while leaving a portion of the high melting point metal layer at the bonding portion.
  • the first high melting point metal and the second high melting point metal described above are the same or substantially the same.
  • the high melting point metal includes Cu as the main component
  • the low melting point metal includes Sn as the main component
  • the intermetallic compound to be produced is Cu 3 Sn
  • preferred embodiments of the present invention are particularly advantageous.
  • the low melting point metal layer including Sn as the main component is preferably formed on the first conductor film including Cu as the main component and, in contrast, the low melting point metal layer including Sn as the main component is preferably formed on the second conductor film, the high melting point metal layer including Cu as the main component is preferably formed on the low melting point metal layer, and then the low melting point metal layer including Sn as the main component is preferably formed on the high melting point metal layer, in this order.
  • the first component is a main substrate on one principal surface of which an electronic circuit formation portion and a first sealing frame surrounding the electronic circuit formation portion are formed
  • the second component is a cap substrate on one principal surface of which a second sealing frame to be bonded to the first sealing frame is formed
  • the first sealing frame is defined by the first conductor film
  • the second sealing frame is defined by the second conductor film
  • a first connecting electrode is preferably formed at a position on the one principal surface of the main substrate and is surrounded by the first sealing frame
  • a second connecting electrode is preferably formed at a position on the one principal surface of the cap substrate and surrounded by the second sealing frame
  • a process for electrically connecting the first connecting electrode and the second connecting electrode to each other is preferably performed simultaneously with the heat bonding process.
  • a first aggregate substrate and a second aggregate substrate individually providing a plurality of the first and second components are preferably prepared, and the low melting point metal layer forming step, the high melting point metal layer forming step, and the heat bonding step may preferably be performed on the first and second aggregate substrates.
  • a step of dividing the first and second aggregate substrates is preferably performed after the heat bonding process.
  • Preferred embodiments of the present invention are also directed to an electronic component device including the following features that can be advantageously produced by the production methods according to various preferred embodiments of the present invention.
  • An electronic component device includes a first component on which a first conductor film including a first high melting point metal is provided, a second component on which a second conductor film including a second high melting point metal is provided, and a bonding portion arranged to bond the first conductor film and the second conductor film to each other.
  • the bonding portion includes a first intermetallic compound layer including an intermetallic compound of the first high melting point metal and a low melting point metal having a melting point less than that of the first and second high melting point metals, a second intermetallic compound layer including an intermetallic compound of the second high melting point metal and the low melting point metal, and a high melting point metal layer that is disposed between the first and second intermetallic compound layers and that includes either one of the first and second high melting point metals.
  • the low melting point metal layer is preferably provided with a sufficient thickness such that variations in the spacing between the first conductor film and the second conductor film is sufficiently compensated for, and, in the heat bonding process, the high melting point metal layer is sandwiched between the low melting point metal layers in the thickness direction, i.e., the high melting point metal layer is disposed at the middle in the thickness direction of the low melting point metal layers as a bonding material.
  • the distance in which the high melting point metal is to be diffused in the low melting point metal layers can be decreased, and, in accordance therewith, the time required to diffuse the same can be reduced. As a result, the efficiency of the heat bonding process can be significantly improved.
  • the high melting point metal layer preferably has a thickness such that the high melting point metal can be supplied in an amount greater than the amount consumed during the formation of the intermetallic compound, and thus, the high melting point metal can be sufficiently supplied into the low melting point metal layer. Therefore, when both of the first and second high melting point metals include Cu as the main component and the low melting point metal includes Sn as the main component, Cu in a sufficient amount to form Cu 3 Sn as the intermetallic compound can be provided. Thus, the formation of Cu 6 Sn 5 , which is particularly fragile among the intermetallic compounds, is reliably prevented. Therefore, even when a stress caused by, for example, thermal expansion differences, occurs between the first component and the second component, the occurrence of cracking caused by the distortion, which results in poor conduction, is reliably prevented.
  • the above-described effect of shortening the time is particularly advantageous when the high melting point metal includes Cu as the main component and the low melting point metal includes Sn as the main component.
  • a low melting point metal layer including Sn as the main component is preferably provided on the first conductor film including Cu as the main component and, in contrast, when a low melting point metal layer including Sn as the main component is preferably provided on the second conductor film including Cu as the main component, a high melting point metal layer including Cu as the main component is preferably provided on the low melting point metal layer, and then a low melting point metal layer including Sn as the main component is preferably provided on the high melting point metal layer, in this order.
  • both the high melting point metal layer and the second conductor film each including, as the main component, Cu that is easily oxidized are covered with the low melting point metal layer including, as the main component, Sn having a function of preventing oxidation. Therefore, the high melting point metal layer including Cu as the main component and the second conductor film can preferably be advantageously prevented from being oxidized without providing an oxidation preventing film, for example.
  • first component is a main substrate on which a first sealing frame defined by the first conductor film is provided and the second component is a cap substrate on which a second sealing frame defined by the second conductor film is provided
  • preferred embodiments of the present invention can be advantageously used to bond the first sealing frame and the second sealing frame to each other while forming a sealed space between the main substrate and the cap substrate.
  • the first connecting electrode when the first connecting electrode is formed at a location surrounded by the first sealing frame, the second connecting electrode is formed at the position surrounded by the second sealing frame, and the first connecting electrode and the second connecting electrode are electrically connected to each other simultaneously when the first sealing frame and the second sealing frame are bonded to each other, electrical connection and sealing can be simultaneously performed, thereby increasing the productivity of the electronic component device.
  • the first and second components are preferably prepared via the first and second aggregate substrates, respectively, and the low melting point metal layer forming step, the high melting point metal layer forming step, and the heat bonding step are performed in a state of the first and second aggregate substrates, the production of a plurality of electronic component devices can be performed at the same time.
  • an increase in the productivity of the electronic component devices can be achieved.
  • the aggregate substrate has a wide area and the in-plane variation in the distance between the sealing frames is likely to be relatively large due to bending of the aggregate substrate, the sealing in the aggregate substrate state may produce poor sealing portions.
  • the distance between the sealing frames can be increased while maintaining a relatively short bonding time. Therefore, even when an in-plane variation occurs, sufficient sealing can be performed throughout the aggregate substrate surface while compensating for the in-plane variation.
  • the high melting point metal layer is preferably provided between the first and second intermetallic compounds.
  • the high melting point metal is softer than the intermetallic compound. Therefore, even when a stress originating from thermal expansion differences occurs between the first component and the second component, the high melting point metal layer acts to reduce the stress, thereby effectively preventing the bonding portion from breaking.
  • FIGS. 1-1 to 1 - 4 are cross sectional views illustrating processes provided in a method for producing an electronic component device according to a first preferred embodiment of the present invention.
  • FIG. 2 is a cross sectional view equivalent to FIG. 1-1 for describing a second preferred embodiment of the present invention.
  • FIG. 3 is a cross sectional view equivalent to FIG. 1-1 for describing a third preferred embodiment of the present invention.
  • FIGS. 4A to 4C are views illustrating a first example of an electronic component device to which preferred embodiments of the present invention can be applied; in which FIG. 4A is a cross sectional view of an electronic component device 31 , FIG. 4B is a view illustrating a lower principal surface 34 of a cap substrate 33 illustrated in FIG. 4A , and FIG. 4C is a view illustrating an upper principal surface 35 of a main substrate 32 illustrated in FIG. 4A .
  • FIG. 5 is a cross sectional view illustrating a second example of an electronic component device to which preferred embodiments of the present invention can be applied.
  • FIG. 6 is a cross sectional view illustrating a third example of an electronic component device to which preferred embodiments of the present invention can be applied.
  • FIGS. 7-1 to 7 - 4 are cross sectional views successively illustrating processes to be provided in an example of a known method for producing an electronic component device.
  • FIG. 8 is a cross sectional views equivalent to FIG. 7-1 for describing an example of a known method for producing an electronic component device.
  • FIGS. 1-1 to 1 - 4 are cross sectional views successively illustrating steps of a method for producing an electronic component device according to a first preferred embodiment of the present invention.
  • FIGS. 1-1 to 1 - 4 illustrate a process for bonding a first component and a second component 12 to each other that are to be provided in a specific electronic component device.
  • the first and second components 11 and 12 preferably include silicon, glass, or ceramic, for example.
  • FIG. 1-1 illustrates a state before the first component 11 and the second component 12 are bonded to each other.
  • a first conductor film 13 is formed and on the second component 12 , a second conductor film 14 is formed.
  • the first and second conductor films 13 and 14 include first and second high melting point metals, respectively.
  • the first and second high melting point metals are preferably the same and, for example, include Cu as the main component.
  • the first conductor film 13 including Cu as the main component is formed with a thickness of about 4 ⁇ m.
  • a film including Ti may preferably be formed with a thickness of about 0.05 ⁇ m, for example, as a base film contacting the first component 11 (not illustrated).
  • the second conductor film 14 including Cu as the main component is formed with a thickness of about 4 ⁇ m.
  • a film including Ti having a thickness of about 0.05 ⁇ m, for example, may preferably be formed as a base layer contacting the second component 12 (not illustrated).
  • an oxidation preventing film 15 including, for example, Au is preferably formed with a thickness of about 0.1 ⁇ m.
  • the oxidation preventing film 15 prevents oxidation of the first conductor film 13 including Cu as the main component.
  • a high melting point metal layer 17 including the high melting point metal is formed on the first low melting point metal layer 16 .
  • a second low melting point metal layer 18 including the low melting point metal is further formed.
  • the low melting point metal layers 16 and 18 function as a bonding material, and preferably include, for example, Sn as the main component.
  • the high melting point metal layer 17 includes Cu as the main component similar to the conductor films 13 and 14 .
  • the thickness of the first low melting point metal layer 16 including Sn as the main component is preferably adjusted to about 3 ⁇ m
  • the thickness of the high melting point metal layer 17 including Cu as the main component is preferably adjusted to about 6 ⁇ m
  • the thickness of the second low melting point metal layer 18 including Sn as the main component is preferably adjusted to about 3 ⁇ m.
  • the thickness of the high melting point metal layer 17 is selected so that the high melting point metal in an amount greater than the amount consumed during the formation of an intermetallic compound can be provided in a heat bonding process, which will be described later.
  • the formation of the conductor films 13 and 14 , the oxidation preventing film 15 , the low melting point metal layers 16 and 18 , and the high melting point metal layer 17 described above are preferably formed using deposition, sputtering, or metal plating, for example.
  • the film formation methods listed above facilitate the control of the supply amount, i.e., a film thickness, and, according to the film formation methods listed above, variations in the film thickness do not readily occur.
  • the first component 11 and the second component 12 are arranged near each other and are aligned while the first component 11 and the second component 12 are arranged to face each other as illustrated in FIG. 1-1 , and then pressurized.
  • a pressure of about 5 MPa to about 10 MPa, for example, is preferably supplied.
  • the oxidation preventing film 15 at the side of the first component 11 and the second low melting point metal layer 18 at the side of the second component 12 contact each other.
  • the oxidation preventing film 15 and the second low melting point metal layer 18 are in contact with each other only at a portion thereof.
  • a heat bonding step of performing heating at a temperature between the melting point of Cu as the high melting point metal and the melting point of Sn as the low melting point metal is performed while maintaining the above-described pressurization state.
  • an inert atmosphere such as a nitrogen atmosphere or a vacuum, for example, is preferably applied, and a temperature increase rate is preferably adjusted to 10° C./minute, for example.
  • the melting point of Sn is about 232° C.
  • the temperature exceeds the melting point and Sn defining the low melting point metal layers 16 and 18 melts.
  • the low melting point metal layers 16 and 18 compensate for variations in the thickness direction while being easily deformed, and the oxidation preventing film 15 contacts the second low melting point metal layer 18 over the surface thereof.
  • the increase in temperature is stopped, and then the temperature is maintained.
  • Au defining the oxidation preventing film 15 dissolves and disappears in the molten Sn which defines the second low melting point metal layer 18 .
  • the first conductor film 13 at the side of the first component 11 contacts the second low melting point metal layer 18 at the side of the second component 12 .
  • intermetallic compound layers 19 , 20 , 21 , and 22 are preferably formed between the first conductor film 13 and the second low melting point metal layer 18 , between the second low melting point metal layer 18 and the high melting point metal layer 17 , between the high melting point metal layer 17 and the first low melting point metal layer 16 , and between the first low melting point metal layer 16 and the second conductor film 14 , respectively.
  • the first and second low melting point metal layers 16 and 18 disappear, and, as a result, the intermetallic compound layers 19 and 20 are integrated to form a first intermetallic compound layer 23 and the intermetallic compound layers 21 and are integrated to form a second intermetallic compound layer 24 , as illustrated in FIG. 1-4 .
  • a bonding portion 25 in which the first conductor film 13 and the second conductor film 14 are bonded to each other is formed.
  • the high melting point metal layer 17 partially remains. Therefore, at the beginning of the formation thereof, the high melting point metal layer 17 has a thickness such that the amount of the high melting point metal is greater than the amount consumed during the formation of intermetallic compounds defining the second intermetallic compound layers 23 and 24 .
  • the high melting point metal layer 17 is sandwiched in the thickness direction by the first and second low melting point metal layers 16 and 18 in the heat bonding step while a thickness with which the variation in the interval between the first conductor film 13 and the second conductor film 14 can be sufficiently compensated for is provided for the low melting point metal layers 16 and 18 .
  • the distance in which the high melting point metal is to be diffused in each of the low melting point metal layers 16 and 18 can be reduced, and, in accordance therewith, the time required for the diffusion can be reduced.
  • the resulting component is cooled at a temperature decrease rate of, for example, about 10° C./minute.
  • Cu 6 Sn 5 When sufficient Cu is not diffused in the molten Sn, Cu 6 Sn 5 is likely to be produced as the intermetallic compound. Cu 6 Sn 5 is hard and fragile, and thus is unsuitable as a bonding material. More specifically, it has been confirmed by an experiment that, when a rupture stress that occurs when a shearing stress is applied to the bonding portion under a temperature of about 280° C. is measured, a rupture stress of about 62.1 MPa is obtained when Cu 6 Sn 5 is produced but, when Cu 3 Sn is produced, a rupture stress of about 230.9 MPa is obtained. Therefore, it is necessary to sufficiently diffuse Cu in the molten Sn to produce Cu 3 Sn as the intermetallic compound in the heating and bonding process.
  • the thickness of the high melting point metal layer 17 including Cu as the main component is sufficient and Cu can be sufficiently diffused into Sn.
  • the thickness of the films and the layers formed at a film formation rate determined so that neither non-uniformities nor defects are produced after the formation thereof and the films and the layers can be formed in the shortest amount of time as possible is as follows.
  • the ratio of the total thickness of the conductor films 13 and 14 including Cu as the main component and the high melting point metal layer 17 to the total thickness of the low melting point metal layers 16 and 18 including Sn as the main component (hereinafter referred to as a “Cu thickness/Sn thickness ratio”) is preferably at least about 4:3, for example.
  • the thicknesses of the first conductor film 13 , the second conductor film 14 , and the high melting point metal layer 17 satisfy the following relationship represented by the following expressions, Cu in an amount sufficient to produce Cu 3 Sn can be supplied into Sn and, after bonding, all of the first conductor film 13 , the second conductor film 14 , and the high melting point metal layer 17 can be made to remain.
  • the thickness of the first conductor film 13 is about 4 ⁇ m
  • the thickness of the second conductor film 14 is about 4 ⁇ m
  • the thickness of the first low melting point metal layer 16 is about 3 ⁇ m
  • the thickness of the high melting point metal layer 17 is about 6 ⁇ m
  • the thickness of the second low melting point metal layer 18 is about 3 ⁇ m
  • the total thickness of the conductor films 13 and 14 including Cu as the main component and the high melting point metal layer 17 is about 14 ⁇ m
  • the total thickness of the low melting point metal layers 16 and 18 including Sn as the main component is about 6 ⁇ m
  • the Cu thickness/S thickness ratio is about 7:3.
  • the thickness of the first conductor film 13 is preferably about 4/3 ⁇ 1 ⁇ 2 ⁇ (Thickness of second low melting point metal layer 18 ), i.e., greater than about 2 ⁇ m
  • the thickness of the second conductor film 14 is preferably about 4/3 ⁇ 1 ⁇ 2 ⁇ (Thickness of First low melting point metal layer 16 ), i.e., greater than about 2 ⁇ m
  • the thickness of the high melting point metal layer 17 is preferably about 4/3 ⁇ 1 ⁇ 2 ⁇ (Thickness of First low melting point metal layer 16 +Thickness of Second low melting point metal layer 18 ), i.e., greater than about 4 ⁇ m.
  • the thickness of a layer required to supply Cu to be diffused to the low melting point metal layers 16 and 18 each having a thickness of about 3 ⁇ m is preferably about 4 ⁇ m when conforming to the above-described Cu thickness/Sn thickness ratio.
  • the layers (the conductor films 13 and 14 and the high melting point metal layer 17 ) including Cu as the main component are present at both sides of each of the low melting point metal layers 16 and 18 . Therefore, a layer having a thickness of about 2 ⁇ m and including Cu as the main component may be present at each side of each of the low melting point metal layers 16 and 18 .
  • the high melting point metal layer 17 having a thickness of about 6 ⁇ m an intermetallic compound is produced to a depth of about 2 ⁇ m from both surfaces thereof.
  • the high melting point metal layer 17 including Cu as the main component remains and has a thickness of about 2 ⁇ m.
  • a heat retention temperature and a heat retention time in the heat bonding step are also important.
  • the heat retention temperature and the heat retention time are insufficient, only Cu 6 Sn 5 is generated in some cases.
  • the formation of Cu 3 Sn can be accelerated by further elevating the heat retention temperature or further lengthening the heat retention time. For example, it has been confirmed that when heated and maintained at about 260° C., a Cu 3 Sn layer having a thickness of about 2 ⁇ m is formed by heating and maintaining for about 15 minutes.
  • the temperature to be applied in the heat bonding process is preferably towards the higher end of a permitted range in the electronic component devices. As the heating temperature increases, the growth rate of Cu 3 Sn increases, thereby further reducing the time required for bonding.
  • FIG. 2 is a cross sectional view equivalent to FIG. 1 - 1 to describe a method of producing an electronic component device according to a second preferred embodiment of the present invention.
  • components equivalent to those illustrated in FIG. 1 are designated by the same reference characters, and the duplicate descriptions thereof are omitted.
  • the first component 11 is prepared in a state in which the second low melting point metal layer 18 is formed on the first conductor film 13 and the second component 12 is prepared in a state in which a low melting point metal layer is not formed on the high melting point metal layer 17 and the oxidation preventing film 15 is formed thereon.
  • the heat bonding step is performed, and Au defining the oxidation preventing film 15 dissolves in the second low melting point metal layer 18 , a cross sectional structure that is substantially the same as that illustrated in FIG. 1-2 is produced. Therefore, subsequent method steps are the same or substantially the same as those of the first preferred embodiment.
  • FIG. 3 is a cross sectional view equivalent to FIG. 1-1 to describe a method for producing an electronic component device according to a third preferred embodiment of the present invention.
  • components equivalent to those illustrated in FIG. 1 are designated by the same reference characters, and the duplicate descriptions thereof are omitted.
  • the second low melting point metal layer 18 is divided into two portions in the thickness direction and is formed at both sides of the first component 11 and the second component 12 . More specifically, the second low melting point metal layer 18 including Sn as the main component is formed on the first conductor film 13 including Cu as the main component. In contrast, the first low melting point metal layer 16 including Sn as the main component is formed on the second conductor film 14 including Cu as the main component, the high melting point metal layer 17 including Cu as the main component is formed on the first low melting point metal layer 16 , and the second low melting point metal layer 18 including Sn as the main component is further formed on the high melting point metal layer 17 .
  • the first conductor film 13 including Cu as the main component is covered with the second low melting point metal layer 18 including Sn as the main component.
  • the second low melting point metal layer 18 including Sn is not necessary to form an oxidation preventing film such that the use of expensive Au can be avoided.
  • Cu is preferably used as the high melting point metal, but Au, Ag, and Ni, for example, may be used in addition to Cu.
  • the first high melting point metal defining the first conductor film 13 and the second high melting point metal defining the second conductor film 14 may preferably be different from each other.
  • the high melting point metals may preferably be used as a pure metal or as a mixture with a slight amount of additives.
  • Sn is preferably used as the low melting point metal, but In, multi-component Sn-base solder, and Pb base solder, for example, may preferably be used in addition to Sn.
  • two layers of the low melting point metal layers 16 and 18 that sandwich the high melting point metal layer 17 are preferably used.
  • three or more low melting point metal layers may preferably be used, such as a low melting point metal layer/a high melting point metal layer/a low melting point metal layer/a high melting point metal layer/a low melting point metal layer/a high melting point metal layer, for example.
  • the production method according to preferred embodiments of the present invention is applied to a method of producing an electronic component device including conductor films including high melting point metals that are bonded to each other using a low melting point metal.
  • an electronic component device filters, oscillators, MEMS (Micro Electro Mechanical Systems) components, etc., may be produced, for example.
  • MEMS components a gyroscope, an acceleration sensor, etc., may be produced, for example.
  • FIGS. 4A to 4C illustrate a first example of such an electronic component device according to a preferred embodiment of the present invention.
  • the electronic component device 31 has a cross sectional structure as illustrated in 4 A and has a main substrate 32 and a cap substrate 33 facing the main substrate 32 at an interval.
  • the structure of a lower principal surface 34 of the cap substrate 33 is illustrated in FIG. 4B and the structure of an upper principal surface 35 of the main substrate 32 is illustrated in FIG. 4C .
  • an electronic circuit formation portion 36 and a first sealing frame 37 surrounding the electronic circuit formation portion 36 are provided on the upper principal surface 35 of the main substrate 32 .
  • first connecting electrodes 38 extending from the electronic circuit formation portion 36 are provided.
  • a second sealing frame 39 to be bonded to the first sealing frame 37 is provided on the lower principal surface 34 of the cap substrate 33 .
  • second connecting electrodes 40 corresponding to the first connecting electrodes 38 are provided at a position on the lower principal surface 34 of the cap substrate 33 and surrounded by the second sealing frame 39 .
  • terminal electrodes 42 are provided on the upper principal surface 41 of the cap substrate 33 . The terminal electrodes 42 are electrically connected to the second connecting electrodes 40 via through hole conductors 43 arranged so as to penetrate the cap substrate 33 in the thickness direction.
  • the production method described with reference to FIGS. 1-1 to 1 - 4 may preferably be used.
  • the equivalent relationship between the electronic component device 31 and the components illustrated in FIGS. 1-1 to 1 - 4 is as follows: the main substrate 32 is equivalent to the first component 11 and the cap substrate 33 is equivalent to the second component 12 .
  • the first sealing frame 37 is equivalent to the first conductor film 13 and the second sealing frame 39 is equivalent to the second conductor film 14 .
  • the method illustrated in FIGS. 1-1 to 1 - 4 is preferably used. In FIG. 4A , the bonding portion 44 .
  • a step of electrically connecting the first connecting electrodes 38 and the second connecting electrodes 40 to each other is performed simultaneously with a heat bonding step to bond the first sealing frame 37 and second sealing frame 39 to each other.
  • the same or substantially the same cross sectional structure as in the case of the first sealing frame 37 and the second sealing frame 39 may preferably be used.
  • the main substrate 32 and the cap substrate 33 are prepared as aggregate substrates 45 and 46 as illustrated by the phantom lines in FIGS. 4C and 4B , respectively.
  • the low melting point metal layer forming step, the high melting point metal layer forming step, and the heat bonding step described above are performed on the aggregate substrates 45 and 46 .
  • the aggregate substrates 45 and 46 may be divided after the heat bonding step.
  • the intermetallic compound layer formed at the bonding portion 44 includes Cu 3 Sn in the electronic component device 31 illustrated in FIGS. 4A to 4C as described above, the electronic circuit formation portion 36 surrounded by the sealing frames 37 and 39 are hermetically sealed with high reliability because the Cu 3 Sn has a dense structure.
  • the melting point of Cu 3 Sn is about 676° C.
  • FIGS. 5 and 6 illustrate the second and third examples of the electronic component device according to preferred embodiments of the present invention.
  • An electronic component device 51 illustrated in FIG. 5 includes a lid 54 that is bonded to a ceramic package 52 in order to accommodate an electronic component chip 53 in the ceramic package 52 and seal the electronic component chip 53 .
  • the electronic component chip 53 is flip-chip mounted on the ceramic package 52 .
  • the production method described with reference to FIGS. 1-1 to 1 - 4 may preferably be used.
  • the equivalent relationship between the electronic component device 51 and the components illustrated in FIG. 1 is as follows: the ceramic package 52 is equivalent to the first component 11 and the lid 54 is equivalent to the second component 12 .
  • a first conductor film 55 that is equivalent to the first conductor film 13 is provided at the peripheral edge portion of an opening of the ceramic package 52 and a second conductor film that is equivalent to the second conductor film 14 is provided at the bottom surface of the lid 54 .
  • the method as illustrated in FIGS. 1-1 to 1 - 4 may preferably be used. In FIG. 5 , the bonding portion 57 is illustrated.
  • An electronic component device 61 illustrated in FIG. 6 includes an electronic component chip 63 that is mounted on a substrate 62 and a shield case 64 that is bonded to the substrate 62 to shield and seal the electronic component chip 63 .
  • the electronic component chip 63 is mechanically fixed to the substrate 62 through a bonding material 65 and also is electrically connected thereto by wire bonding 66 .
  • the production method described with reference to FIGS. 1-1 to 1 - 4 may preferably be used.
  • the equivalent relationship between the electronic component device 61 and the components illustrated in FIG. 1 is as follows: the substrate 62 is equivalent to the first component 11 and the shielding case 64 is equivalent to the second component 12 .
  • a first conductor film 67 that is equivalent to the first conductor film 13 is provided on the upper surface of the substrate 62 and a second conductor film 68 that is equivalent to the second conductor film 14 is provided at the peripheral edge portion of an opening of the seal and case 64 .
  • the method illustrated in FIGS. 1-1 to 1 - 4 may preferably be used. In FIG. 5 , the bonding portion 69 is illustrated.

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JP5093235B2 (ja) 2012-12-12
EP2157605A1 (de) 2010-02-24
EP2157605A4 (de) 2013-09-25
JPWO2008149584A1 (ja) 2010-08-19
CN101681888B (zh) 2012-08-22
US20110268977A1 (en) 2011-11-03
EP2157605B1 (de) 2016-07-13
WO2008149584A1 (ja) 2008-12-11
US8794498B2 (en) 2014-08-05

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