US20090089633A1 - Semiconductor Testing Apparatus and Method - Google Patents

Semiconductor Testing Apparatus and Method Download PDF

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Publication number
US20090089633A1
US20090089633A1 US12/196,420 US19642008A US2009089633A1 US 20090089633 A1 US20090089633 A1 US 20090089633A1 US 19642008 A US19642008 A US 19642008A US 2009089633 A1 US2009089633 A1 US 2009089633A1
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Prior art keywords
test
cell
execution unit
function
power
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English (en)
Inventor
Akihiro Hirota
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Lapis Semiconductor Co Ltd
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Oki Electric Industry Co Ltd
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Assigned to OKI ELECTRIC INDUSTRY CO., LTD. reassignment OKI ELECTRIC INDUSTRY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HIROTA, AKIHIRO
Assigned to OKI SEMICONDUCTOR CO., LTD. reassignment OKI SEMICONDUCTOR CO., LTD. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: OKI ELECTRIC INDUSTRY CO., LTD.
Publication of US20090089633A1 publication Critical patent/US20090089633A1/en
Priority to US13/081,189 priority Critical patent/US8225149B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/146—Write once memory, i.e. allowing changing of memory content by writing additional bits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM

Definitions

  • the present invention relates to a semiconductor testing or inspecting apparatus and method, and particularly to screening of a non-volatile semiconductor memory.
  • a result of a pretest in a laser repair process for, when a defective memory cell exists in a memory array, substituting a spare memory array therefor by blowing a fuse provided within the semiconductor memory is stored in the semiconductor memory.
  • the test result stored in the memory is read and unnecessary tests are omitted.
  • a contact test, a DC test (Direct Current Test) and an FC test (FunCtion test) are performed in order and thereby a decision as to whether the semiconductor memory is good or bad is made (refer to a patent document 1 (Japanese Unexamined Patent Publication No. Hei 08(1996)-023016)).
  • the invention of the present application has been made with the foregoing in view. It is an object of the present invention to obtain a semiconductor inspecting or testing apparatus and method capable of reliably determining whether a semiconductor memory is good or bad.
  • a semiconductor testing apparatus for mounting a device having a plurality of normal cells each having a memory function for accumulating an electric charge by a floating gate thereof and a control gate thereof thereby to store information, and at least one reference cell identical in structure and function to each of the normal cells and taken as a reference object for an operating state of the normal cell, to a mounting portion as an object to be tested thereby to supply power to the device and testing an operating state of the device, comprising function test execution unit for operating each of the normal cells as an object on a pseudo basis to perform a function test on the corresponding cell with the reference cell as a reference, and power supply control unit for controlling the supply of power in such a manner that after the completion of execution of the function test execution unit, the supply thereof from the mounting portion to the device is stopped and the power is supplied again after a predetermined time, wherein the function test execution unit performs at least one the function test, based on the function test execution unit after the resupply of power
  • a semiconductor testing apparatus for mounting a device having a plurality of normal cells each including a memory function for accumulating an electric charge by a floating gate thereof and a control gate thereof thereby to store information, and at least one reference cell identical in structure and function to each of the normal cells and taken as a reference object for an operating state of the normal cell, to a mounting portion as an object to be tested thereby to supply power to the device and testing an operating state of the device, comprising contact test execution unit for performing a contact test for determining electrical conduction between the mounting portion and pads or terminals of the device on all of the pads or terminals, dc test execution unit for performing a dc test for inspecting a state of a direct current characteristic at an input/output of the device on all the cells, function test execution unit for operating each of the normal cells as an object on a pseudo basis to perform a function test on the corresponding cell with the reference cell as a reference, and power supply control unit for controlling the supply
  • a semiconductor testing apparatus wherein in the semiconductor testing apparatus according to the first or second aspect, the normal cells are classified into plural sets and one the reference cell is provided for each set, and the function test execution unit performs a function test on the corresponding cell for every set.
  • a semiconductor testing apparatus wherein in the semiconductor testing apparatus according to the second or third aspect, the contact test execution unit is executed after the elapse of the predetermined time and before the resupply of the power.
  • a semiconductor testing apparatus for mounting a device having a plurality of normal cells each having a memory function for accumulating an electric charge by a floating gate thereof and a control gate thereof thereby to store information, and at least one reference cell identical in structure and function to each of the normal cells and taken as a reference object for an operating state of the normal cell, to a mounting portion as an object to be tested thereby to supply power to the device and testing an operating state of the device, comprising function test execution unit for operating each of the normal cells as an object on a pseudo basis to perform a function test on the corresponding cell with the reference cell as a reference, wherein the function test execution unit preferentially performs a decision as to whether the operation of the reference cell is good, by conducting at least one the function test.
  • a semiconductor testing apparatus for mounting a device having a plurality of normal cells each having a memory function for accumulating an electric charge by a floating gate thereof and a control gate thereof thereby to store information, and at least one reference cell identical in structure and function to each of the normal cells and taken as a reference object for an operating state of the normal cell, to a mounting portion as an object to be tested thereby to supply power to the device and testing an operating state of the device, comprising contact test execution unit for performing a contact test for determining electrical conduction between the mounting portion and pads or terminals of the device on all of the pads or terminals, function test execution unit for operating each of the normal cells as an object on a pseudo basis after the supply of the power thereby to preferentially execute a decision as to whether the operation of the reference cell is good, by conducting at least one the function test based on a function test on the corresponding cell with the reference cell as a reference and operating each of the normal cells other that the normal
  • a semiconductor testing apparatus for mounting a device having a plurality of normal cells each including a memory function for accumulating an electric charge by a floating gate thereof and a control gate thereof thereby to store information, and at least one reference cell identical in structure and function to each of the normal cells and taken as a reference object for an operating state of the normal cell, to a mounting portion as an object to be tested thereby to supply power to the device and testing an operating state of the device, comprising contact test execution unit for performing a contact test for determining electrical conduction between the mounting portion and pads or terminals of the device on all of the pads or terminals, function test execution unit for supplying the power after execution of the contact test execution unit, operating each of the normal cells as an object on a pseudo basis thereby to determine whether the operation of the reference cell is good, by conducting at least one function test based on the function test on the corresponding cell with the reference cell as a reference and performing the function test on all the remaining normal cells as objects,
  • a semiconductor testing apparatus wherein in the semiconductor testing apparatus according to the sixth or seventh aspect, the normal cells are classified into plural sets and one the reference cell is provided for each set, and the function test execution unit performs a function test on the corresponding cell for every set.
  • a semiconductor testing method for mounting a device having a plurality of normal cells each having a memory function for accumulating an electric charge by a floating gate thereof and a control gate thereof thereby to store information, and at least one reference cell identical in structure and function to each of the normal cells and taken as a reference object for an operating state of the normal cell, to a mounting portion as an object to be examined thereby to supply power to the device and testing an operating state of the device, comprising the steps: a function test executing step for operating each of the normal cells as an object on a pseudo basis to perform a function test on the corresponding cell with the reference cell as a reference, a power supply control step for controlling the supply of power in such a manner that after the completion of execution of the function test executing step, the supply thereof from the mounting portion to the device is stopped and the power is supplied again after a predetermined time, and a determining step for performing at least one the function test, based on the function test execution
  • a semiconductor testing method for mounting a device having a plurality of normal cells each having a memory function for accumulating an electric charge by a floating gate thereof and a control gate thereof thereby to store information, and at least one reference cell identical in structure and function to each of the normal cells and taken as a reference object for an operating state of the normal cell, to a mounting portion as an object to be tested thereby to supply power to the device and testing an operating state of the device, comprising the steps: a contact test executing step for performing a contact test for determining electrical conduction between the mounting portion and pads or terminals of the device on all of the pads or terminals, a dc test executing step for performing a dc test for inspecting a state of a direct current characteristic at an input/output of the device on all the cells, a function test executing step for operating each of the normal cells as an object on a pseudo basis to perform a function test on the corresponding cell with the reference cell
  • a semiconductor testing method for mounting a device having a plurality of normal cells each having a memory function for accumulating an electric charge by a floating gate thereof and a control gate thereof thereby to store information, and at least one reference cell identical in structure and function to each of the normal cells and taken as a reference object for an operating state of the normal cell, to a mounting portion as an object to be tested thereby to supply power to the device and testing an operating state of the device, comprising the steps: a function test executing step for operating each of the normal cells as an object on a pseudo basis to perform a function test on the corresponding cell with the reference cell as a reference, and a decision priority executing step for preferentially performing a decision as to whether the operation of the reference cell is good, by conducting at least one the function test, based on the function test executing step.
  • a semiconductor testing method for mounting a device having a plurality of normal cells each including a memory function for accumulating an electric charge by a floating gate thereof and a control gate thereof thereby to store information, and at least one reference cell identical in structure and function to each of the normal cells and taken as a reference object for an operating state of the normal cell, to a mounting portion as an object to be tested thereby to supply power to the device and testing an operating state of the device, comprising the steps: a contact test executing step for performing a contact test for determining electrical conduction between the mounting portion and pads or terminals of the device on all of the pads or terminals, a decision priority executing step for operating each of the normal cells as an object on a pseudo basis after the supply of the power thereby to preferentially execute a decision as to whether the operation of the reference cell is good, by conducting at least one the function test based on a function test on the corresponding cell with the reference cell as a reference,
  • a semiconductor testing method for mounting a device having a plurality of normal cells each having a memory function for accumulating an electric charge by a floating gate thereof and a control gate thereof thereby to store information, and at least one reference cell identical in structure and function to each of the normal cells and taken as a reference object for an operating state of the normal cell, to a mounting portion as an object to be tested thereby to supply power to the device and testing an operating state of the device, comprising the steps: a contact test executing step for performing a contact test for determining electrical conduction between the mounting portion and pads or terminals of the device on all the pads or terminals, a decision executing step for supplying the power after execution of the contact test executing step and operating each of the normal cells as an object on a pseudo basis thereby to determine whether the operation of the reference cell is good, by conducting at least one function test based on the function test on the corresponding cell with the reference cell as a reference, a function test test
  • FIG. 1 is a configuration diagram of a non-volatile semiconductor memory showing a device according to a first preferred embodiment of the invention of the present application;
  • FIG. 2 is a first flowchart for inspecting a wafer level OTP according to the first preferred embodiment of the invention of the present application;
  • FIG. 3 is a second flowchart for inspecting the packaged OTP according to the first preferred embodiment of the invention of the present application
  • FIG. 4 is a third flowchart for inspecting a wafer level OTP according to a second preferred embodiment of the invention of the present application.
  • FIG. 5 is a fourth flowchart for inspecting the packaged OTP according to the second preferred embodiment of the invention of the present application.
  • FIG. 6 shows a wafer level test process according to a prior art
  • FIG. 7 shows a packaged test process according to the prior art
  • FIG. 8 shows the state of defects in the gate of a reference column switch transistor according to the prior art.
  • FIG. 1 is a configuration diagram of a non-volatile semiconductor memory 100 showing a device according to a first preferred embodiment of the invention of the present application.
  • the non-volatile semiconductor memory 100 corresponding to the device is also called “one time PROM (One Time Programmable Read Only Memory), which is hereinafter referred to as “OTP 100 ”.
  • the OTP 100 is equivalent to one in which an ultra violet-erasable PROM (UV-EPROM: Ultra Violet-Erasable Programmable Read Only Memory, which is hereinafter called “EPROM”) is encapsulated (resin-sealed) in a plastic package with no ultraviolet penetration.
  • EPROM Ultra Violet-Erasable Programmable Read Only Memory
  • the number of writings is limited to once because the contents stored cannot be erased by ultraviolet irradiation as in the EPROM.
  • the OTP 100 is very lower in cost than other EPROMs owing to the use of the plastic package therein.
  • non-volatile semiconductor memory 100 may be an EEPROM (Electric Erasable Programmable Read Only Memory) or a flash memory.
  • EPROM Electrical Erasable Programmable Read Only Memory
  • all data are batch-erased using an EPROM eraser and data is written again by a PROM writer.
  • EEPROM Electrical Erasable Programmable Read Only Memory
  • an arbitrary one bit is designated using word and bit lines and data is erased and written electrically.
  • the erasure of data can be conducted only in block units of predetermined bytes or the like in the flash memory, the writing thereof is enabled in a one-bit unit.
  • the OTP 100 comprises a memory cell array 110 , a column switch group 120 , a detector 130 and a reference detector 140 .
  • the memory cell array 110 is connected to the column switch group 120 .
  • the column switch group 120 is connected to the detector 130 and the reference detector 140 .
  • the memory cell array 110 comprises a selection word line (hereinafter called “selection WL”) 112 , a normal cell transistor 114 and a reference cell transistor 116 .
  • selection WL selection word line
  • the normal cell transistor 114 and the reference cell transistor 116 respectively have a memory function for accumulating electric charges therein by floating and control gates thereby to store information and have the same structure and function.
  • the control gates of the reference cell transistor 116 and the normal cell transistor 114 are connected to the selection WL 112 and shared therefor.
  • the selection WL 112 there is a case where one reference cell transistor 116 is connected to the selection WL 112 , and there is also a case where a plurality of the reference cell transistors 116 are connected thereto.
  • a plurality of the normal cell transistors 114 are connected to the selection WL 112 .
  • a plurality of the selection WLs 112 exist in the memory cell array 110 .
  • the capacity of the memory cell array 110 is determined depending on the number of the selection WLs 112 and the amount of the normal cell transistors 114 respectively connected to the selection WLs 112 .
  • a cell drain 114 d is connected to one end of the normal cell transistor 114 and supplied with a drain voltage. Even in the case of the reference cell transistor 116 in a manner similar to the normal cell transistor 114 , a cell drain 116 d is connected to one end of the reference cell transistor 116 and supplied with a drain voltage.
  • bit line 114 b is connected to the other end of the normal cell transistor and a normal cell current Icell flows therethrough. Even in the reference cell transistor 116 , a reference bit line 116 b is connected to the other end of the reference cell transistor 116 and a reference cell current Iref flows therethrough.
  • bit line 114 b is connected between division resistors Ra and Rb of the detector 130 (connected to a detector output DO) via a column switch transistor 124 of the column switch group 120 .
  • bit line 116 b is connected between division resistors Ra/2 and Rb/2 of the reference detector 140 (connected to a reference detector output RDO) via a column switch transistor 126 of the column switch group 120 .
  • a read operation of the OTP 100 will be explained with reference to FIG. 1 .
  • FIG. 1 shows a simplified one of a circuit diagram at the reading of the OTP 100 .
  • One normal cell transistor 114 lying within the memory cell array 110 is supplied with a drain voltage from its cell drain 114 d.
  • the reference cell transistor 116 is supplied with a drain voltage from its cell drain 116 d.
  • a normal cell current Icell flows from the cell drain 114 d to the detector 130 via the bit line 114 b.
  • a voltage of 3.6V is applied to the selection WL 112 and a voltage of 1.0V is applied to the cell drain 114 d, so that the normal cell current Icell flows into the detector 130 via the bit line 114 b.
  • the detector 130 is simplified by such an equivalent circuit as shown in FIG. 1 .
  • the voltage of the detector output DO can be expressed in terms of Ra (VCC/(Ra+Rb)+Icell).
  • the normal voltage VCC is of 3.3V (for example, standard: 3.3V ⁇ 0.3V).
  • 3.3V of the normal voltage VCC is applied to the gates 124 g and 126 g of the column switch transistor 124 and reference column switch transistor 126 respectively so that they are respectively brought to an ON state (active state).
  • the gate 126 g of the reference column switch transistor 126 is in a normally ON state and always supplied with the voltage of 3.3V.
  • connection of the gate 126 g of the reference column switch transistor 126 to the power supply VCC is made to compare the reference cell current Iref that flows from the reference cell transistor 116 and the normal cell current Icell that flows from the normal cell transistor 114 . Therefore, there is a need to cause the current to flow at all times without depending on the column address. This is also made because there is a need to make the above connection via the reference column switch transistor 126 in such a manner that no difference occurs between a current path of the normal cell transistor 114 and a current path of the reference cell transistor 116 .
  • the reference cell current Iref also flows into the reference detector 140 in a manner similar to the normal cell current Icell, the inter-source resistance becomes 1 ⁇ 2 in the reference detector 140 as compared with the detector 130 , and the reference detector output RDO is brought to Ra (VCC/(Ra+Rb)+Iref/2).
  • “0” and “1” are determined by making a comparison between the reference detector output RDO and the detector output DO, based on the electric charge accumulated in the normal cell transistor 114 of the OTP 100 .
  • the threshold voltage Vt of the normal cell transistor 114 is higher than the voltage level of the selection WL 112 and no normal cell current Icell flows.
  • DO ⁇ RDO ⁇ Ra (Iref/2)
  • the threshold voltage Vt of the normal cell transistor 114 is lower than the voltage level of the selection WL 112 and the normal cell current Icell flows.
  • the threshold voltage Vt of the normal cell transistor 114 is lower than the voltage level of the selection WL 112 and the normal cell current Icell flows.
  • data is brought to “1” in the blank state, electrons are being emitted into the floating gate of the normal cell transistor 114 .
  • the UV-EPROM for example, the electrons confined within the floating gate by ultraviolet irradiation are emitted so that data is erased (brought to “1”). Similarly, data is electrically erased (brought to “1”) even in the case of the EEPROM.
  • FIG. 6 shows a wafer level test process 600 in a prior art.
  • the test process 600 of FIG. 6 indicates where a wafer level OTP 100 is tested using a probe card.
  • the test process for the OTP 100 is broadly divided into three process steps corresponding to a contact test of Step 610 , a DC test of Step 620 and an FC test (function test) of Step 630 .
  • the FC test of Step 630 further consists of three process steps: a “1” reading test of Step 630 a, “0” writing of Step 630 b and a “0” and “1” reading test of Step 630 c.
  • the contact test unit a test on contact and conducts a test of whether each of pads (or terminals) of a DUT (Device Under Test) corresponding to an actual device such as the OTP 100 and an inspection terminal of semiconductor testing equipment or apparatus (hereinafter called “LSI tester”) are in contact with each other. Described in detail, a test on the contact between the pad and the inspection terminal of the LSI tester is conducted on a contact test on a wafer. In the case of a contact test on an IC (Integrated Circuit) brought into a package such as a plastic package or a ceramic package, a test on the contact between each terminal of the IC and the inspection terminal of the LSI tester is conducted.
  • IC Integrated Circuit
  • a DUT equipped with a normal cell and a reference cell that becomes a basic target for the normal cell is mounted to a mounting portion (via a probe card or an inspecting board) of the LSI tester as a target to be inspected or examined thereby to perform its test.
  • a contact test on the NC terminal is not conducted.
  • the DC test corresponding to a direct current test for testing the state of a DC characteristic at the input/output of the device is also called “DC parametric test” and measures the DC characteristic.
  • the DC test includes, for example, an input leak test, an output leak test, a source current test, a quiescent source current test, an input current test and an output current test or the like.
  • FC test The function test (hereinafter called “FC test”) unit that each cell to be examined of the OTP 100 (device) is operated on a pseudo basis to conduct a function test on the cell (perform a function test under actual operating conditions). Described in detail, the FC test indicates a function test or an actual operation test. On the FC test, a function test on an actual operation for each circuit block (or over the entire integrated circuit) mounted to an IC or LSI (Large Scale Integrated Circuit) or the like is carried out.
  • FC test The function test (hereinafter called “FC test”) unit that each cell to be examined of the OTP 100 (device) is operated on a pseudo basis to conduct a function test on the cell (perform a function test under actual operating conditions). Described in detail, the FC test indicates a function test or an actual operation test. On the FC test, a function test on an actual operation for each circuit block (or over the entire integrated circuit) mounted to an IC or LSI (Large Scale Integrated Circuit) or
  • Step 630 a Since UV (Ultra-Violet) irradiation is required to return “0” (write state) to “1” (blank state) in the OTP 100 , the “1” reading test of Step 630 a is generally executed and thereafter the “0” writing of Step 630 b is executed. Finally, the “0” and “1” reading test of Step 630 c is executed.
  • data about fixed patterns corresponding to predetermined pattern data and hereinafter called fixed pattern data
  • fixed pattern data are used as the data of “0” and “1” here.
  • Step 630 a since the initial state is of the blank state, the “1” reading test of Step 630 a is first carried out upon inspection of the blank state (because there is a case where when the device is defective, the initial state does not reach “1” indicative of the blank state).
  • the “0” writing at the fixed pattern data, of Step 630 b is executed.
  • the “0” and “1” reading test of Step 630 c is finally carried out. Since there is a case in which at Step 630 b, the “0” of the fixed pattern data is not written properly or the “1” of the fixed pattern data is erroneously reprogrammed or rewritten into “0”, the “0” and “1” reading test of Step 630 c is carried out. Since the FC test of Step 630 is long in test time, the contact test of Step 610 shorter in test time, and the DC test of Step 620 are executed before the FC test of Step 630 .
  • FIG. 7 shows a packaged test process 700 in a prior art.
  • the OTP 100 placed in the packaged state (only one-time writable or programmable EPROM) is not capable of erasing stored data using UV irradiation.
  • Step 710 a test similar to the contact test of Step 610 in FIG. 6 is carried out.
  • Step 720 a test similar to the DC test of Step 620 in FIG. 6 is performed.
  • An FC test of Step 730 is basically of a test similar to the FC test of Step 630 in FIG. 6 . Unlike the FC test of Step 640 in FIG. 6 , however, the process of writing specific user data prepared in advance into a plurality of normal cells contained in the OTP 100 without using the fixed pattern data at the writing of Step 730 a is executed. At a “0” and “1” reading test of Step 730 b, “0” and “1” of written used data are read to make a decision as to whether the user data are being written properly.
  • Power supply timings in the test processes of the OTP 100 are also shown in FIGS. 6 and 7 .
  • the power is turned ON continuously subsequent to the DC tests of Steps 620 and 720 .
  • the power is turned ON immediately again to execute the next test. From this regard, the time during which the power is being ON from before test execution, becomes long on the FC tests of Steps 630 and 730 .
  • FIG. 8 shows the state of defects in a gate 126 g of a reference column switch transistor 126 according to a prior art.
  • each wiring or Via (Via: connection region that electrically couples an upper layer wiring and a lower layer wiring in a multilayered interconnection or wiring) is high in resistance or broken.
  • FIG. 8A shows the state of the reference column switch transistor 126 corresponding to a normally ON transistor just after the supply of power.
  • FIG. 8B shows the state of the reference column switch transistor 126 corresponding to the normally ON transistor at the time that it is left for a while the supply of power remains held. Since, at this time, the gate level is charged with the elapse of time after the power supply although the high resistance or breaking of the wiring or Via exists, the transistor is brought to an ON state so that the current flows into the transistor.
  • FIG. 2 shows a first flowchart 200 for inspecting a wafer level OTP 100 according to the first preferred embodiment of the invention of the present application.
  • the inspection of the OTP 100 by the first flowchart 200 indicates where the wafer level OTP 100 is tested using a probe card.
  • a contact test is conducted. Described in detail, a contact test as to whether a probe or inspection needle corresponding to an inspection terminal of the probe card connected (mounted) to the inspection terminal of the LSI tester, and its corresponding pad of the wafer level OTP 100 corresponding to an inspected object (device) mounted to the mounting portion of the LSI tester are in contact.
  • a DC test is done. Described in detail, the wafer level OTP 100 is supplied with power from the LSI tester via the probe card to perform the DC test of the OTP 100 , whereby the DC characteristic of the OTP 100 is measured.
  • Step 230 an FC test is conducted. Described in detail, the conventional FC test (test similar to the FC test of Step 630 in FIG. 6 ) is carried out. A “1” reading test in an initial state of Step 230 a, “0” writing at fixed pattern data of Step 230 b, and a “0” and “1” reading test at fixed pattern data of Step 230 c are executed. Incidentally, the reason why the “1” reading test is done again at Step 230 c, is the same as when the conventional FC tests 630 c and 730 b in FIGS. 6 and 7 are performed.
  • Steps 230 a, 230 b and 230 c “0” or “1” of the normal cell transistor 114 is determined by making a comparison between a detector output DO of each normal cell and a reference detector output RDO of a reference cell, and the “1” reading test, “0” writing and “0” and “1” reading test are conducted. A method for its comparison is determined based on a voltage value of the detector output DO—the reference detector output RDO.
  • the normal cell transistor 114 , the column switch transistor 124 of the column switch group 120 , and the detector 130 all of which are shown in FIG. 1 , are generically called “normal cell”.
  • the reference cell transistor 116 , the column switch transistor 126 of the column switch group 120 , and the reference detector 140 are generically referred to as each reference cell.
  • Step 240 the power is turned OFF. Described in detail, the power supplied from the corresponding inspection or testing equipment to the OTP 100 is cut off or shut down here to free the electric charge of the gate 126 g of the reference column switch transistor 126 , which might have been charged.
  • the power OFF is maintained for a predetermined time. Described in detail, the power is turned OFF for about a few minutes (specifically, a time interval ranging from about 5 minutes to about 10 minutes) to free the electric charge accumulated in the gate 126 g of the reference column switch transistor 126 as descried at Step 240 .
  • Step 260 a contact test is carried out. Described in detail, it performs exactly the same operation as Step 210 . Incidentally, here, the execution of the contact test is done because there is a possibility that since the power has been supplied for a long time on the FC test of Step 230 and the transfer of data between the LSI tester and the OTP 100 has been performed, heat would have been generated in the inspection needle of the probe card or each pad of the OTP 100 .
  • Step 270 the power is turned ON. Described in detail, the power is supplied to carry out tests subsequent to Step 280 .
  • an FC test on a cell corresponding to one bit is executed. Described in detail, a “0” reading test on the one-bit cell at Step 280 a is carried out. And so, reference cells of more than at least one exist in the selection WL 112 , and a plurality of normal cells are respectively connected thereto in association with one another. When, for example, one reference cell that exists in the selection WL 112 is connected to a predetermined number of normal cells, any one of the normal cells and its corresponding reference cell are compared and the “0” reading test is conducted. This is represented as the “0” reading test of the one-bit cell being conducted.
  • a decision as to whether the reference cell is good or bad is made by conducting at least one function test, based on the function test of each normal cell. Of the normal cells corresponding to the respective reference cells, the “0” reading test is conducted on all the reference cells one by one by the reference cells.
  • Step 280 It is determined at Step 280 whether the OTP 100 is good or bad. Then, the test is ended and the power is turned OFF.
  • Step 280 a Whether the reference cell is good or bad can be determined by the “0” reading test of Step 280 a.
  • FIG. 3 shows a second flowchart 300 for examining or inspecting the packaged OTP 100 according to the first preferred embodiment of the invention of the present application.
  • the inspection of the OTP 100 by the second flowchart 300 indicates where the packaged OTP 100 is tested using an inspecting board.
  • a contact test of Step 310 is of a test similar to the contact test of Step 210 of FIG. 2 . Described in detail, there is a difference in that an object to be inspected or examined is of the wafer level OTP 100 at Step 210 of FIG. 2 , and the object is of the packaged OTP 100 at Step 310 of FIG. 3 .
  • the contact test is made as to whether an inspection terminal (IC socket) of the inspecting board connected (mounted) to its corresponding inspection terminal of the LSI tester, and a terminal of the OTP 100 (packaged IC) set to the IC socket of the inspecting board mounted to its corresponding mounting portion of the LSI tester are in contact with each other.
  • a DC test of Step 320 is of a DC test similar to the Step 220 of FIG. 2 .
  • An FC test of Step 330 and the FC test of Step 230 of FIG. 2 are basically identical to each other.
  • user data is written at Step 330 a, and whether the written user data is proper or correct is determined by a “0” and “1” reading test of Step 330 b.
  • Power-OFF of Step 340 is of a process similar to Step 240 of FIG. 2 .
  • Maintaining the power-OFF for a predetermined time at Step 350 is of a process similar to Step 250 of FIG. 2 .
  • a contact test of Step 360 is of a test similar to the contact test of Step 310 .
  • Power-ON of Step 370 is of a process similar to Step 270 of FIG. 2 .
  • An FC test of Step 380 is of an FC test similar to the FC test of Step 280 in FIG. 2 (an FC test of Step 380 a is also of an FC test similar to the FC test of Step 280 a in FIG. 2 ).
  • Step 380 It is determined at Step 380 whether the OTP 100 is good or bad. Then, the test is ended and power is cut off.
  • the decision as to whether the reference cell is good or bad is made by Step 380 . Therefore, the defect of the reference bit line 116 b due to the breaking or high resistance of the gate of the reference column switch transistor 126 corresponding to the normally ON transistor can be screened.
  • the time provided to turn off the power using such a method as to forcibly free the electric charge charged into the gate of the reference column switch transistor 126 corresponding to the normally ON transistor in a short period of time may be shortened.
  • FIG. 4 shows a third flowchart 400 for inspecting a wafer level OTP 100 according to the second preferred embodiment of the invention of the present application.
  • FIG. 4 illustrative of the third flowchart 400 for inspecting the OTP 100 according to the second preferred embodiment of the invention of the present application is of a screening method applied where such a defect as described in FIG. 8 exists in the reference bit line 116 b.
  • An inspection process is divided broadly into a contact test of Step 410 , an FC test of Step 420 and a DC test of Step 430 .
  • the FC test of Step 420 consists of two process steps of an FC test of Step 440 and an FC test of Step 450 .
  • the FC test of Step 440 comprises three process steps of an FC test of Step 440 a, an FC test of Step 440 b and an FC test of Step 440 c.
  • the FC test of Step 450 consists of three process steps of an FC test of Step 450 a, an FC test of Step 450 b and an FC test of Step 450 c.
  • the contact test is carried out. Described in detail, the contact test is similar to the process steps corresponding to Steps 210 and 260 in FIG. 2 .
  • Step 420 the FC test is performed. Described in detail, the FC test of Step 440 and the FC test of Step 450 are executed on the FC test of Step 420 .
  • Step 440 a On the FC test of Step 440 a in the FC test of Step 440 , a “1” reading test in an initial state of each cell corresponding to one bit is carried out. Next, “0” writing of fixed pattern data of each cell corresponding to one bit is performed on the FC test of Step 440 b. Finally, a “0” reading test on fixed pattern data of each cell corresponding to one bit is performed on the FC test of Step 440 c.
  • reference cells of more than at least one exist in a selection WL 112 , and a plurality of normal cells are respectively connected thereto in association with one another.
  • any one of the normal cells and its corresponding reference cell are compared and the “1” reading test is conducted.
  • “0” is written into any one of the normal cells, and the normal cell with “0” written therein and its corresponding reference cell are compared, whereby the “0” reading test is executed. This is represented as the “0” reading test of the cell corresponding to one bit being carried out.
  • a decision as to whether the reference cell is good or bad is made by conducting at least one function test, based on the function test on each normal cell.
  • the FC test of Step 450 is carried out.
  • the “1” reading test in the initial state is performed on all remaining normal cells other than on the FC test of Step 440 .
  • the “0” writing of the fixed pattern data is performed on all remaining normal cells other than on the FC test of Step 440 .
  • the “0” and “1” reading test of the fixed pattern data is conducted on all remaining normal cells other than on the FC test of Step 440 .
  • the fixed pattern data are used as the data of “0” and “1” on the FC test of Step 450 .
  • Step 430 the DC test is performed. Described in detail, it is executed after the completion of the six process steps (Steps 440 a, 440 b, 440 c, 450 a, 450 b and 450 c ) contained in the FC test of Step 420 .
  • the time taken from the supply of power to the start of the “0” reading test of the fixed pattern data of the one-bit cell at Step 440 c can be shortened, and the defect of the reference bit line can be screened.
  • FIG. 5 shows a fourth flowchart 500 for inspecting the packaged OTP 100 according to the second preferred embodiment of the invention of the present application.
  • the inspection of the OTP 100 by the fourth flowchart 500 indicates where the packaged OTP 100 is tested using an inspecting board.
  • a contact test of Step 510 is of a test similar to the contact test of Step 410 of FIG. 4 . Described in detail, there is a difference in that an object to be inspected or examined is of the wafer level OTP 100 at Step 410 of FIG. 4 , and the object is of the packaged OTP 100 at Step 510 of FIG. 5 .
  • the contact test is made as to whether an IC socket mounted to the inspecting board connected (mounted) to its corresponding inspection terminal of the LSI tester, and a terminal of the OTP 100 (packaged IC) set to the IC socket of the inspecting board mounted to its corresponding mounting portion of the LSI tester are in contact with each other.
  • FC test of Step 520 and the FC test of Step 420 of FIG. 4 are basically identical to each other. Upon inspection of the packaged OTP 100 , however, the FC test of Step 520 consists of an FC test of Step 540 and an FC test of Step 550 .
  • the FC test of Step 540 comprises Steps 540 a and 540 b.
  • Step 540 a “0” of each cell corresponding to one bit in user data is written, and whether a reference cell is good or bad is determined by a “0” reading test of each cell corresponding to one bit at Step 540 b.
  • the FC test of Step 550 comprises Steps 550 a and 550 b.
  • Step 550 a “0” writing of remaining cells in the user data is performed. Described in detail, “0” writing of all data in user data other than those written at Step 540 a is performed on all remaining normal cells other than those subjected to the end of the test.
  • Step 550 b it is determined by a “0” and “1” reading test whether the user data written at Step 550 a is proper or correct.
  • the FC-test process step at Step 540 b is performed on all reference cells on the FC test of Step 540 .
  • a DC test of Step 530 is of a DC test similar to Step 430 of FIG. 4 .
  • a decision made as to whether the operation of each reference cell is good or not, by performing at least one function test, based on the function test, is performed preferentially.
  • the time taken from the supply of power to the start of the “0” reading test of each cell corresponding to one bit at Step 540 b is shortened, and the defect of the reference bit line can be screened.
  • the defect of the reference bit line 116 b due to the breaking or high resistance of the gate 126 g of the reference column switch transistor 126 cannot be detected on the reading test.
  • This defect can be detected on the “0” reading test (“0” reading test of each cell corresponding to one bit at Steps 440 c and 540 b ).
  • the DC tests of Steps 430 and 530 are performed after the FC tests of Steps 420 and 520 . Further, in order to avoid the spending of much time, the “0” writing (“0” writing of the cell corresponding to one bit in the user data at Step 540 a ) of the cell corresponding to one bit at Step 440 b is performed, and the “0” reading test of the cell corresponding to one bit at Steps 440 c and 540 b is carried out.
  • reference column switch transistor 126 shown in FIG. 1 is normally held ON without depending on the column address and row address (selection WL 112 ) and becomes defective even though any address is selected.
  • the “1” reading test of each cell corresponding to one bit at Step 440 a is first performed on the memory cell array 110 , and the “0” writing of each cell corresponding to one bit at Step 440 b and the “0” reading test of each cell corresponding to one bit at Step 440 c are performed on the memory cell array 110 , thereby making it possible to significantly shorten the time taken from the supply of power to the start of the “0” reading test of the cell corresponding to one bit at Step 440 c.
  • the “0” writing of each cell corresponding to one bit in the user data at Step 540 a is first performed on the memory cell array 110 , and the “0” reading test of each cell corresponding to one bit at Step 540 b is performed thereon, thereby making it possible to significantly shorten the time taken from the supply of power to the start of the “0” reading test of each cell corresponding to one bit at Step 540 b.
  • the defect of the reference bit line 116 b due to the breaking or high resistance of the gate 126 g of the reference column switch transistor 126 corresponding to the normally ON transistor can be screened.

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
US12/196,420 2007-09-28 2008-08-22 Semiconductor Testing Apparatus and Method Abandoned US20090089633A1 (en)

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WO2019041663A1 (zh) * 2017-08-29 2019-03-07 深圳市江波龙电子有限公司 Die测试装置及方法

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US9188562B2 (en) * 2012-05-31 2015-11-17 Fms Technologies, Llc Silver testing apparatus
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