WO2019041663A1 - Die测试装置及方法 - Google Patents

Die测试装置及方法 Download PDF

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Publication number
WO2019041663A1
WO2019041663A1 PCT/CN2017/117227 CN2017117227W WO2019041663A1 WO 2019041663 A1 WO2019041663 A1 WO 2019041663A1 CN 2017117227 W CN2017117227 W CN 2017117227W WO 2019041663 A1 WO2019041663 A1 WO 2019041663A1
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Prior art keywords
test
die
module
current
tested
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English (en)
French (fr)
Inventor
龙红卫
卢浩
李志雄
肖浩
吴方
胡宏辉
邓恩华
谭康强
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Shenzhen Longsys Electronics Co Ltd
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Shenzhen Longsys Electronics Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2894—Aspects of quality control [QC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns

Definitions

  • the present application belongs to the field of semiconductor device testing, and in particular, to a Die testing device and method.
  • FPGA Field Programmable Gate Array
  • DRAM dynamic random access memory
  • Die refers to the unpackaged integrated circuit chip in the semiconductor industry. That is, bare chips, wafers, etc. Or the original factory tests through its own internal test equipment.
  • the traditional method is to test the FPGA chip as a platform.
  • the test method includes several modules, system modules, FPGA modules, pin card modules and some power modules. These modules form a DIE TEST needle card. Then through the analog and DRAM communication to read and write operations, to achieve the purpose of testing; the existence of FPGA test methods have high cost, low test frequency and other shortcomings, the high cost is mainly reflected in the high cost of FPGA chips suitable for DRAM communication.
  • the purpose of the present application is to provide a Die test apparatus and method, which aim to solve the problem of high cost of the test method existing in the conventional technical solution.
  • a Die test device comprising a pin card module for placing a Die to be tested, a program storage module for storing a test program, a current test module connected to the pin card module, and a test control module, the test control module and the The pin card module, the program storage module and the current test module are connected; the test control module receives the test switch command to perform current test and function test on the test Die and upload the test result, wherein:
  • the current test includes: controlling the current test module to supply a voltage to the Die to be tested while detecting an operating current of the Die to be tested;
  • the function test comprises: performing a write-reading procedure on the test Die according to the test program of the program storage module, comparing whether the read and write programs are consistent and obtaining a comparison result.
  • a Die test method including:
  • the current test includes: providing a voltage to the Die to be tested while detecting an operating current of the Die to be tested;
  • the function test comprises: performing a write-reading procedure on the test Die according to the test program of the program storage module, comparing whether the read and write programs are consistent and obtaining a comparison result.
  • an embodiment of the present application provides an electronic device, where the electronic device includes:
  • At least one processor and,
  • the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method described above.
  • embodiments of the present application provide a non-transitory computer readable storage medium storing computer-executable instructions that, when executed by an electronic device, cause the electronic The device performs the above method.
  • the above Die test device and method can set the test control module, read the pre-stored test program to complete the function test for Die, and can also control the current test module to perform current test on the Die load voltage, by setting a low-cost independent module to the package before the package. The wafers are tested to select the defective products for maximum efficiency.
  • FIG. 1 is a schematic structural diagram of a Die test apparatus according to a preferred embodiment of the present application.
  • FIG. 2 is a schematic circuit diagram of an example of a master mold in the current test module shown in FIG. 1;
  • FIG. 3 is a schematic circuit diagram of an example of a first voltage output unit in the current test module shown in FIG. 1;
  • FIG. 4 is a schematic circuit diagram of an example of a second voltage output unit in the current test module shown in FIG. 1;
  • FIG. 5 is a schematic circuit diagram of an example of a level conversion unit in the current test module shown in FIG. 1;
  • FIG. 6 is a schematic circuit diagram of an example of a sampling unit in the current testing module shown in FIG. 1;
  • FIG. 7 is a specific flowchart of a Die test method according to a preferred embodiment of the present application.
  • FIG. 8 is a schematic diagram showing the hardware structure of an electronic device of the Die test method provided by the embodiment of the present application.
  • the Die testing device provided by the preferred embodiment of the present application includes a pin card module 101 for placing a Die to be tested, a program storage module 102 for storing a test program, a current test module 103 connected to the pin card module 101, and a test control module 104.
  • the test control module 104 is connected to the pin card module 101, the program storage module 102, and the current test module 103.
  • the test control module 104 receives the test switch command to perform current test and function test on the test Die and uploads the test result, wherein: the current test includes: The control current test module 103 provides a voltage to the Die to be tested and simultaneously detects the operating current of the Die to be tested; the functional test includes: performing a write program for the test Die according to the test program of the program storage module, comparing whether the read and write programs are consistent and compare results. Further, the serial port module 105 is further configured to communicate with the host computer 200 (such as a personal computer) to upload test results.
  • the host computer 200 such as a personal computer
  • the needle card module 101 has a needle card holder, and the Die is placed on the needle of the needle card by a machine/manual. And the Pad on the Die and the needle on the needle end are in one-to-one correspondence, and the tip of the needle holder is in contact with the Die.
  • Die makes part of the system through contact with the needle card, and then performs handshake communication. When the test is over, the machine then removes the tested Die and sorts it.
  • the program storage module 102 includes an EMMC (Embedded Multi Media Card) or a separate memory card slot for mounting a removable memory card.
  • the platform chip of the test control module 104 is a low cost MTK chip.
  • the current test module 103 includes a main controller (see FIG. 2), a first voltage output unit that supplies 1.8V (see FIG. 3), a second output unit that supplies 1.2V (see FIG. 4), and is used for level shifting.
  • the level shifting unit see Figure 5) and the sampling unit that samples the Die operating current (see Figure 6).
  • Read and write current and standby current test The standby current has a very important impact on the standby time of the whole machine.
  • the size of the read and write current also plays an important role in the power consumption of the whole machine during use.
  • Test the current level of Die before packaging can more effectively distinguish the product usage level, supply power to the DRAM Die by applying 1.2V voltage and 1.8V voltage through the external power supply of the current test module 103, and then separately use the software command to the DRAM Die.
  • the currents in the read, write, and standby states are tested. In the process of these states, the magnitude of the current is detected, including the data written to the DRAM Die, the data read, and the current during standby. Then, the tested current value is fed back to the upper computer 200 through the serial port module 105.
  • this Die test device runs at a frequency of 200 MHz with a long signal line, and in order to save time, the program is simplified as much as possible.
  • the program is simplified as much as possible.
  • strict control impedance, line width and line spacing are used to reduce the influence of signal attenuation, thereby achieving high-speed transmission.
  • the Die test device includes a switch control module 106 coupled to the test control module 104 for receiving an external control to send a test switch command to the test control module 104 to control the start and stop and switch test modes.
  • the switch control module 106 includes a plurality of trigger switch buttons; in other embodiments, the switch control module 106 can use the host computer 200 to issue test switch commands through the serial port module 105.
  • the Die test device can perform DIE test and repackage on some low-yield batch products to improve the usage rate, reduce the packaging cost and test cost.
  • the platform-based chip is cheaper and the test frequency can reach 200Mhz.
  • the chip yield is high.
  • a Die test method including:
  • Step S110 pre-storing the test program
  • Step S120 receiving a test switch command to perform current test and function test on the test Die and upload the test result.
  • the current test includes: providing a voltage to the Die to be tested and simultaneously detecting the working current of the Die to be tested;
  • the functional test comprises: performing a writing process on the test Die according to the test program of the program storage module, comparing whether the read and write programs are consistent and obtain Compare the results.
  • the test switch command includes controlling the test start and stop and the test mode switching.
  • the operating current includes writing data to the Die to be tested, reading data, and current during standby. Upload test results to the host computer through the serial port.
  • the signal frequency of reading and writing data in the function test is 200 MHz. Achieve high-speed testing at longer distances.
  • FIG. 8 is a schematic diagram showing the hardware structure of an electronic device according to the Die test method provided by the embodiment of the present application. As shown in FIG. 8, the electronic device 800 includes:
  • processors 81 and a memory 82 are exemplified by a processor 81 in FIG.
  • the processor 81 and the memory 82 can be connected by a bus or other means, as exemplified by a bus connection in FIG.
  • the memory 82 is a non-volatile computer readable storage medium and can be used for storing non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions corresponding to the Die test method in the embodiment of the present application. /module/unit.
  • the processor 81 executes various functional applications and data processing by executing non-volatile software programs, instructions, and modules stored in the memory 82, that is, implementing the above-described method embodiment Die test method.
  • the memory 82 may include a storage program area and an storage data area, wherein the storage program area may store an operating system, an application required for at least one function; the storage data area may store data created according to the use of the Die test method, and the like.
  • memory 82 can include high speed random access memory, and can also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device.
  • memory 82 can optionally include memory remotely located relative to processor 81, which can be connected to the electronic device over a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
  • the one or more modules or units are stored in the memory 82, and when executed by the one or more processors 81, perform the Die test method in any of the above method embodiments.
  • the embodiment of the present application provides a non-transitory computer readable storage medium storing computer-executable instructions that are executed by one or more processors, such as in FIG.
  • a processor 81 can cause the one or more processors to perform the Die test method in any of the above method embodiments.
  • the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, ie may be located A place, or it can be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • the various embodiments can be implemented by means of software plus a general hardware platform, and of course, by hardware.
  • a person skilled in the art can understand that all or part of the process of implementing the above embodiments can be completed by a computer program to instruct related hardware, and the program can be stored in a computer readable storage medium. When executed, the flow of an embodiment of the methods as described above may be included.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (Random Access Memory). RAM) and so on.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

一种Die测试装置，包括用于放置待测试Die的针卡模块（101）、用于存储测试程序的程序储存模块（102）、电流测试模块（103）以及测试控制模块（104），所述测试控制模块（104）接收测试开关命令对待测试Die进行电流测试和功能测试并上传测试结果，通过设置测试控制模块（104），读取预存的测试程序对Die完成功能测试，也可以控制电流测试模块（103）对Die加载电压进行电流测试，通过设置低成本的独立模块对封装前的晶元进行测试，将不良品挑选出来，达到最大的使用效率。

Description

Die测试装置及方法 技术领域
本申请属于半导体器件测试领域，尤其涉及一种Die测试装置及方法。
 背景技术
目前，随着DRAM（Dynamic Random Access Memory，动态随机存取存储器）技术的制程转换越来越快，从30nm、25nm、20nm甚至更小的制程的发展，在每次制程转换过程中都会存在一定的问题，从而出现一些良率偏低的产品，这些良率偏低的产品如果采取直接封装的形式，那较多的不良品也会一起封装出来，当良率低到无法弥补封装产生的费用时，将会产生亏损现象。
目前市场上主要是通过FPGA（Field Programmable Gate Array，现场可编程门阵列）的方式和DRAM进行通信，模拟读写操作，且测试频率一般在50Mhz左右来对DRAM Die进行测试，其中，Die在半导体行业指的是没有经过封装的集成电路芯片，即为裸芯片、晶片等。或者原厂通过自己内部的测试装置进行测试。
传统是以FPGA芯片为平台的测试方法，该测试方法包括几个模块，系统模块、FPGA模块、针卡模块及一些电源模块，通过这些模块组成一个DIE TEST（晶粒测试）针卡。再通过模拟和DRAM通信进行读写操作，从而达到测试的目的；存在FPGA的测试方法存在成本高，测试频率低等缺点，成本高主要体现在适配DRAM通信的FPGA芯片价格昂贵等缺点。
发明内容
本申请的目的在于提供一种Die测试装置及方法，旨在解决传统的技术方案中存在的测试方法存在成本高的问题。
一种Die测试装置，包括用于放置待测试Die的针卡模块、用于存储测试程序的程序储存模块、与所述针卡模块连接电流测试模块以及测试控制模块，所述测试控制模块与所述针卡模块、所述程序储存模块和所述电流测试模块连接；所述测试控制模块接收测试开关命令对待测试Die进行电流测试和功能测试并上传测试结果，其中：
所述电流测试包括：控制所述电流测试模块向待测试Die提供电压同时检测待测试Die的工作电流；
所述功能测试包括：根据所述程序存储模块的测试程序对待测试Die进行写读程序，对比读与写的程序是否一致并得出对比结果。
此外，还提供了一种Die测试方法，包括：
预存储测试程序；
接收测试开关命令对待测试Die进行电流测试和功能测试并上传测试结果，其中：
所述电流测试包括：向待测试Die提供电压同时检测待测试Die的工作电流；
所述功能测试包括：根据所述程序存储模块的测试程序对待测试Die进行写读程序，对比读与写的程序是否一致并得出对比结果。
此外，本申请实施例提供一种电子设备，所述电子设备包括：
至少一个处理器；以及，
与所述至少一个处理器通信连接的存储器；其中，
所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够执行上述方法。
此外，本申请实施例提供一种非易失性计算机可读存储介质，所述计算机可读存储介质存储有计算机可执行指令，当所述计算机可执行指令被电子设备执行时，使所述电子设备执行上述方法。
上述的Die测试装置及方法通过设置测试控制模块，读取预存的测试程序对Die完成功能测试，也可以控制电流测试模块对Die加载电压进行电流测试，通过设置低成本的独立模块对封装前的晶元进行测试，将不良品挑选出来，达到最大的使用效率。
 附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为本申请较佳实施例提供的Die测试装置结构示意图；
图2为图1所示的电流测试模块中主控模器的示例电路原理图；
图3为图1所示的电流测试模块中第一电压输出单元的示例电路原理图；
图4为图1所示的电流测试模块中第二电压输出单元的示例电路原理图；
图5为图1所示的电流测试模块中电平转换单元的示例电路原理图；
图6为图1所示的电流测试模块中采样单元的示例电路原理图；
图7为本申请较佳实施例提供的Die测试方法的具体流程图；
图8是本申请实施例提供的Die测试方法的电子设备的硬件结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
请参阅图1。本申请较佳实施例提供的Die测试装置包括用于放置待测试Die的针卡模块101、用于存储测试程序的程序储存模块102、与针卡模块101连接电流测试模块103以及测试控制模块104，测试控制模块104与针卡模块101、程序储存模块102和电流测试模块103连接；测试控制模块104接收测试开关命令对待测试Die进行电流测试和功能测试并上传测试结果，其中：电流测试包括：控制电流测试模块103向待测试Die提供电压同时检测待测试Die的工作电流；功能测试包括：根据程序存储模块的测试程序对待测试Die进行写读程序，对比读与写的程序是否一致并得出对比结果。进一步地，还包括串口模块105，串口模块105用于与上位机200（如个人计算机）通讯，上传测试结果。
其中，针卡模块101具有针卡座，Die通过机器/人工顶在针卡的针上。且Die上的Pad（焊盘）和针卡端的针一一对应，通过针卡座的针尖和Die接触。测试开始时，Die通过和针卡的接触使之成为系统的一部分，再进行握手通信，当测试结束后，机器再将测试完的Die移开进行分类。程序储存模块102包括EMMC（Embedded Multi Media Card，内嵌式存储器），或设置独立的存储卡槽，用以安装可拔插存储卡。测试控制模块104的平台芯片为低成本的MTK芯片。
电流测试模块103包括主控制器（参阅图2）、提供1.8V电压的第一电压输出单元（参阅图3）、提供1.2V电压的第二输出单元（参阅图4）、用于电平转换的电平转换单元（参阅图5）和对Die工作电流进行采样的采样单元（参阅图6）。
读写电流及待机电流测试：待机电流的大小对整机的待机时间起到非常重要的影响。读写电流大小对整机在使用过程中的耗电量也起到很重要的影响。在封装前测试Die的电流大小，能更有效的区分产品使用等级，通过电流测试模块103外供电源，对DRAM Die加载1.2V电压和1.8V电压进行外部供电，再通过软件指令分别对DRAM Die进行读、写及待机状态的电流进行测试。在这些状态的过程中去检测其电流的大小，具体包括向DRAM Die写数据、读数据及待机时的电流。然后再通过串口模块105将测试出来的电流值反馈到上位机200。
功能测试：为保障Die的正常使用，就需对Die进行功能测试，把坏的Die挑选出来。通过将EMMC中事先烧录好的程序加载到DRAM Die后，对在针卡端的DRAM die进行扫描测试。再通过串口模块105反馈到上位机200进行分类。此功能测试是对DRAM Die内部全部地址进行写和读操作，然后再进行对比写进去的和读出来的是否一致，从而检查内部阵列是否存在信号不好、是否存在坏块等问题。
区别于成品芯片测试，此Die测试装置在信号线较长的情况下跑200MHZ的频率，且为了节省时间，程序尽可能的进行了简化。另外，为了实现在较远距离情况下实现高速测试。当高速信号在远距离传输的时候会产生较大的信号衰减，导致速率降低，因此采用严格控制阻抗、线宽线距，减少信号衰减带来的影响，从而实现高速传输。
在进一步的实施方式中，Die测试装置包括开关控制模块106，开关控制模块106与测试控制模块104连接，用于接收外部控制向测试控制模块104发送控制启停和切换测试模式的测试开关命令。具体地，开关控制模块106包括多个触发开关按键；在其他实施方式中，开关控制模块106可以使用上位机200通过串口模块105发出测试开关命令。
Die测试装置对一些良率较低的批次产品可先进行DIE测试再封装，提高使用率，降低封装成本和测试成本，基于平台的芯片价格较为便宜，且测试频率可达到200Mhz，测试出来的芯片良率较高。
此外，请参阅图7，还公开了一种Die测试方法，包括：
步骤S110，预存储测试程序；
步骤S120，接收测试开关命令对待测试Die进行电流测试和功能测试并上传测试结果。
其中：电流测试包括：向待测试Die提供电压同时检测待测试Die的工作电流；功能测试包括：根据程序存储模块的测试程序对待测试Die进行写读程序，对比读与写的程序是否一致并得出对比结果。
具体地，测试开关命令包括控制测试启停和测试模式切换。
具体地，工作电流包括向待测试Die写数据、读数据及待机时的电流。通过串口上传测试结果至上位机。
具体地，在功能测试中读写数据的信号频率为200MHz。实现在较远距离情况下实现高速测试。
图8是本申请实施例提供的Die测试方法的电子设备的硬件结构示意图，如图8所示，该电子设备800包括：
一个或多个处理器81以及存储器82，图8中以一个处理器81为例。
处理器81和存储器82可以通过总线或者其他方式连接，图8中以通过总线连接为例。
存储器82作为一种非易失性计算机可读存储介质，可用于存储非易失性软件程序、非易失性计算机可执行程序以及模块，如本申请实施例中的Die测试方法对应的程序指令/模块/单元。处理器81通过运行存储在存储器82中的非易失性软件程序、指令以及模块，从而执行各种功能应用以及数据处理，即实现上述方法实施例Die测试方法。
存储器82可以包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需要的应用程序；存储数据区可存储根据Die测试方法的使用所创建的数据等。此外，存储器82可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他非易失性固态存储器件。在一些实施例中，存储器82可选包括相对于处理器81远程设置的存储器，这些远程存储器可以通过网络连接至电子设备。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
所述一个或者多个模块或单元存储在所述存储器82中，当被所述一个或者多个处理器81执行时，执行上述任意方法实施例中的Die测试方法。
上述产品可执行本申请实施例所提供的方法，具备执行方法相应的功能模块和有益效果。未在本实施例中详尽描述的技术细节，可参见本申请实施例所提供的方法。
本申请实施例提供了一种非易失性计算机可读存储介质，所述计算机可读存储介质存储有计算机可执行指令，该计算机可执行指令被一个或多个处理器执行，例如图8中的一个处理器81，可使得上述一个或多个处理器可执行上述任意方法实施例中的Die测试方法。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
通过以上的实施方式的描述，本领域普通技术人员可以清楚地了解到各实施方式可借助软件加通用硬件平台的方式来实现，当然也可以通过硬件。本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory, ROM)或随机存储记忆体(Random Access Memory, RAM)等。
以上仅所述为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (12)

  1. 一种Die测试装置，其特征在于，包括用于放置待测试Die的针卡模块、用于存储测试程序的程序储存模块、与所述针卡模块连接电流测试模块以及测试控制模块，所述测试控制模块与所述针卡模块、所述程序储存模块和所述电流测试模块连接；所述测试控制模块接收测试开关命令对待测试Die进行电流测试和功能测试并上传测试结果，其中：
    所述电流测试包括：控制所述电流测试模块向待测试Die提供电压同时检测待测试Die的工作电流；
    所述功能测试包括：根据所述程序存储模块的测试程序对待测试Die进行写读程序，对比读与写的程序是否一致并得出对比结果。
  2. 如权利要求1所述的Die测试装置，其特征在于，还包括开关控制模块，所述开关控制模块与所述测试控制模块连接，用于接收外部控制向所述测试控制模块发送控制启停和切换测试模式的测试开关命令。
  3. 如权利要求1所述的Die测试装置，其特征在于，所述工作电流包括向待测试Die写数据、读数据及待机时的电流。
  4. 如权利要求1所述的Die测试装置，其特征在于，在所述功能测试中读写数据的信号频率为200MHz。
  5. 如权利要求1所述的Die测试装置，其特征在于，还包括串口模块，所述串口模块用于与上位机通讯，上传所述测试结果。
  6. 一种Die测试方法，其特征在于，包括：
    预存储测试程序；
    接收测试开关命令对待测试Die进行电流测试和功能测试并上传测试结果，其中：
    所述电流测试包括：向待测试Die提供电压同时检测待测试Die的工作电流；
    所述功能测试包括：根据所述程序存储模块的测试程序对待测试Die进行写读程序，对比读与写的程序是否一致并得出对比结果。
  7. 如权利要求6所述的Die测试方法，其特征在于，所述测试开关命令包括控制测试启停和测试模式切换。
  8. 如权利要求1所述的Die测试方法，其特征在于，所述工作电流包括向待测试Die写数据、读数据及待机时的电流。
  9. 如权利要求1所述的Die测试方法，其特征在于，在所述功能测试中读写数据的信号频率为200MHz。
  10. 如权利要求1所述的Die测试方法，其特征在于，通过串口上传所述测试结果至上位机。
  11. 一种电子设备，所述电子设备包括：
    至少一个处理器；以及，
    与所述至少一个处理器通信连接的存储器；其中，
    所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够执行权利要求6至10任一项所述的Die测试方法。
  12. 一种非易失性计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机可执行指令，当所述计算机可执行指令被电子设备执行时，使所述电子设备执行权利要求6至10任一项所述的Die测试方法。
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