US20070069780A1 - Delay cell of voltage controlled delay line using digital and analog control scheme - Google Patents

Delay cell of voltage controlled delay line using digital and analog control scheme Download PDF

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Publication number
US20070069780A1
US20070069780A1 US11/480,668 US48066806A US2007069780A1 US 20070069780 A1 US20070069780 A1 US 20070069780A1 US 48066806 A US48066806 A US 48066806A US 2007069780 A1 US2007069780 A1 US 2007069780A1
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analog
digital
analog control
transistor circuit
recited
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US11/480,668
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Yong-Ju Kim
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SK Hynix Inc
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Hynix Semiconductor Inc
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Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, YONG-JU
Publication of US20070069780A1 publication Critical patent/US20070069780A1/en
Priority to US12/283,810 priority Critical patent/US7696799B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

Definitions

  • the present invention relates to semiconductor design technologies; and, more particularly, to a delay locked loop (DLL) for use in a synchronous dynamic random access memory (SDRAM), which is capable of determining a coarse delay amount by increasing an operating range of a delay cell.
  • DLL delay locked loop
  • SDRAM synchronous dynamic random access memory
  • time taken for passing through a clock buffer inside a chip, among clock skew factors obstructing high-speed data transmission is important to determine major timing parameters of DRAM.
  • An external clock should be accepted through the clock buffer because it is not inputted at CMOS level and also be passed through a clock driver circuit with large driving capacity for supplying an internal clock signal to many internal circuits. Therefore, the internal clock signal has a delay compared to the external clock; and various internal circuits always have a constant delay with respect to the external clock by a control of the internal clock.
  • a clock access time tAC which denotes time taken from receipt of the external clock to output of data, is increased by the delay component, thus causing a burden for designing a system. For the above reason, a high speed operation of DRAM is impossible.
  • Circuits that achieve a high speed operation of memory by removing the delay components include a phase locked loop (PLL) circuit and a DLL circuit.
  • PLL phase locked loop
  • the DLL includes a phase comparator for periodically comparing a phase of an external clock signal with that of an internal clock signal and detecting whether to increase or decrease the phase depending on a phase difference therebetween, a charge pump for generating a constant output voltage level based on a phase increase/decrease signal, and a loop filter for filtering a high frequency component of the output voltage level from the charge pump, like the PLL circuit.
  • the PLL using a voltage controlled oscillator (VCO) is distinguished from the DLL using a voltage controlled delay line (VCDL).
  • VCO voltage controlled oscillator
  • a delay tracking range of DLL is very important in a memory with a wide range of operating frequencies. Namely, because a range of control voltage becomes small in the DLL as an operating voltage is lower, it is very difficult to manufacture a chip with an operating range from hundreds of MHz to dozens of GHz.
  • FIG. 1 is a block diagram for describing a basic operation of a conventional analog control DLL.
  • the conventional analog control DLL includes a phase detector 10 for receiving an input clock signal FREF and a feedback signal FEEDBACK_CLK, which is provided by modeling an output clock signal FOUT in delay factors inside a memory, and detecting a phase difference between the two signals to produce an up detection signal UP or a down detection signal DOWN, a charge pump 20 for taking the up or down detection signals UP or DOWN from the phase detector 10 , and increasing an output current IC in response to the up detection signal UP and decreasing it in response to the down detection signal DOWN, a loop filter 30 for low pass-filtering the increased/decreased output current IC to generate an analog control voltage VCTRL, a voltage controlled delay line (VCDL) 40 for receiving the analog control voltage VCTRL and the input clock signal FREF and delaying the input clock signal FREF by a certain value corresponding to the analog control voltage VCTRL to provide a delayed signal as the output clock signal FOUT, and a delay replica modeling unit 50 for accepting and modeling the output
  • FIG. 2 is a block diagram for describing a configuration of the general VCDL 40 shown in FIG. 1 .
  • the VCDL 40 may be implemented with a plurality of delay cells, 40 A to 40 D, which delays input clock signals IN and INB by a preset delay value and provides delayed signals as output clock signals OUTB and OUT.
  • the input clock signals IN and INB are differential signals of the input clock signal FREF.
  • the output clock signals OUTB and OUT output from the last delay cell 40 D are differential signals of the output clock signal FOUT.
  • FIG. 3 shows a detailed circuit diagram of one of the plurality of delay cells of FIG. 2 .
  • each delay cell includes NMOS transistors 44 and 45 whose gates take the input clock signals IN and INB and sources are coupled to each other, a pair of symmetrical loads 42 and 43 connected between a power supply voltage VDD and each of the NMOS transistors 44 and 45 , and an NMOS transistor 46 connected between the sources of the NMOS transistors 44 and 45 and ground voltage VSS.
  • Each of the symmetrical loads 42 and 43 has a same structure, wherein each load may be composed of two PMOS transistors connected in parallel, one having a structure that its drain and gate are coupled and the other receiving an analog control voltage PCTRL via the gate to control a delay value.
  • inputted to the gates of the NMOS transistors 44 and 45 are the input clock signals IN and INB, which are delayed by a preset value depending on the analog control voltage PCTRL inputted to the symmetrical loads 42 and 43 to provide delayed signals as the output signals OUTB and OUT.
  • the NMOS transistor 46 connected to the VSS can compensate a variation of drain and substrate voltages in response to an analog control voltage NCTRL.
  • the analog control voltages PCTRL and NCTRL are differential signals of the analog control voltage VCTRL shown in FIG. 1 .
  • FIG. 4 depicts a graph for describing characteristics of the nonlinear analog control voltage VCTRL of the delay cell of FIG. 3 .
  • a horizontal axis of the graph shows the analog control voltage VCTRL and a vertical axis thereof denotes a delay time per delay cell. It can be seen that the delay time according to the analog control voltage VCTRL is varied depending on the process variation of the plurality of delay cells of FIG. 3 .
  • the linear analog control voltage VCTRL approximately ranges from 0.7 V to 1 V at operation voltage of 1.5 V.
  • a typical case has a delay range from 60 ps to 32 ps
  • a slow case has a delay range from 99 ps to 44 ps
  • a fast case has a delay range from 40 ps to 23 ps.
  • an object of the present invention to provide a delay cell circuit of VCDL using a digital and analog control scheme for maximizing its operating range through a combination of a digital control and an analog control.
  • an analog/digital control DLL including: a phase detector for receiving an input clock signal and a feedback signal and detecting a phase difference between the two signals to provide an up detection signal or a down detection signal; a charge pump for taking the up detection signal or the down detection signal and generating an adjusted output current based on the signals; a loop filter for low pass-filtering the output current to produce an analog control voltage; a VCDL for receiving the analog control voltage, the input clock signal and a digital code, and delaying the input clock signal based on the analog control voltage and the digital code to generate an output clock signal; a delay replica modeling unit formed by replicas of a delay factor for receiving the output clock signal and producing the feedback signal; and a digital code generator for generating the digital code.
  • the VCDL includes a plurality of delay cells connected in series, and each delay cell includes: a differential input transistor unit for receiving differential input clock signals; an analog control transistor unit whose one terminal is connected to a power supply terminal for adjusting a fine delay amount in response to analog control voltages; and a digital control transistor unit connected between the analog control transistor unit and the differential input transistor unit for adjusting a coarse delay amount in response to a digital code.
  • the delay cell of the VCDL further includes first and second output nodes connected to each drain of transistors included in the differential input transistor unit for generating differential output clock signals, respectively.
  • the analog control transistor unit includes: an analog control load transistor circuit whose one terminal is connected to the power supply terminal, driven in response to a first analog control voltage; and an analog control current source transistor circuit whose one terminal is connected to a ground voltage terminal, driven in response to a second analog control voltage.
  • the digital control transistor unit includes: a digital control load transistor circuit connected between the other terminal of the analog control load transistor circuit and the first and second output nodes, driven in response to the digital code; and a digital control current source transistor circuit connected between the common source of the differential input transistor unit and the analog control current source transistor circuit, driven in response to a complementary value of the digital code.
  • FIG. 1 is a block diagram for describing a basic operation of a conventional analog control DLL
  • FIG. 2 is a block diagram for describing a configuration of the general voltage controlled delay line (VCDL) 40 shown in FIG. 1 ;
  • VCDL general voltage controlled delay line
  • FIG. 3 shows a schematic circuit diagram of one of a plurality of delay cells of FIG. 2 ;
  • FIG. 4 depicts a graph for describing characteristics of the nonlinear analog control voltage of the delay cell of FIG. 3 ;
  • FIG. 5 shows a block diagram for describing a basic operation of an analog/digital control DLL circuit having a digital code generator in accordance with an embodiment of the present invention
  • FIG. 6 exemplifies a schematic circuit diagram of one of delay cells in VCDL in accordance with an embodiment of the present invention.
  • DLL delay locked loop
  • FIG. 5 shows a block diagram for describing a basic operation of an analog/digital control DLL circuit having a digital code generator 600 in accordance with an embodiment of the present invention.
  • the analog/digital control DLL circuit of the present invention includes a phase detector 100 for receiving an input clock signal FREF and a feedback signal FEEDBACK_CLK, which is provided by modeling an output clock signal FOUT in delay factors, and detecting a phase difference therebetween to provide an up detection signal UP or a down detection signal DOWN, a charge pump 200 for taking the up or down detection signals UP or Down from the phase detector 100 , and increasing an output current IC in response to the up detection signal UP and decreasing it in response to the down detection signal DOWN, a loop filter 300 for low pass-filtering the increased/decreased output current IC to produce an analog control voltage VCTRL, a VCDL 400 for receiving the analog control voltage VCTRL, the input clock signal FREF and a digital code, and delaying the input clock signal FREF by a certain value that corresponds to the digital code and the analog control voltage VCTRL to generate a delayed signal as the output clock signal FOUT, a delay replica modeling unit 500 for
  • the phase detector 100 receives the input clock signal FREF and the feedback signal FEEDBACK_CLK, which is derived by modeling the output clock signal Fout in the delay factors, and issues the up detection signal UP if a phase of the input clock signal FREF precedes that of the feedback signal FEEDBACK_CLK and the down detection signal DOWN if the phase of the input clock signal FREF lags that of the feedback signal FEEDBACK_CLK.
  • the charge pump 200 increase and outputs the output current IC; and in response to the down detection signal DOWN, it decrease and outputs the output current IC. Thereafter, the increased/decreased output current IC is delivered from the charge pump 200 to the loop filter 300 that low pass-filters to create the analog control voltage VCTRL.
  • the digital code generator 600 produces the digital code to control an operation of the VCDL 400 .
  • the VCDL 400 which accepts the input clock signal FREF, the analog control voltage VCTRL from the loop filter 300 and the digital code from the digital code generator 600 , delays the the input clock signal FREF by a predetermined value that is based on the digital code and the analog control voltage VCTRL to output a delayed signal as the output clock signal FOUT.
  • the delay replica modeling unit 500 takes and models the clock output signal FOUT in the delay factors to produce the feedback signal FEEDBACK_CLK. In other words, the delay replica modeling unit 500 models the clock path of the input clock signal FREF inside the chip in order to synchronize the data output from the chip with the clock input to the chip.
  • the digital code generator 600 that generates the digital code, in order to have different functions in various modes, it can be implemented by a fuse option that selects a corresponding mode by using metal mask differently, applying wire bonding differently, or cutting fuse at the last step of the process. And also, it may be implemented by a register control that chooses a corresponding mode by changing a value stored therein. Alternatively, it may be implemented with a digital filter. Since the technical implementation of such digital code generator 600 is obvious to those skilled in the art, details thereof will be omitted here.
  • FIG. 6 exemplifies a detailed circuit diagram of one of a plurality of delay cells of the VCDL 400 in accordance with an embodiment of the present invention.
  • the VCDL 400 of the invention also includes a plurality of delay cells 40 a to 40 d coupled in serial, as shown in FIG. 2 .
  • Each of the plurality of delay cells included in the VCDL 400 of the present invention includes a differential input transistor unit 10 a and 10 b for receiving differential input clock signals IN and INB, an analog control transistor unit 20 a and 20 b whose one terminal is connected to power supply terminals VDD and VSS for adjusting a fine delay amount in response to the analog control voltages PCTL and NCTL, and a digital control transistor unit 30 a and 30 b connected between the analog control transistor unit 20 a and 20 b and the differential input transistor unit 10 a and 10 b for adjusting a coarse delay amount in response to the digital code ⁇ 3 : 0 >.
  • it further includes first and second output nodes N 1 and N 2 connected to each drain of the differential input transistor unit 10 a and 10 b to output differential output clock signals OUTB and OUT.
  • the analog control transistor unit 20 a and 20 b includes an analog control load transistor circuit 20 a whose one terminals are connected to the power supply voltage terminal VDD, driven in response to the first analog control voltage PCTL, and an analog control current source transistor circuit 20 b whose one terminals are connected to the ground voltage terminal VSS, driven in response to the second analog control voltage NCTL.
  • the digital control transistor unit 30 a and 30 b includes a digital control load transistor circuit 30 a connected between the other terminal of the analog control load transistor circuit 20 a and the first and second output nodes N 1 and N 2 , driven in response to the digital code ⁇ 3 : 0 >, and a digital control current source transistor circuit 30 b connected between the common source of the differential input transistor unit 10 a and 10 b and the analog control current source transistor circuit 20 b, driven in response to a complementary value of the digital code ⁇ 3 : 0 >.
  • the analog control load transistor circuit 20 a is provided with a plurality of unit symmetrical loads p 1 a to p 1 d , p 2 a to p 2 d, p 3 a to p 3 d, or p 4 a p 4 d having a symmetrical structure with respect to the first and second output nodes N 1 and N 2 .
  • Any one of the unit symmetrical loads, p 1 a to p 1 d is composed of the unit load p 1 a and p 1 b having a pair of transistors with a first transistor p 1 a taking the first analog voltage pctl via its gate and a second transistor p 1 b whose gate and drain are commonly connected.
  • the unit load p 1 a and p 1 b and the unit load p 1 c and p 1 d are symmetrical to each other to form the unit symmetrical load p 1 a to p 1 d.
  • the digital control load transistor circuit 30 a is implemented with a plurality of transistors that corresponds to the number of transistors p 1 a to p 1 d , p 2 a to p 2 d , p 3 a to p 3 d, and p 4 a to p 4 d of the analog control load transistor circuit 20 a and is controlled by the digital code ⁇ 3 : 0 > of bit number, 4 bits, that corresponds to the unit symmetrical load p 1 a to p 1 d .
  • the transistors of the digital control load transistor circuit 30 a, p 5 a to p 5 d , p 6 a to p 6 d , p 7 a to p 7 d , and p 8 a to p 8 d receive the same code ⁇ 3 : 0 > that corresponds to the unit symmetrical loads of the analog control load transistor circuit 20 a via gates.
  • the code ⁇ 0 > corresponding to the unit symmetrical load p 1 a to p 1 d of the analog control load transistor circuit 20 a is applied to the gates of the transistors p 5 a to p 5 d of the digital control load transistor circuit 30 a ; and the code ⁇ 1 > corresponding to the unit symmetrical load p 2 a to p 2 d is inputted to the gates of the transistors p 6 a to p 6 d of the digital control load transistor circuit 30 a.
  • the code ⁇ 2 > corresponding to the unit symmetrical load p 3 a to p 3 d is provided to the gates of the transistors p 7 a to p 7 d of the digital control load transistor circuit 30 a; and the code ⁇ 3 > corresponding to the unit symmetrical load p 4 a to p 4 d is inputted to the gates of the transistors p 8 a to p 8 d of the digital control load transistor circuit 30 a.
  • the analog control current source transistor circuit 20 b is composed of a plurality of transistors, n 1 a , n 2 a , n 3 a and n 4 a, which corresponds to the number (i.e., 4) of the unit symmetrical loads of the analog control load transistor circuit 20 a .
  • the digital control current source transistor circuit 30 b is composed of a plurality of transistors, n 1 b , n 2 b , n 3 b and n 4 b , which correspond to the number of the analog control current source transistor circuit 20 b.
  • a delay time of the delay cell is proportional to Cb/gm.
  • Cb is formed by junction capacitance and routing capacitance of a PMOS transistor and a NMOS transistor of the delay cell, and gate capacitance of a next delay cell.
  • gm is decided based on ⁇ of a PMOS transistor and a voltage level of PCTRL. To adjust the coarse delay amount, it is designed to correspond to the overall process variation by binary-weighting a gate input of a PMOS transistor used at the loads. Further, it is also designed to meet falling time and a swing level by binary-weighting tail current.
  • the coarse delay amount is first decided by adjusting gm and tail current of the PMOS transistor by a selection of the digital code ⁇ 3 : 0 >; and then the required fine delay amount is decided by adjusting the analog control voltages PCTL and NCTL.
  • the differential input clock signals IN and INB inputted to the differential input transistor unit 10 a and 10 b enable the adjustment of the coarse delay amount by the digital control transistor unit 30 a and 30 b that is responsive to the digital code ⁇ 3 : 0 > and also of the fine delay amount by the analog control transistor unit 20 a and 20 b that is responsive to the analog control voltages PCTL and NCTL.
  • the present invention can prevent speed binning by the DLL by securing a wide operating range of the delay cell through both the digital control and the analog control.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Dram (AREA)
US11/480,668 2005-09-28 2006-06-30 Delay cell of voltage controlled delay line using digital and analog control scheme Abandoned US20070069780A1 (en)

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IT202000013627A1 (it) 2020-06-08 2021-12-08 St Microelectronics Srl Un circuito di controllo per un convertitore elettronico, relativo circuito integrato, convertitore elettronico e procedimento
IT202200007685A1 (it) 2022-04-15 2023-10-15 Milano Politecnico Circuito convertitore DC-DC e corrispondente procedimento di funzionamento
KR20240045772A (ko) 2022-09-30 2024-04-08 주식회사 스카이칩스 위상차 제어회로

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CN1941184A (zh) 2007-04-04
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US7696799B2 (en) 2010-04-13
TWI323567B (en) 2010-04-11

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