US20060263235A1 - Solder alloy and a semiconductor device using the solder alloy - Google Patents

Solder alloy and a semiconductor device using the solder alloy Download PDF

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Publication number
US20060263235A1
US20060263235A1 US11/345,516 US34551606A US2006263235A1 US 20060263235 A1 US20060263235 A1 US 20060263235A1 US 34551606 A US34551606 A US 34551606A US 2006263235 A1 US2006263235 A1 US 2006263235A1
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US
United States
Prior art keywords
solder alloy
germanium
antimony
tin
insulative substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/345,516
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English (en)
Inventor
Akira Morozumi
Shin Soyano
Yoshikazu Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Device Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Device Technology Co Ltd filed Critical Fuji Electric Device Technology Co Ltd
Assigned to FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD. reassignment FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TAKAHASHI, YOSHIKAZU, MOROZUMI, AKIRA, SOYANO, SHIN
Publication of US20060263235A1 publication Critical patent/US20060263235A1/en
Priority to US12/213,923 priority Critical patent/US7816249B2/en
Assigned to FUJI ELECTRIC SYSTEMS CO., LTD. reassignment FUJI ELECTRIC SYSTEMS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
Abandoned legal-status Critical Current

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/262—Sn as the principal constituent
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C13/00—Alloys based on tin
    • C22C13/02—Alloys based on tin with antimony or bismuth as the next major constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates to a solder alloy free of lead and a semiconductor device using the solder alloy, and in particular, to a solder alloy of a tin (Sn)-antimony (Sb) system.
  • a solder alloy generally requires sufficient bonding performance and corrosion resistance.
  • a solder alloy is used to join the back surface of a semiconductor chip to a conductor pattern disposed on a principal surface (front surface) of an insulative substrate that is a ceramic substrate having conductor patterns on the surfaces thereof.
  • Such a solder alloy needs high strength against thermal fatigue, because large thermal strain develops in the soldering area.
  • the back surface of the semiconductor chip joins to the conductor pattern on the surface of the insulative substrate in a face-bonding way, and thermal expansion coefficients are different in a semiconductor chip and in a conductor pattern.
  • the semiconductor chip generates heat in a conducting period. Therefore, the soldering portion suffers from large thermal strain.
  • the conductor pattern disposed on the other principal surface (a back surface) of an insulative substrate is joined to a heat sink plate made of a metal. Since the soldering area is very wide, the solder alloy used for this joint must exhibit excellent wettability. Further, in the joining area between the heat sink plate and the conductor pattern on the back surface of the insulative substrate, large thermal strain develops caused by the difference in thermal expansion coefficients of the insulative substrate (a ceramic substrate) and the heat sink plate.
  • the generated strain in the soldering area is larger than the strain that develops in the joint between the semiconductor chip and the conductor pattern on the front surface of the insulative substrate as mentioned earlier.
  • solder alloy that does not contain lead (Pb) is in demand in view of environmental considerations.
  • One of such known solder alloys is a tin (Sn)-antimony (Sb) alloy.
  • a known solder alloy (see Japanese Unexamined Patent Application Publication No. H11-58066, for example) contains tin (Sn) as a principal component, and antimony (Sb) not more than 3.0 wt %, silver (Ag) not more than 3.5 wt %, germanium (Ge) not more than 0.1 wt %, and further, copper not more than 1.0 wt % or nickel not more than 1.0 wt % or the both elements.
  • Another known solder alloy contains germanium (Ge) in the range of 0.01 to 10 wt %, antimony in the range of 5 to 30 wt %, and tin (Sn) in the range of 65 to 90 wt %.
  • a tin (Sn)-antimony (Sb) alloy having a peritectic point at 8.5 wt % of antimony (Sb) and a temperature of 245° C., is generally used with a composition containing antimony (Sb) within 8 wt %. Melting of the tin (Sn)-antimony (Sb) alloy occurs at temperatures between 232° C., the melting point of tin (Sn), and 245° C., the peritectic point. The liquid-solid coexistence region is narrow, the heat resistance is favorable, and mechanically superior performances can be obtained by increasing the antimony (Sb) content. A large content of antimony (Sb), however, results in a problem of low wettability upon soldering the alloy. Oxidation of a solder component such as tin (Sn) involves another problem of deteriorated bonding performance.
  • a solder alloy according to one embodiment of the invention contains antimony in a range of 3 wt % to 5 wt %, a trace amount of germanium, and a balance of tin.
  • a solder alloy according to another aspect of the invention is the solder alloy according to the first embodiment of the invention, wherein the content of the germanium is not more than 0.2 wt %.
  • a semiconductor device using a solder alloy comprises an insulative substrate having conductor patterns on both surfaces thereof, a semiconductor chip joined to a conductor pattern on a front surface of the insulative substrate, and a heat sink plate joined to a conductor pattern on a back surface of the insulative substrate.
  • the conductor pattern on the back surface of the insulative substrate and the heat sink plate are soldered with a solder alloy that contains antimony in a range of 3 wt % to 5 wt %, a trace amount of germanium, and the balance of tin.
  • a back surface of the semiconductor chip and the conductor pattern on the front surface of the insulative substrate are soldered with a solder alloy that contains antimony in a range of 3 wt % to 5 wt %, a trace amount of germanium, and the balance of tin.
  • electrodes disposed on the surfaces of the semiconductor chip and conductors for wiring are soldered with a solder alloy that contains antimony in, a range of 3 wt % to 5 wt %, a trace amount of germanium, and the balance of tin.
  • the content of the germanium in the solder alloy is not more than 0.2 wt %.
  • the insulative substrate is a ceramic substrate substantially composed of alumina, aluminum nitride, or silicon nitride and having copper patterns on both surfaces of the substrate, and the heat sink plate is made of copper.
  • the thermal fatigue life is very short if the content of antimony (Sb) is less than 3 wt %, the amount of additive antimony (Sb) is preferably at least 3 wt %. If the content of antimony (Sb) is more than 5 wt %, wettability of the solder deteriorates. Accordingly, the amount of additive antimony (Sb) is preferably not more than 5 wt %.
  • an amount of additive germanium (Ge) is preferably at least 0.01 wt % in order to achieve sufficient effect to suppress oxidation.
  • the germanium content of more than 0.2 wt % on the other hand, the oxide film with the germanium (Ge) grows too thick, which adversely affects the bonding performance. Accordingly, the amount of additive germanium is appropriately not more than 0.2 wt %. Therefore, the germanium added in an amount in the range of 0.01 to 0.2 wt % provides satisfactory bonding performance as well as excellent thermal fatigue characteristic.
  • a tin (Sn)-antimony (Sb) solder alloy is obtained that exhibits excellent wettability and satisfactory bonding performance.
  • a semiconductor device is obtained using a solder alloy of tin (Sn)-antimony (Sb) system that exhibits excellent wettability and satisfactory bonding performance.
  • the FIGURE is a sectional view of an example of a semiconductor device using a solder alloy according to an embodiment of the present invention.
  • a solder alloy is prepared by melting the raw materials of tin (Sn), antimony (Sb), and germanium (Ge) in an electric furnace. Purity of each raw material is 99.99% or more. Compositions of the materials are antimony 3 to 5 wt %, germanium 0.01 to 0.2 wt %, and the balance of tin (Sn), a main component.
  • an insulative substrate 10 comprises a ceramic substrate 1 and conductor patterns 2 and 3 joined on both surfaces of the, ceramic substrate.
  • the ceramic substrate 1 is substantially composed of alumina, aluminum nitride, or silicon nitride.
  • the conductor pattern 2 formed on the front surface of the ceramic substrate 1 is a metallic conductor pattern composing an electric circuit.
  • On the back surface of the ceramic substrate 1 is provided a metallic conductor pattern 3 .
  • the conductor patterns 2 and 3 are preferably formed of copper, which is inexpensive and exhibits high thermal conductivity.
  • back surface electrodes of metallic films are provided on the back surface of the semiconductor chip 4 .
  • the back surface electrodes are joined to the conductor pattern 2 on the front surface of the insulative substrate 10 with a solder alloy 5 having a composition as described previously.
  • front surface electrodes of metallic films are provided on the front surface of the semiconductor chip 4 .
  • the front surface electrodes are joined to the wiring conductor 6 with a solder alloy 7 having a composition as described previously.
  • the conductor pattern 3 on the back surface of the insulative substrate 10 is joined to the metallic heat sink plate 8 with a solder alloy 9 having a composition as described previously.
  • the heat sink plate 8 is a heat conductor to external cooling fins of the semiconductor package not shown in the FIGURE.
  • the heat sink plate 8 is preferably made of copper, which is inexpensive and exhibits high thermal conductivity.
  • solder alloy with the above-described composition for joining the conductor pattern 3 and the heat sink plate 8 , excellent cooling characteristics and satisfactory bonding performance can be achieved employing copper with low cost and high thermal conductivity.
  • a solder material with a different composition from that of the solder alloy 5 , 7 , 9 may be used for joining the front surface electrodes of the semiconductor chip 4 and the wiring conductor 6 , and for joining the back surface electrodes of the semiconductor chip 4 and the conductor pattern 2 on the insulative substrate 10 .
  • Solder alloys of a tin (Sn)-antimony (Sb) system were prepared in the compositions of antimony (Sb): 5.0 wt %, germanium (Ge): four steps of contents in the range of 0.01 to 0.2 wt %, and the balance of tin (Sn).
  • Germanium content was 0.01 wt % in Example 1, 0.05 wt % in Example 2, 0.1 wt % in Example 3, and 0.2 wt % in Example 4.
  • Solder alloys of tin (Sn)-antimony (Sb) system were prepared in the compositions of antimony (Sb): 3.0 wt %, germanium (Ge): four steps of contents in the range of 0.01 to 0.2 wt %, and the balance of tin (Sn).
  • Germanium content was 0.01 wt % in Example 5, 0.05 wt % in Example 6, 0.1 wt % in Example 7, and 0.2 wt % in Example 8.
  • Solder alloys not containing germanium (Ge) were prepared for comparison.
  • the content of antimony (Sb) was 6.0 wt % in Comparative Example 1, 5.0 wt % in Comparative Example 2, 3.0 wt % in Comparative Example 3, 2.0 wt % in Comparative Example 4; the remainder was tin (Sn) in every Comparative Example.
  • soldering flux RMA type
  • the rate of wetted area and the wetting angle were measured and the generation of an oxide film on the melt was observed.
  • the thermal fatigue life was also evaluated on each solder alloy.
  • a conjugated body a combination of the heat sink plate 8 and the insulative substrate 10 having the conductor pattern 3 joined together with the solder alloy 9 as illustrated in the FIGURE
  • Table 1 shows the following. With the increase of the added antimony (Sb), the thermal fatigue performance improves, but the increase beyond 5.0 wt % does not provide further improvement of the thermal fatigue performance. On the other hand, antimony (Sb) content less than 3.0 wt % significantly worsens the thermal fatigue performance. Addition of 0.01 to 0.2 wt % of germanium remarkably suppresses generation of an oxide film on the molten solder and at the same time improves wettability.
  • germanium (Ge) is effective for both flow soldering and reflow soldering. Further, the effect of germanium is valid in both cream solder and sheet solder.
  • the addition of germanium (Ge) in the amount more than 0.01 wt % made no significant difference in the wettability and the oxide film formation as increased from the germanium content of 0.01 wt %.
  • the added germanium (Ge), suppressing oxidation of tin (Sn), is effective not only in the process of soldering but also in the process of preparing a solder alloy, to provide a solder alloy with essentially no oxidation film, and of high quality.
  • each particle of the powder is desired to have a spherical shape.
  • the powder is necessarily manufactured under a condition in which only the surface tension works, which requires suppressing the surface oxidation to the minimum possible degree. Therefore, germanium (Ge) is beneficially added to suppress the surface oxidation.
  • the rate of oxidation of germanium (Ge) is stable and only a small amount of the additive holds the effect.
  • germanium (Ge) in a tin (Sn)-antimony (Sb) alloy provides a solder alloy exhibiting excellent thermal fatigue performance, a solder alloy exhibiting heat resistance, a solder alloy exhibiting high wettability, and a solder alloy exhibiting satisfactory bonding performance. Because the alloy is free of lead (Pb), a solder alloy that does not cause environmental pollution is provided.
  • solder alloy and a semiconductor device using the solder alloy according to the invention are beneficially applied to a variety of apparatuses having soldered parts, and are particularly suited to semiconductor devices for power conversion used in a power conversion apparatus installed in electric vehicles.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
US11/345,516 2005-05-20 2006-02-02 Solder alloy and a semiconductor device using the solder alloy Abandoned US20060263235A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/213,923 US7816249B2 (en) 2005-05-20 2008-06-26 Method for producing a semiconductor device using a solder alloy

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005148730A JP4635715B2 (ja) 2005-05-20 2005-05-20 はんだ合金およびそれを用いた半導体装置
JP2005-148730 2005-05-20

Related Child Applications (1)

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US12/213,923 Continuation-In-Part US7816249B2 (en) 2005-05-20 2008-06-26 Method for producing a semiconductor device using a solder alloy

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US20060263235A1 true US20060263235A1 (en) 2006-11-23

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US (1) US20060263235A1 (de)
JP (1) JP4635715B2 (de)
CN (3) CN1864909B (de)
DE (1) DE102006005271B4 (de)
GB (1) GB2426251B (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090289344A1 (en) * 2008-05-23 2009-11-26 Fuji Electric Device Technology Co., Ltd. Semiconductor device
US20100328247A1 (en) * 2008-02-22 2010-12-30 Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.) Touch panel sensor
US20140144019A1 (en) * 2011-08-29 2014-05-29 Asia Vital Components Co., Ltd. Heat Dissipation Device and Method of Manufacturing Same

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008221330A (ja) * 2007-03-16 2008-09-25 Fuji Electric Holdings Co Ltd はんだ合金
CN102717201B (zh) * 2012-07-04 2015-04-22 深圳市斯特纳新材料有限公司 具有耐腐蚀的高强度高温焊料
JP6713106B2 (ja) * 2014-02-24 2020-06-24 株式会社弘輝 鉛フリーはんだ合金、はんだ材料及び接合構造体
CN108428682B (zh) * 2018-04-13 2020-08-18 江西江铃集团新能源汽车有限公司 一种功率模组及其制备方法

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US6179935B1 (en) * 1997-04-16 2001-01-30 Fuji Electric Co., Ltd. Solder alloys
US6187114B1 (en) * 1996-10-17 2001-02-13 Matsushita Electric Industrial Co. Ltd. Solder material and electronic part using the same
US6319461B1 (en) * 1999-06-11 2001-11-20 Nippon Sheet Glass Co., Ltd. Lead-free solder alloy
US20030230361A1 (en) * 2002-06-17 2003-12-18 Kabushiki Kaisha Toshiba Lead-free solder alloy and lead-free solder paste using the same

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JPS62230493A (ja) * 1986-03-31 1987-10-09 Taruchin Kk はんだ合金
JP3269745B2 (ja) * 1995-01-17 2002-04-02 株式会社日立製作所 モジュール型半導体装置
JPH09330941A (ja) * 1996-06-13 1997-12-22 Toshiba Corp 高熱伝導ペースト半田および半導体デバイス
US6033488A (en) * 1996-11-05 2000-03-07 Samsung Electronics Co., Ltd. Solder alloy
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JP3353662B2 (ja) * 1997-08-07 2002-12-03 富士電機株式会社 はんだ合金
JP2002232022A (ja) * 2001-01-31 2002-08-16 Aisin Seiki Co Ltd 熱電モジュール及びその製造方法
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US20030021718A1 (en) * 2001-06-28 2003-01-30 Osamu Munekata Lead-free solder alloy
JP2003094194A (ja) * 2001-07-16 2003-04-02 Uchihashi Estec Co Ltd はんだ材及び電子部品における部材の固定方法
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Publication number Priority date Publication date Assignee Title
US6187114B1 (en) * 1996-10-17 2001-02-13 Matsushita Electric Industrial Co. Ltd. Solder material and electronic part using the same
US6179935B1 (en) * 1997-04-16 2001-01-30 Fuji Electric Co., Ltd. Solder alloys
US6319461B1 (en) * 1999-06-11 2001-11-20 Nippon Sheet Glass Co., Ltd. Lead-free solder alloy
US20030230361A1 (en) * 2002-06-17 2003-12-18 Kabushiki Kaisha Toshiba Lead-free solder alloy and lead-free solder paste using the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100328247A1 (en) * 2008-02-22 2010-12-30 Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.) Touch panel sensor
US20090289344A1 (en) * 2008-05-23 2009-11-26 Fuji Electric Device Technology Co., Ltd. Semiconductor device
US20140144019A1 (en) * 2011-08-29 2014-05-29 Asia Vital Components Co., Ltd. Heat Dissipation Device and Method of Manufacturing Same

Also Published As

Publication number Publication date
DE102006005271B4 (de) 2012-12-06
CN102637662B (zh) 2014-09-24
CN102637662A (zh) 2012-08-15
GB2426251B (en) 2007-10-10
GB0601776D0 (en) 2006-03-08
CN1864909A (zh) 2006-11-22
JP4635715B2 (ja) 2011-02-23
DE102006005271A1 (de) 2006-11-23
CN101905388B (zh) 2012-05-30
JP2006320955A (ja) 2006-11-30
GB2426251A (en) 2006-11-22
CN101905388A (zh) 2010-12-08
CN1864909B (zh) 2012-05-30

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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.;REEL/FRAME:024252/0438

Effective date: 20090930