US20050230750A1 - Cathode substrate and its manufacturing method - Google Patents

Cathode substrate and its manufacturing method Download PDF

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Publication number
US20050230750A1
US20050230750A1 US11/066,562 US6656205A US2005230750A1 US 20050230750 A1 US20050230750 A1 US 20050230750A1 US 6656205 A US6656205 A US 6656205A US 2005230750 A1 US2005230750 A1 US 2005230750A1
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US
United States
Prior art keywords
emitter
insulator layer
hole
layer
electrode layer
Prior art date
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Abandoned
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US11/066,562
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English (en)
Inventor
Haruhisa Nakano
Masaaki Hirakawa
Osamu Miura
Hirohiko Murakami
Kensuke Okasaka
Tomoaki Kojima
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Ulvac Coating Corp
Ulvac Inc
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Individual
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Filing date
Publication date
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Assigned to ULVAC COATING CORPORATION, ULVAC, INC. reassignment ULVAC COATING CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HIRAKAWA, MASAAKI, KOJIMA, TOMOAKI, MIURA, OSAMU, MURAKAMI, HIROHIKO, NAKANO, HARUHISA, OKASAKA, KENSUKE
Publication of US20050230750A1 publication Critical patent/US20050230750A1/en
Priority to US12/538,354 priority Critical patent/US20090325452A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02—Main electrodes
    • H01J1/30—Cold cathodes, e.g. field-emissive cathode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J29/00—Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
    • H01J29/46—Arrangements of electrodes and associated parts for generating or controlling the ray or beam, e.g. electron-optical arrangement
    • H01J29/48—Electron guns
    • H01J29/481—Electron guns using field-emission, photo-emission, or secondary-emission electron source
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J3/00—Details of electron-optical or ion-optical arrangements common to two or more basic types of discharge tubes or lamps
    • H01J3/02—Electron guns
    • H01J3/021—Electron guns using a field emission, photo emission, or secondary emission electron source
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J31/00—Cathode ray tubes; Electron beam tubes
    • H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
    • H01J31/10—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
    • H01J31/12—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
    • H01J31/123—Flat display tubes
    • H01J31/125—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection
    • H01J31/127—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection using large area or array sources, i.e. essentially a source for each pixel group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02—Manufacture of electrodes or electrode systems
    • H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes

Definitions

  • the present invention relates to a cathode substrate which is suitably usable, for example, in a display having an electron emission source, and its manufacturing method.
  • the present invention particularly relates to a cathode substrate suitable for use in a field emission display (FED) and which is formed of a carbon group emitter material such as graphite nanofibers or carbon nanotubes, and its manufacturing method.
  • FED field emission display
  • FED which utilizes an electron emission source formed of a carbon group emitter material such as graphite nanofiber or carbon nanotube, such a material having a lower electron emission voltage and a chemical stability. It is the mainstream that this FED makes use of a field emitter with a triode structure comprising a cathode electrode, a gate electrode and an anode electrode so that the necessary drive voltage to emit electrons can be reduced.
  • a cathode substrate is provided by sequentially forming a cathode electrode layer, insulator layer and gate electrode layer on a substrate to be processed, forming one gate aperture on the gate electrode layer, forming a hole through the gate aperture, said hole having its area of top opening larger than that of the gate aperture in the insulator layer, thereafter providing a catalyst layer at the bottom of the hole, and growing a carbon group emitter material to form an emitter on the catalyst layer.
  • the above prior art raises a problem in that, because only one gate aperture is located on the insulator layer opposite to the emitter, electrons will be drawn and accelerated from the emitter toward the gate electrode when the drive voltage is applied to the emitter to emit electrons. Thus, the emitted electrons will be diffused after passed through the gate aperture. The diffused electrons will deteriorate the efficiency of charge injection to an anode substrate (or electrode) which has been arranged opposite to the cathode substrate to form the field emitter with the triode structure.
  • this invention has an object of providing a cathode substrate which can prevent electrons emitted between each of emitters from being diffused to improve the efficiency of charge injection and which can also less vary the efficiency of charge injection between each of emitters, and its manufacturing method.
  • a cathode substrate comprising: a cathode electrode layer formed on a substrate to be processed; a insulator layer formed on the cathode layer, said insulator layer including an emitter located at the bottom of a hole formed therein; and a gate electrode layer formed on the insulator layer, said gate electrode layer including a gate aperture formed therethrough, said gate aperture consisting of a plurality of openings, the total area of which is smaller than the area of top opening of the hole in said insulator layer, said openings being arranged densely at a position opposite to the emitter and just above the hole of the insulator layer.
  • the openings forming the gate aperture are arranged densely at a position opposite to the emitter and just above the hole of the insulator layer.
  • the efficiency of charge injection to an anode substrate to be disposed opposite to said cathode substrate to form the field emitter with the triode structure is changed by increasing or decreasing at least one of the area of each opening and the number of openings.
  • said emitter is formed of a carbon group emitter material and that the carbon group emitter material is grown on a catalyst layer.
  • a cathode substrate manufacturing method comprises the steps of: forming a cathode electrode layer on a substrate to be processed; forming insulator layer on said cathode electrode layer; forming gate electrode layer on said insulator layer; providing a resist pattern on said gate electrode layer before the resist pattern and the gate electrode layer are etched to form a gate aperture consisting of a plurality of openings; etching said insulator layer through said gate aperture both in the directions of depth and width to form a single hole, the openings of said gate aperture being arranged densely at a position just above said hole; and providing an emitter at the bottom of the hole.
  • said emitter is formed of a carbon group emitter material and that a catalyst layer acting as a catalyst as said carbon group emitter material is being grown is previously formed underside of said insulator layer.
  • said emitter is formed of a carbon group emitter material and that after the insulator layer has been etched, the catalyst layer acting as a catalyst as the carbon group emitter material is being grown is formed through the lift-off method and that a carbon group emitter is grown at the bottom of the hole through CVD method or a carbon group emitter is applied on the bottom of the hole through printing method.
  • FIG. 1 is a perspective view schematically illustrating a cathode substrate for FED according to the present invention.
  • FIGS. 2A through 2E illustrate a procedure for manufacturing a cathode substrate for FED according to the present invention.
  • FIG. 3 is a view illustrating a cathode substrate for FED according to the prior art.
  • FIGS. 4A and 4B show SEM illustrating a cathode substrate for FED manufactured according to the present invention.
  • FIGS. 5A and 5B show enlarged photographs which illustrate one pixel projected onto anode fluorescent substrates using cathode substrates in the Example 1 and comparative example 1.
  • FIGS. 6A through 6F illustrate a procedure for manufacturing another cathode substrate for FED according to the present invention.
  • the cathode substrate 1 comprises a glass substrate 11 which is a substrate to be processed.
  • a cathode electrode layer (bus) 12 for example, of chromium is formed on the surface of the glass substrate 11 with a predetermined film thickness.
  • the cathode electrode layer 12 may be formed, for example, by DC sputtering while heating the glass substrate 11 to a predetermined temperature (e.g., 200 degrees Celsius).
  • a catalyst layer 13 for example, of a material selected from a group consisting of Fe, Co and alloys containing at least one of these metals is formed on the surface of the cathode electrode layer 12 with a predetermined film thickness (a range of 1-50 nm) and is then processed line-like.
  • the catalyst layer 13 may be formed, for example, by DC sputtering.
  • An emitter E is formed on the surface of this catalyst layer 13 by growing a carbon group emitter material C such as graphite nanofiber or carbon nanotube through any known process after a hole has been formed through an insulator layer as described later.
  • the insulator layer 14 for example, of SiO 2 is formed on the surface of the catalyst layer 13 with a predetermined film thickness (e.g., 3 ⁇ m).
  • the insulator layer 14 may be formed, for example, by RF sputtering while heating the glass substrate 11 to a predetermined temperature (e.g., 300 degrees Celsius) for preventing damage due to stress in the formed insulator layer 14 .
  • This insulator layer 14 may be formed through several steps for preventing the formation of pinholes due to dust on the glass substrate 11 in the RF sputtering.
  • the insulator layer 14 may be formed by any of EB and in-gas vapor depositions other than the aforementioned RF sputtering.
  • the insulator layer 14 also includes a hole 14 a formed therethrough so that the catalyst layer 13 used to grow the carbon group emitter materials C will be exposed.
  • the fluoric acid may be used as an etchant.
  • the hydrofluoric acid is used to etch the insulator layer 14 to form the hole 14 a having a predetermined section shape (e.g., circular).
  • the insulator layer 14 is etched through each opening both in the directions of depth and width to form a single hole 14 a below the gate electrode layer.
  • These openings are arranged densely at a position opposite to the emitter E and just above the hole 14 a of the insulator layer 14 .
  • the crosswise etching may be progressed if the over-etching time is controlled.
  • the shape and/or size of the hole 14 a in the insulator layer 14 may be selected depending on the number and/or layout of openings in the gate aperture.
  • the gate electrode layer 15 for example, of chromium is formed on the insulator layer 14 with a predetermined film thickness (e.g., 300 nm).
  • the gate electrode layer 15 may be formed by DC sputtering while heating the substrate as in the cathode electrode layer 12 .
  • the gate electrode layer 15 includes a gate aperture 16 formed therethrough.
  • the gate electrode layer 15 may be formed by any one of EB and in-gas vapor depositions other than the aforementioned RF sputtering.
  • the gate aperture 16 consists of a plurality of openings 16 a , the total area of which is smaller than the area of top opening in the hole 14 a on the insulator layer 14 .
  • These openings 16 a are arranged densely and preferably densely and uniformly at a position opposite to the emitter E and just above the hole 14 a of the insulator layer 14 .
  • Each of the openings 16 a is of substantially square or circular configuration, the length of one side or the diameter being between 1 ⁇ m and 3 ⁇ m.
  • the spacing between the openings 16 a adjacent to each other is ranged between 0.5 ⁇ m and 2 ⁇ m and the number of openings 16 a is selected to be between 2 and 50. In this case, it is preferred that the total area of the openings 16 a is between 50% and 90% of the area of top opening of the hole 14 a in the insulator layer 14 .
  • each of the openings 16 a may be formed by transferring a predetermined resist pattern on the gate electrode layer 15 through the photolithography method and then etching it in wet or dry.
  • the electrons will be drawn and accelerated just above the emitter E when the drive voltage is applied to the emitter to emit the electrons.
  • the emitted electrons will not be diffused after passed through the openings 16 a of the gate aperture 16 in the gate electrode layer 15 .
  • the emission of electrons will be less influenced by the minute variation of emitters.
  • the efficiency of charge injection to the anode substrate can be changed by increasing or decreasing either of the total area or number of openings 16 a.
  • the present invention will not be limited to such a structure, but can provide the cathode substrate 1 which can broadly be utilized as a general electron emission source.
  • FIGS. 2A through 2E schematically illustrate various processes in a method of the present invention which can be carried out to make a cathode substrate 1 for FED according to the present invention.
  • a cathode electrode layer 12 of chromium was formed over a glass substrate 11 by DC sputtering while heating a glass substrate 11 to 200 degrees Celsius, the cathode electrode layer 12 having its film thickness of 100 nm.
  • a catalyst layer 13 to be used for growing a carbon group emitter material of Fe alloy was then formed over the cathode electrode layer 12 , the catalyst layer 13 having its film thickness of 25 nm.
  • An insulator layer 14 of SiO2 was then formed over the catalyst layer 13 by RF sputtering while heating the substrate to 375 degrees Celsius, the insulator layer 14 having its film thickness of 3 ⁇ m.
  • a gate electrode layer 15 of chromium was formed over the insulator layer 14 by DC sputtering while heating the glass substrate 11 to 200 degrees Celsius, as in the cathode electrode layer 12 .
  • the gate electrode layer 15 had its film thickness of 300 nm.
  • a resist pattern 17 was then formed over the gate electrode layer 15 by photolithography method, the resist pattern 17 having its thickness of about 1 ⁇ m.
  • a gate aperture 16 was then formed through the resist pattern 17 by etching.
  • the resist material was one that was generally used in electron beam exposure apparatus.
  • the gate aperture 16 included nineteen square-shaped openings 16 a which were formed through the resist pattern 17 in a grid-like pattern by wet etching using a cerium sulfate ammonium solution.
  • each of the openings 16 a was originally formed to have the length of each side equal to about 1 ⁇ m with the spacing between the adjacent openings 16 a being equal to about 1 ⁇ m.
  • the resist pattern 17 was over-etched to provide each opening 16 a having the length of one side equal to about 1.2 ⁇ m and to provide the spacing between the adjacent openings 16 a equal to 0.8 ⁇ m.
  • the insulator layer 14 was wet-etched to form a single hole 14 a of substantially circular configuration using fluoric acid as an etchant, so that the openings 16 a were arranged densely at a position just above the hole 14 a of the insulator layer 14 . Thereafter, the resist pattern 17 was removed. At this time, the diameter of the top opening in the hole 14 a was equal to about 16 ⁇ m. Subsequently, carbon nanotubes C were grown on the catalyst layer 13 through the openings 16 a of the gate aperture 16 to form an emitter E by any suitable known method, as shown in FIG. 2E . Thus, the cathode substrate 1 was provided.
  • a cathode electrode layer 12 , catalyst layer, insulator layer 14 and gate electrode layer 15 were formed on a glass substrate 11 under the same conditions as in the above example 1, as shown in FIG. 3 .
  • a single gate aperture 20 was formed through the gate electrode layer 15 with the diameter thereof being equal to 10 ⁇ m, as in the above example 1.
  • the insulator layer 14 was etched to form a hole 14 a which had the diameter of top opening equal to about 16 ⁇ m.
  • Carbon nanotubes were then grown on the catalyst layer to form an emitter E by any suitable known method. In this way, a cathode substrate 10 was provided.
  • FIGS. 4A and 4B show SEM which illustrate the top face and cross-section of a cathode substrate 1 made according to the above procedure described in connection with Example 1. It is to be understood from these figures that a gate aperture 16 was formed through the insulator layer 14 to have a plurality of openings 16 a with the total area and spacing as described above (see FIG. 4A ). It is also to be understood that carbon nanotubes could be grown through the openings 16 a (see FIG. 4 B).
  • FIGS. 5A and 5B show enlarged photographs which illustrate one pixel projected onto anode fluorescent substances in connection with the structures of the Example 1 and comparative example 1, respectively.
  • FIG. 5A relates to the Example 1, while FIG. 5B shows the comparative example 1. It is understood from this that the diffusion of electrons in the Example 1 could be reduced half of that in the comparative example 1.
  • Example 2 is different from the above example 1 only in that a catalyst layer 13 is formed at the bottom of a hole 14 a by RF sputtering method after an insulator layer 14 has been etched to form the hole 14 a .
  • a catalyst layer 13 is formed at the bottom of a hole 14 a by RF sputtering method after an insulator layer 14 has been etched to form the hole 14 a .
  • FIGS. 6A through 6F an insulator layer 14 and gate electrode layer 15 were sequentially formed on a glass substrate 11 after a cathode electrode layer (bus) 12 has been provided on the glass substrate 11 , in the same manner as in the above example 1 (see FIG. 6A ).
  • a predetermined resist pattern 17 was transferred to the gate electrode layer 15 through photolithography method (see FIG. 6B ), and the resist pattern 17 was then dry-etched to form a gate aperture 16 consisting of a plurality of openings 16 a (see FIG. 6C ).
  • the insulator layer 14 was then wet-etched to form a single hole 14 a (see FIG. 6D ), and a catalyst layer 13 of carbon group emitter material was formed at the bottom of the hole 14 a by RF sputtering method (see FIG. 6E ), as in the above example 1.
  • the carbon system material was grown on the catalyst layer 13 remaining on the bottom of the hole 14 a to form an emitter E(see FIG. 6F ).
  • the catalyst layer could be formed through the openings 16 a of the gate aperture 16 formed on the insulator layer 14 with the pre-selected total area and spacing of the openings 16 a and the carbon nanotubes could be grown on the catalyst layer.
  • the necessary drive voltage to emit electrons could be reduced while at the same time the electronic diffusion could be reduced.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Cold Cathode And The Manufacture (AREA)
US11/066,562 2004-03-01 2005-02-28 Cathode substrate and its manufacturing method Abandoned US20050230750A1 (en)

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JP056624/2004 2004-03-01
JP2004056624A JP4456891B2 (ja) 2004-03-01 2004-03-01 カソード基板及びその作製方法

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010000895B4 (de) * 2010-01-14 2018-12-27 Robert Bosch Gmbh Verfahren zum Herstellen eines Durchkontaktes eines Halbleiterbauelements mit einem umgebenden ringförmigen Isolationsgraben und entsprechendes Halbleiterbauelement
US20190043685A1 (en) * 2017-07-22 2019-02-07 Modern Electron, LLC Shadowed Grid Structures For Electrodes In Vacuum Electronics

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JP4833639B2 (ja) * 2005-11-09 2011-12-07 株式会社アルバック カソード基板及びその作製方法、並びに表示素子及びその作製方法
JP4755898B2 (ja) * 2005-12-28 2011-08-24 株式会社アルバック カソード基板の作製方法及び表示素子の作製方法
CN102034664A (zh) * 2009-09-30 2011-04-27 清华大学 场发射阴极结构及场发射显示器
EP2602830A4 (en) * 2010-08-05 2017-03-22 Fujitsu Limited Method for manufacturing semiconductor device and method for growing graphene
CN101908457B (zh) * 2010-08-27 2012-05-23 清华大学 金属栅网及场发射装置和场发射显示器
CN105374654B (zh) * 2014-08-25 2018-11-06 同方威视技术股份有限公司 电子源、x射线源、使用了该x射线源的设备
CN110767519B (zh) * 2019-10-21 2022-03-04 中国电子科技集团公司第十二研究所 一种场发射电子源结构及其形成方法、电子源、微波管
CN114525498B (zh) * 2022-03-07 2022-11-01 苏州迈为科技股份有限公司 下垂罩板及带有该下垂罩板的pecvd设备

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US5621272A (en) * 1995-05-30 1997-04-15 Texas Instruments Incorporated Field emission device with over-etched gate dielectric
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Publication number Priority date Publication date Assignee Title
DE102010000895B4 (de) * 2010-01-14 2018-12-27 Robert Bosch Gmbh Verfahren zum Herstellen eines Durchkontaktes eines Halbleiterbauelements mit einem umgebenden ringförmigen Isolationsgraben und entsprechendes Halbleiterbauelement
US20190043685A1 (en) * 2017-07-22 2019-02-07 Modern Electron, LLC Shadowed Grid Structures For Electrodes In Vacuum Electronics
US10658144B2 (en) * 2017-07-22 2020-05-19 Modern Electron, LLC Shadowed grid structures for electrodes in vacuum electronics

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Publication number Publication date
JP2005251430A (ja) 2005-09-15
KR101121195B1 (ko) 2012-03-23
CN1664972A (zh) 2005-09-07
JP4456891B2 (ja) 2010-04-28
CN100477060C (zh) 2009-04-08
KR20060043044A (ko) 2006-05-15
TW200531116A (en) 2005-09-16
US20090325452A1 (en) 2009-12-31
TWI359436B (https=) 2012-03-01

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