US20040135157A1 - Combined semiconductor apparatus with semiconductor thin film - Google Patents

Combined semiconductor apparatus with semiconductor thin film Download PDF

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Publication number
US20040135157A1
US20040135157A1 US10/743,104 US74310403A US2004135157A1 US 20040135157 A1 US20040135157 A1 US 20040135157A1 US 74310403 A US74310403 A US 74310403A US 2004135157 A1 US2004135157 A1 US 2004135157A1
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Prior art keywords
semiconductor
thin film
combined
layer
led
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US10/743,104
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Mitsuhiko Ogihara
Hiroyuki Fujiwara
Masaaki Sakuta
Ichimatsu Abiko
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Oki Electric Industry Co Ltd
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Individual
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Assigned to OKI DATA CORPORATION reassignment OKI DATA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ABIKO, ICHIMATSU, FUJIWARA, HIROYUKI, OGIHARA, MITSUHIKO, SAKUTA, MASAAKI
Publication of US20040135157A1 publication Critical patent/US20040135157A1/en
Priority to US12/654,486 priority Critical patent/US8664668B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/435—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material
    • B41J2/447—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources
    • B41J2/45—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources using light-emitting diode [LED] or laser arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components

Definitions

  • the present invention relates to a combined semiconductor apparatus useful in, for example, a light-emitting diode (LED) print head in an electrophotographic printer.
  • LED light-emitting diode
  • FIG. 26 is a perspective view schematically showing a part of a conventional LED print unit
  • FIG. 27 is a plan view showing a part of an LED array chip provided to the LED print unit of FIG. 26.
  • a conventional LED print unit 900 includes a circuit board 901 on which are mounted a plurality of LED array chips 902 having electrode pads 903 , and a plurality of driving integrated circuit (IC) chips 904 having electrode pads 905 .
  • the electrode pads 903 and 905 are interconnected by bonding wires 906 through which current is supplied from the driving-IC chips 904 to LEDs 907 formed in the LED array chips 902 .
  • Further electrode pads 909 on the driving-IC chips 904 are connected to bonding pads 910 on the circuit board 901 by further bonding wires 911 .
  • the electrode pads 903 , 905 , and 909 must be comparatively large, e.g., one hundred micrometers square (100 ⁇ m ⁇ 100 ⁇ m), and the LED array chips 902 must have approximately the same thickness as the driving-IC chips 904 (typically 250-300 ⁇ m), even though the functional parts of the LED array chips 902 (the LEDs 907 ) have a depth of only about 5 ⁇ m from the surface.
  • an LED array chip 902 must therefore be much larger and thicker than necessary simply to accommodate the LEDs 907 . These requirements drive up the size and material cost of the LED array chips 902 .
  • the electrode pads 903 may need to be arranged in a staggered formation on each LED array chip 902 . This arrangement further increases the chip area and, by increasing the length of the path from some of the LEDs 907 to their electrode pads 903 , increases the associated voltage drop.
  • the size of the driving-IC chips 904 also has to be increased to accommodate the large number of bonding pads 905 by which they are interconnected to the LED array chips 902 .
  • Light-emitting elements having a thin-film structure are disclosed in Japanese Patent Laid-Open Publication No. 10-063807 (FIGS. 3-6, FIG. 8, and paragraph 0021), but these light-emitting elements have electrode pads for solder bumps through which current is supplied. An array of such light-emitting elements would occupy substantially the same area as a conventional LED array chip 902 .
  • a combined semiconductor apparatus includes a semiconductor substrate having an integrated circuit, a planarized region formed in a surface of the semiconductor substrate, and a semiconductor thin film including at least one semiconductor device and bonded on the planarized region.
  • a surface of the semiconductor thin film, in which the semiconductor device is formed, may be disposed on a side of the planarized region.
  • the apparatus may further include a planarized film disposed between the planarized region and the semiconductor thin film.
  • FIG. 1 is a perspective view schematically showing a part of an integrated LED/driving-IC chip in accordance with a first embodiment of the present invention
  • FIG. 2 is a perspective view schematically showing a part of the integrated LED/driving-IC chip of the first embodiment before an LED epitaxial film is bonded;
  • FIG. 3 is a plan view schematically showing a part of the integrated LED/driving-IC chip of the first embodiment
  • FIG. 4 is a schematic cross sectional view showing a cross section through line S 4 -S 4 in FIG. 3;
  • FIGS. 5A and 5B are schematic cross sectional views for explaining a process of forming a planarized film in the integrated LED/driving-IC chip of the first embodiment
  • FIG. 6 is a plan view schematically showing a part of the integrated LED/driving-IC chip of the first embodiment after forming common interconnecting layers;
  • FIG. 7 is a schematic cross sectional view for explaining a first process of fabricating an LED epitaxial film of the first embodiment
  • FIG. 8 is a schematic cross sectional view for explaining a second process of fabricating the LED epitaxial film in the first embodiment
  • FIG. 9 is a schematic cross sectional view for explaining a third process of fabricating the LED epitaxial-film in the first embodiment
  • FIG. 10 is a schematic cross sectional view showing a cross section through line S 10 -S 10 in FIG. 9;
  • FIGS. 11A to 11 D are schematic cross sectional views for explaining a process of bonding the LED epitaxial in the first embodiment
  • FIG. 12 is a schematic plan view showing a part of the integrated LED/driving-IC chip in accordance with a modification of the first embodiment
  • FIG. 13 is a perspective view schematically showing a part of an integrated LED/driving-IC chip in accordance with a second embodiment of the present invention.
  • FIG. 14 is a schematic perspective view showing the integrated LED/driving-IC chip of the second embodiment before an LED epitaxial film is bonded;
  • FIG. 15 is a schematic cross sectional view showing a cross section through line S 15 -S 15 in FIG. 13;
  • FIG. 16 is a perspective view schematically showing a part of an integrated LED/driving-IC chip in accordance with a third embodiment of the present invention.
  • FIG. 17 is a perspective view schematically showing the integrated LED/driving-IC chip of the third embodiment before an LED epitaxial film is bonded;
  • FIG. 18 is a plan view schematically showing a part of the integrated LED/driving-IC chip of the third embodiment
  • FIG. 19 is a perspective view schematically showing a part of an integrated LED/driving-IC chip in accordance with a fourth embodiment of the present invention.
  • FIG. 20 is a perspective view schematically showing the integrated LED/driving-IC chip of the fourth embodiment before an LED epitaxial film is bonded;
  • FIG. 21 is a plan view schematically showing a part of the integrated LED/driving-IC chip of the fourth embodiment
  • FIG. 22 is a schematic cross sectional view showing a cross section through line S 22 -S 22 in FIG. 21;
  • FIG. 23 is a schematic cross sectional view showing an integrated LED/driving-IC chip in accordance with a fifth embodiment of the present invention.
  • FIG. 24 is a schematic cross sectional view showing an LED print head equipped with a combined semiconductor apparatus of the present invention.
  • FIG. 25 is a schematic cutaway side view of an LED printer employing the invented semiconductor apparatus
  • FIG. 26 is a perspective view schematically showing a part of a conventional LED print unit.
  • FIG. 27 is a plan view showing a part of an LED array chip provided in the LED print unit of FIG. 26.
  • FIG. 1 is a perspective view schematically showing a part of an integrated LED/driving-IC chip 100 as a combined semiconductor apparatus in accordance with a first embodiment of the present invention
  • FIG. 2 is a perspective view schematically showing the integrated LED/driving-IC chip 100 before an LED epitaxial film 110 is bonded
  • FIG. 3 is a plan view schematically showing a part of the integrated LED/driving-IC chip 100
  • FIG. 4 is a schematic cross sectional view showing a cross section through line S 4 -S 4 in FIG. 3.
  • an integrated LED/driving-IC chip 100 of the first embodiment includes a silicon (Si) substrate 101 as a semiconductor substrate which has an integrated circuit 102 and a planarized region 103 formed in a surface of the Si substrate 101 .
  • the planarized region 103 is obtained by forming a dielectric layer (not shown in the figures) on the surface of the Si substrate 101 and then subjecting the surface of the Si substrate 101 to a planarizing process such as chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the planarized region 103 is formed on the integrated circuit 102 of the Si substrate 101 in the first embodiment, the planarized region 103 may be formed in a region of the Si substrate 101 adjacent to the integrated circuit 102 .
  • the integrated LED/driving-IC chip 100 of the first embodiment also includes a planarized film 104 disposed on the planarized region 103 .
  • the planarized film 104 has a metal layer 105 and an interdielectric layer 106 formed in a region peripheral to the metal layer 105 .
  • An upper surface of the planarized film 104 is subjected to a planarizing process such as CMP.
  • the integrated LED/driving-IC chip 100 further includes a sheet-like semiconductor epitaxial film 110 including LEDs 120 and bonded on the upper surface of the planarized film 104 .
  • the planarized film 104 may be omitted and the LED epitaxial film 110 may be bonded directly on the surface of the planarized region 103 .
  • the LED epitaxial film 110 is formed with a plurality of LEDs (also referred to below as light-emitting parts or regions) 120 .
  • the plurality of LEDs 120 is arranged in a row at regular intervals.
  • the arrangement of the LEDs 120 is not limited to the regular intervals.
  • the arrangement of the LEDs 120 is not limited to a single row, but the LEDs 120 may be arranged as regularly shifted in a direction perpendicular to a direction of the arrangement of the LEDs 120 .
  • number of LEDs 120 to be formed to the LED epitaxial film 110 is not limited to the illustrated number. Further, as shown in FIG.
  • the LED epitaxial film 110 has a width W 1 larger than a width W 2 of the light-emitting region 120 .
  • the width W 2 of the light-emitting region 120 is set to be 20 ⁇ m
  • the width W 1 of the LED epitaxial film 110 is set to be 50 ⁇ m, so that a margin of 15 ⁇ m is provided to each of both sides of the light-emitting region 120 .
  • the width W 1 of the LED epitaxial film 110 is much smaller than width (typically, about 400 ⁇ m) of a substrate of the conventional LED print head having electrode pads.
  • the width W 1 of the LED epitaxial film 110 and the width W 2 of the light-emitting region 120 are not limited to the aforementioned values.
  • the LED epitaxial film 110 will be made of only epitaxial layers to be explained later.
  • the thickness of the LED epitaxial film 110 may be about 2 ⁇ m that is sufficient to secure stable characteristics (e.g., light-emitting characteristics or electrical characteristics) of the LED 120 .
  • the thickness of the LED epitaxial film 110 is much smaller than the thickness (typically, about 300 ⁇ m) of the conventional LED print head. As the thickness of the LED epitaxial film 110 is increased, a disconnection due to poor step coverage tends to probably occur in the thin-film wiring layer (e.g. the layer 130 shown in FIG. 6) formed on the LED epitaxial film 110 .
  • the LED epitaxial film 110 have a thickness of about 10 ⁇ m or less.
  • the thickness of the LED epitaxial film 110 it is also possible to set the thickness of the LED epitaxial film 110 to exceed 10 ⁇ m.
  • the Si substrate 101 is a monolithic Si substrate, in which the integrated circuit 102 is formed.
  • the integrated circuit 102 includes a plurality of driving-ICs for driving the LEDs 120 formed in the LED epitaxial film 110 . Besides the driving circuits, the integrated circuit 102 includes shared circuitry for illumination control of the LEDs 120 .
  • the Si substrate 101 has a thickness of about 300 ⁇ m, for example.
  • the integrated circuit 102 of the Si substrate 101 has a rough or irregular surface due to the openings of the interdielectric layer, wiring pattern, etching pattern, etc.
  • a dielectric layer (not shown in the figures) is formed on the irregular surface of the integrated circuit 102 and then subjected to a planarizing process such as CMP, thus forming the planarized region 103 .
  • the planarized film 104 disposed on the planarized region 103 includes a plurality of the metal layers 105 formed on predetermined regions on which the LEDs 120 of the LED epitaxial film 110 are to be bonded, and the interdielectric layer 106 formed on the peripheral region of the metal layers 105 to have the same thickness as that of the metal layers 105 .
  • the structure and material of the planarized film 104 are not restricted to the illustrated or above-described ones.
  • the structure and material of the planarized film 104 may be determined by various factors including the structure and material of the planarized region 103 of the Si substrate 101 , and the shape, size, thickness and material of the LED epitaxial film 110 .
  • FIGS. 5A and 5B are schematic cross sectional views for explaining a process of forming the planarized film 104 .
  • an interconnecting layer 105 a, an interdielectric layer 106 a and a metal layer 105 b are sequentially formed on the planarized region 103 of the Si substrate 101 .
  • the interdielectric layer 106 a and metal layer 105 b are subjected to a planarizing process such as CMP (Chemical Mechanical Polishing) to planarize surfaces of the metal layers 105 and interdielectric layer 106 .
  • CMP Chemical Mechanical Polishing
  • planarized film 104 is formed on the planarized region 103 .
  • the structure of the planarized film 104 and a method of forming the planarized film 104 are not restricted to the aforementioned structure and method.
  • a spin-on-glass (SOG) method which is generally used for forming a surface protective film of an IC or an LSI, may be used for forming a planarized film on the Si substrate 101 .
  • the SOG method includes, for example, the steps of dropping ether-series solvent with dissolved organic silicon onto the Si substrate 101 , rotating the Si substrate 101 at a high speed to form a uniform and thin SOG film on the Si substrate 101 , and subsequently heating the Si substrate 101 at a range between 300 to 500 degrees centigrade to remelt the SOG film for a certain period for hardening the SOG film.
  • the interdielectric layer 106 a is made of an insulating film such as an oxide film or a nitride film made of, e.g., SiO 2 , SiN or polyamide.
  • the metal layer 105 is made of, e.g., palladium or gold or metal material including palladium and/or gold.
  • the metal layer 105 may be a conduction layer of electrically conductive material (such as polysilicon) other than metal.
  • flatness (which is an indicator used for indicating unevenness on the surface) of the planarized region 103 is preferably not more than 10 nanometers. The smaller the value of flatness becomes, the more preferable the planarized region 103 becomes.
  • the LED epitaxial film 110 has a first surface 110 a, in which the LEDs 120 are formed, and a second surface 110 b opposed to the first surface 110 a and having a common electrode layer 116 .
  • the light-emitting parts 120 are positioned in the first surface 110 a in the LED epitaxial film 110 .
  • the first surface 110 a of the LED epitaxial film 110 is located on the side of the planarized region 103 .
  • the LED epitaxial film 110 is bonded on the planarized film 104 in such a way that the plurality of LEDs 120 are in contact with the associated metal layers 105 .
  • the integrated LED/driving-IC chip 100 has a structure in which sequentially laminated are the Si substrate 101 , the integrated circuit 102 , the planarized region 103 , the planarized film 104 , the LED epitaxial film 110 , and a common electrode layer 116 . More specifically, the planarized region 103 is formed on the integrated circuit 102 of the Si substrate 101 , the planarized film 104 is formed on the planarized region 103 , the first surface 110 a provided with the LEDs 120 is disposed on the side of the planarized region 103 in the LED epitaxial film 110 .
  • the common electrode layer 116 may be made of an electrically conductive material, through which light can pass, such as a transparent oxide electrically conductive film.
  • the transparent oxide electrically conductive film may be made of, e.g., indium tin oxide (ITO) or zinc oxide (ZnO).
  • the LED epitaxial film 110 has a stacking layered structure of an n-type Al z Ga 1-z As layer 114 (0 ⁇ z ⁇ 1), an n-type Al y Ga 1-y As layer 113 (0 ⁇ y ⁇ 1), and an n-type Al x Ga 1-x As layer 112 (0 ⁇ x ⁇ 1), and an n-type GaAs layer 111 .
  • a Zn diffusion region 115 is formed in the n-type Al y Ga 1-y As layer 113 and n-type Al z Ga 1-z As layer 114 .
  • the common electrode layer 116 is formed on the n-type GaAs layer 111 .
  • the thicknesses of the above layers are not limited to the above values.
  • the material of the LED epitaxial film 110 may be replaced by other material such as (Al x Ga 1-x ) y In 1-y P, where 0 ⁇ x ⁇ 1 and 0 ⁇ z ⁇ 1, in this case, GaN, AlGaN, or InGaN.
  • minority carriers injected through the pn junction are confined within the n-type Al y Ga 1-y As active layer 113 and the p-type Al y Ga 1-y As region created therein by zinc diffusion, so that high luminous efficiency is obtained.
  • the structure shown in FIG. 4 enables high luminous efficiency to be obtained with an LED epitaxial film 110 as thin as about 2 ⁇ m.
  • the LED epitaxial film 110 is not limited to thicknesses or materials given above.
  • Other materials such as an aluminum-gallium indium phosphide ((Al x Ga 1-x ) y In 1-y P, where 0 ⁇ x ⁇ 1 and 0 ⁇ y ⁇ 1, a gallium nitride (GaN), an aluminum gallium nitride (AlGaN), and an indium gallium nitride (InGaN), may also be employed.
  • GaN gallium nitride
  • AlGaN aluminum gallium nitride
  • InGaN indium gallium nitride
  • a single hetero-epitaxial structure and a homo-epitaxial structure can be also applied in LEDs.
  • FIG. 6 Shown in FIG. 6 is a schematic plan view of a part of the integrated LED/driving-IC chip 100 after common interconnecting layers 130 are formed.
  • the common interconnecting layers 130 are electrically connected to associated common electrode terminals 107 of the integrated circuit 102 of the Si substrate 101 .
  • the Zn diffusion region 115 shown in FIG. 4) is electrically connected to the metal layer or conductive layer 105 .
  • the metal layer 105 is electrically connected to the integrated circuit 102 (not shown in the figure).
  • the common interconnecting layer 130 is, for example, a thin metal wiring film.
  • FIGS. 7 to 10 are schematic cross sectional views for explaining process of fabricating an LED epitaxial film 110 of the first embodiment. Further, FIG. 9 shows a cross section through line S 9 -S 9 in FIG. 10, and FIG. 10 shows a cross section through line S 10 -S 10 in FIG. 9.
  • An LED epitaxial layer 110 c can be fabricated by the techniques such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). After lifting off the LED epitaxial layer 110 c, it becomes the LED epitaxial film 110 . Before fabricating the LED epitaxial layer 110 c, as shown in FIG. 7, the LED epitaxial film fabrication substrate 140 is formed.
  • the fabrication substrate 140 in FIG. 7 includes a GaAs substrate 141 , a GaAs buffer layer 142 , an aluminum-gallium indium phosphide ((AlGa)InP) etching stop layer 143 , and an aluminum arsenide (AlAs) sacrificial layer 144 .
  • the n-type GaAs contact layer 111 , n-type Al x Ga 1-x As lower cladding layer 112 , n-type Al y Ga 1-y As active layer 113 , and n-type Al z Ga 1-z As upper cladding layer 114 are formed in this order on the AlAs sacrificial layer 144 , creating an LED epitaxial layer 110 c.
  • Lifting-off of the LED epitaxial layer 110 c can be carried out by a chemical lift off method. In this case, the (AlGa)InP etching stop layer 143 can be omitted.
  • the structures of the semiconductor epitaxial layer 110 c and the fabrication substrate 140 are not limited to those shown in FIG. 7, and various modifications of the LED epitaxial layer 110 c and the fabrication substrate 140 can be made.
  • a p-type impurity comprising zinc (Zn) is diffused by, for example, a solid-phase diffusion method to create the zinc diffusion regions 115 .
  • the diffusion source film (not shown in the figures) used for the solid-phase diffusion process is then removed to expose the surface of the zinc diffusion regions 115 .
  • the AlAs sacrificial layer 144 is selectively removed with use of a 10% HF (hydrogen fluoride) solution. Since an etching rate for the AlAs sacrificial layer 144 is much larger than an etching rate for the AlGaAs layers 112 to 114 , GaAs layers 111 , 141 , 142 , and etching stop layer 143 ; the AlAs sacrificial layer 144 can be selectively etched. As a result, the LED epitaxial layer 110 c (LED epitaxial film 110 ) can be lifted off from the LED epitaxial film fabrication substrate 140 .
  • a 10% HF hydrogen fluoride
  • the LED epitaxial film 110 for the purpose of making the LED epitaxial film 110 thin and also to lift off the LED epitaxial film 110 from the fabrication substrate 140 in a comparative short time, it is desirable that the LED epitaxial film 110 have a width of 300 ⁇ m or less, e.g., about 50 ⁇ m.
  • the respective epitaxial layers 111 to 114 are previously etched so that trenches 145 are made therein and the layers have a width W 1 of 50 ⁇ m.
  • the supporting material when the supporting material is provided on the LED epitaxial film 110 , the supporting material can be transferred to a predetermined position by sucking the surface of the supporting material for the LED epitaxial film by vacuum suction or bonding the surface of the supporting material for the LED epitaxial film by a photo-hardening adhesive sheet, which hardens and loses its adhesive property when subjected to light irradiation.
  • FIGS. 11A to 11 D are schematic cross sectional views for explaining a process of bonding the LED epitaxial film 110 in the integrated LED/driving-IC chip of the first embodiment.
  • the LED epitaxial film 110 (corresponding to the LED epitaxial layer 110 c in FIGS. 9 and 10 before lifting-off) is lifted from the fabrication substrate 140 and carried by a photo-hardening adhesive sheet 150 a of a first supporting material 150 , and, as shown in FIG. 11B, is bonded onto a photo-hardening adhesive sheet 160 a of a second supporting material 160 .
  • the surface area of the LED epitaxial film 110 can be made small and thus the integrated LED/driving-IC chip 100 can be made small in size.
  • the surface area of the LED epitaxial film 110 can be made small, its material cost can be reduced.
  • the LED epitaxial film 110 is supported by the Si substrate 101 and need not be thickened to provide strength for wire bonding, it can be much thinner than a conventional LED array chip. This effect lead to a substantial reduction in material costs.
  • the first surface 110 a of the LED epitaxial film 110 provided with the LEDs 120 is located on the side of the Si substrate 101 provided with the planarized region 103 and overlapped with the metal layer 105 .
  • the LED epitaxial film 110 is provided on the planarized region 103 above the integrated circuit 102 , the width of the Si substrate having the integrated circuit 102 can be reduced to a large extent.
  • the common interconnecting layer 131 has such a shape as to spread nearly all over the LED epitaxial film 110 other than openings 131 a on the LEDs 120 .
  • a metal layer or a transparent electrode or a semi-transparent electrode can be used as the common interconnecting layer 131 . In this case, fluctuations in the potential of the common electrode layer 116 of the LED epitaxial film 110 can be made small and fluctuations in the luminous intensities of the LEDs 120 can be made small.
  • FIG. 13 is a perspective view schematically showing a part of an integrated LED/driving-IC chip 200 in accordance with a second embodiment of the present invention
  • FIG. 14 is a perspective view schematically showing the integrated LED/driving-IC chip 200 of the second embodiment before the LED epitaxial films 210 are bonded
  • FIG. 15 is a schematic cross sectional view showing a cross section through line S 15 -S 15 in FIG. 13.
  • FIG. 13 parts that are the same as or correspond to those in FIG. 1 (first embodiment) are denoted by the same reference numerals.
  • FIG. 14 parts that are the same as or correspond to those in FIG. 2 (first embodiment) are denoted by the same reference numerals.
  • FIG. 15 parts that are the same as or correspond to those in FIG. 4 (first embodiment) are denoted by the same reference numerals.
  • An integrated LED/driving-IC chip 200 shown in FIGS. 13 and 14 is different from the integrated LED/driving-IC chip 100 of the first embodiment shown in FIGS. 1 and 2 in that a single LED epitaxial film 210 is bonded onto each metal layer 105 and that each LED epitaxial film 210 has a single LED.
  • various types of structures including provision of nondoped active layer between cladding layers or insertion of a quantum-well layer between in the cladding layers can be employed.
  • the LED epitaxial films 210 are divided to be small.
  • a problem with the internal stress of the LED epitaxial films 210 involved when the thermal expansion coefficient of the LED epitaxial films 210 and the thermal expansion coefficient of the Si substrate 101 are largely different, can be reduced, and thus one of factors causing a defect in the LED epitaxial films 204 can be eliminated.
  • the integrated LED/driving-IC chip 200 of the second embodiment can be increased in reliability.
  • the second embodiment is substantially the same as the above first embodiment, except for the above-described respects.
  • the integrated LED/driving-IC chip 300 also includes thin individual interconnecting layers 330 formed on a region extending from the upper surfaces of the LEDs 320 of the LED epitaxial film 310 to the upper surfaces of individual electrode terminals 308 of the integrated circuit 302 .
  • Formed under the individual interconnecting lines 330 is a suitable interdielectric layer (not shown in the figures).
  • the metal layer 305 is electrically connected to a common potential terminal provided on the substrate 301 .
  • the third embodiment is substantially the same as the above first or second embodiment, except for the above-described respects.
  • the integrated LED/driving-IC chip 400 also a sheet-like LED epitaxial film 410 including LEDs 420 and bonded on the metal layer 405 .
  • the LED epitaxial film 410 has a common interconnecting layer (not shown in the figures) on a second surface 410 b of the epitaxial film opposed to a first surface 410 a, in which the LEDs 420 is formed.
  • the LED epitaxial film 410 is bonded on the metal layer 405 so that the second surface 410 b is located on the side of the planarized region 403 of the Si substrate 301 .
  • a plurality of metal layers may be formed so that the LEDs 420 of the first surface 410 a are placed on the metal layers respectively.
  • a plurality of LED epitaxial films each having a single LED may be arranged in a row on the metal layer.
  • the LED epitaxial film 410 can be bonded on the Si substrate 401 at a position higher than an irregular surface 402 a of the integrated circuit 402 of the Si substrate 401 . For this reason, such a problem that a part (e.g., a bonding collet) of a device used in the process of bonding the LED epitaxial film 410 onto the metal layer 405 abuts against the surface 402 a of an integrated circuit 502 can be avoided.
  • a part e.g., a bonding collet
  • the LED epitaxial film 510 can be bonded at a position higher than the irregular surface 502 a of the integrated circuit 502 of the Si substrate 501 . For this reason, a problem that a part (e.g., bonding collet) of a device used in the process of bonding the LED epitaxial film 510 onto the metal layer 505 on the raised layer 504 can be easily avoided.
  • the paper 810 passes through the process units 801 , 802 , 803 , 804 in turn, traveling in each process unit between the photosensitive drum and a transfer roller 812 made of, for example, semi-conductive rubber.
  • the transfer roller 812 is charged so as to create a potential difference between it and the photosensitive drum.
  • the potential difference attracts the toner image from the photosensitive drum onto the paper 805 .
  • a full-color image is built up on the paper 805 in four stages, the yellow process unit 801 printing a yellow image, the magenta process unit 802 a magenta image, the cyan process unit 803 a cyan image, and the black process unit 804 a black image.
  • the LED heads account for a significant part of the manufacturing cost of this type of LED printer 800 .
  • the present invention enables a high-quality printer to be produced at a comparatively low cost.
  • the semiconductor substrate may be made of other materials such as amorphous silicon, single crystal silicon, polysilicon, compound semiconductor or organic semiconductor.
  • the semiconductor device may be another light-emitting element such as a laser, a light-sensing element, a Hall element, or a piezoelectric element.

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  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)
  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
  • Light Receiving Elements (AREA)
  • Solid State Image Pick-Up Elements (AREA)
US10/743,104 2002-12-24 2003-12-23 Combined semiconductor apparatus with semiconductor thin film Abandoned US20040135157A1 (en)

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US20130149803A1 (en) * 2011-12-12 2013-06-13 Electronics And Telecommunications Research Institute Method of fabricating organic light emitting diode
CN104040738A (zh) * 2011-12-23 2014-09-10 欧司朗光电半导体有限公司 用于制造多个光电子半导体芯片的方法和光电子半导体芯片
US9214342B2 (en) 2009-09-17 2015-12-15 Sumitomo Chemical Company, Limited Method for producing compound semiconductor crystal, method for producing electronic device, and semiconductor wafer
CN109300932A (zh) * 2018-11-12 2019-02-01 严光能 Led显示器及其制作方法

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DE102004050371A1 (de) * 2004-09-30 2006-04-13 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement mit einer drahtlosen Kontaktierung
JP4837295B2 (ja) * 2005-03-02 2011-12-14 株式会社沖データ 半導体装置、ｌｅｄ装置、ｌｅｄヘッド、及び画像形成装置
JP4636501B2 (ja) 2005-05-12 2011-02-23 株式会社沖データ 半導体装置、プリントヘッド及び画像形成装置
JP5258167B2 (ja) * 2006-03-27 2013-08-07 株式会社沖データ 半導体複合装置、ｌｅｄヘッド、及び画像形成装置
JP5438889B2 (ja) * 2007-06-20 2014-03-12 株式会社沖データ 半導体装置、及びｌｅｄプリントヘッド
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EP2500623A1 (en) 2011-03-18 2012-09-19 Koninklijke Philips Electronics N.V. Method for providing a reflective coating to a substrate for a light-emitting device
JP5404709B2 (ja) * 2011-08-02 2014-02-05 株式会社沖データ 半導体装置、ｌｅｄ装置、ｌｅｄヘッド、及び画像形成装置
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JP6129777B2 (ja) 2014-03-31 2017-05-17 株式会社沖データ 半導体装置、半導体装置の製造方法、プリントヘッド、及び画像形成装置
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DE102015115812B4 (de) * 2015-09-18 2025-12-04 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Bauelement sowie Verfahren zur Herstellung eines Bauelements

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US20080217414A1 (en) * 2007-03-09 2008-09-11 Oki Data Corporation Flexible display member and article having the same
US9214342B2 (en) 2009-09-17 2015-12-15 Sumitomo Chemical Company, Limited Method for producing compound semiconductor crystal, method for producing electronic device, and semiconductor wafer
US20130149803A1 (en) * 2011-12-12 2013-06-13 Electronics And Telecommunications Research Institute Method of fabricating organic light emitting diode
CN104040738A (zh) * 2011-12-23 2014-09-10 欧司朗光电半导体有限公司 用于制造多个光电子半导体芯片的方法和光电子半导体芯片
CN109300932A (zh) * 2018-11-12 2019-02-01 严光能 Led显示器及其制作方法

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US20100096748A1 (en) 2010-04-22
EP1434271A3 (en) 2011-01-12
EP1434271A2 (en) 2004-06-30
US8664668B2 (en) 2014-03-04
JP2004207323A (ja) 2004-07-22

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