US20020096677A1 - Semiconductor integrated circuit having noise detect circuits detecting noise on power supply nets - Google Patents

Semiconductor integrated circuit having noise detect circuits detecting noise on power supply nets Download PDF

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US20020096677A1
US20020096677A1 US09/946,451 US94645101A US2002096677A1 US 20020096677 A1 US20020096677 A1 US 20020096677A1 US 94645101 A US94645101 A US 94645101A US 2002096677 A1 US2002096677 A1 US 2002096677A1
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power supply
noise
circuit
semiconductor integrated
nets
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Fumio Yuuki
Katsuya Tanaka
Takeshi Kato
Teruhisa Shimizu
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Hitachi Ltd
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Assigned to HITACHI, LTD. reassignment HITACHI, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHIMZU, TERUHISA, YUUKI, FUMIO, KATO, TAKESHI, TANAKA, KATSUYA
Publication of US20020096677A1 publication Critical patent/US20020096677A1/en
Priority to US11/253,833 priority Critical patent/US7339411B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor integrated circuit that prevents a malfunction caused by noise on power supply nets and is suitable to cost reduction, and in particular, to a CMOS processor.
  • bypass capacitors or condensers As a general measure of RF noise reduction, there is a method of mounting bypass capacitors or condensers in an LSI chip. This is a method of connecting bypass condensers to respective places of power supply nets so that a malfunction may not occur to the worst noise in the LSI chip.
  • FIG. 15 shows a conventional semiconductor integrated circuit on which bypass condensers are mounted.
  • Power supply nets inside a chip are arranged in a mesh-like shape in the XY directions.
  • the bypass condensers are arranged an area just under the power supply nets inside the chip in the Y direction, and areas, which are vacant after spreading gates all over, as much as possible.
  • a bypass condenser is typically formed with a capacity between gate channels of an MOS transistor.
  • VSS is connected to a gate
  • a drain and a source are connected to VDD.
  • VDD is connected to a gate
  • VSS is connected to a drain and a source.
  • a necessary amount of condensers is decided in consideration of the switching current of MOS transistors in an entire chip.
  • bypass condensers occupy 20% of chip size.
  • a preventive measure against a malfunction caused by the noise on power supply nets a method of detecting the noise and performing interruption is known.
  • a conventional method of the noise detection and interruption processing for example, a method described in JP-A-9-73400 is known.
  • JP-A-9-73400 The external noise that invades into the power supply nets of an I/O circuit section arranged around a semiconductor integrated circuit is detected, and a malfunction of internal circuits is prevented by the interruption.
  • noise detecting circuit for example, a circuit described in U.S. Pat. No. 6,191,647 is known. This circuit has the structure of receiving power supply from a power supply line other than a power supply line set as an object of noise observation to avoid that noise on the power supply nets influences the observation of noise itself.
  • a conventional semiconductor integrated circuit detects external noise which enters into power supply nets of an I/O circuit and prevents a malfunction, but does not correspond to the prevention of a malfunction caused by the noise inside internal circuits.
  • a noise detecting circuit judges that the voltage difference between a supply voltage signal to be monitored and a power supply voltage of a circuit is noise.
  • a power supply voltage for a noise detecting circuit that operates with a power supply where the noise on power supply nets is generated is drifted by the noise.
  • the noise detecting circuit cannot detect the voltage difference between the power supply voltage and the noise.
  • a first object of the present invention is to provide a semiconductor integrated circuit which prevents a malfunction of a semiconductor integrated circuit and makes cost reduction possible, in order to solve the above-described problem (1).
  • a second object of the present invention is to provide a semiconductor integrated circuit that can prevent a malfunction caused by noise in an internal circuit of the semiconductor integrated circuit, in order to solve an above-described problem (2).
  • a third object of the present invention is to provide a noise detecting circuit that can detect noise also under a noise environment, in order to solve the above-described problem (3).
  • the configuration of the present invention is characterized by including a noise detecting circuit which detects noise on power supply nets inside at least one circuit block, and performing interruption for preventing a malfunction to the above-described circuit block itself or another circuit block relating to this signal processing with this detection signal of the above-described noise detecting circuit.
  • the processor has a noise detecting circuit which detects noise on power supply nets inside at least one circuit block, and a circuit block receiving a detection signal of the above-described noise detecting circuit and performing recovery processing to the above-described logical circuit blocks or memory circuit blocks.
  • the semiconductor integrated circuit has at least one pair of circuit blocks, which has the same functions and operates in parallel, and has a noise detecting circuit, which detects noise on power supply nets, inside at least one of the above-described pair of circuit blocks, and collates the signal processing result of the above-described plurality of circuit blocks with a detecting signal of the above-described noise detecting circuit and performs interruption for preventing a malfunction to the circuit block itself or other circuit blocks relating to this signal processing.
  • the processor has a circuit block that has at least one pair of circuit blocks that operates in parallel to each other and is redundantly doubled, and has a noise detecting circuit which detects noise on power supply nets inside at least one of the above-described pair of circuit blocks, collates the signal processing result of the above-described pair of circuit blocks with a detection signal of the above-described noise detecting circuit, and performs recovery processing.
  • the above-described semiconductor integrated circuit makes a circuit block itself or other circuit blocks relating to this signal processing rerun the signal processing by the above-described interruption if a detection signal which shows that noise on power supply nets which induces a malfunction arises from the above-described power supply noise detecting circuit is outputted.
  • the above-described semiconductor integrated circuit moves to system failure treatment if a detection signal which shows that noise on power supply nets which induces a malfunction arises from the above-described power supply noise detecting circuit is again outputted at the time of the above-described rerun.
  • the above-described semiconductor integrated circuit suspends an output of the signal processing result of the above-described circuit block in the clock cycle concerned by the above-described interruption and outputs the signal processing result after the following cycle if a detection signal which shows that noise on power supply nets which induces a malfunction arises from the above-described power supply noise detecting circuit is outputted.
  • the above-described semiconductor integrated circuit performs the above-described interruption if the signal processing results from the above-described pair of circuit blocks differ from each other, or if a detection signal which shows that noise on power supply nets which induces a malfunction arises from the above-described power supply noise detecting circuit is outputted.
  • the present invention supplies electric power to the above-described power supply noise detecting circuit from power supply nets that are shared with the above-described circuit blocks, and generates a dedicated power supply, which is free from the influence of noise from the above-described power supply nets, inside a power supply noise detecting circuit.
  • the above-described power supply noise detecting circuit includes a noise detector which detects the noise produced in power supply nets of the above-described circuit block, a detection signal holder which holds an output of the above-described noise detector in a predetermined period, and a power supply which generates a dedicated power supply, which is free from the influence of noise from the above-described power supply nets, and supplies electric power thereof to the above-described noise detector.
  • the above-described noise detector includes a level shift circuit that shifts a voltage in the above-described power supply nets to a predetermined reference voltage level by making the voltage in the above-described power supply nets as an input, and a level discriminator which judges whether an output of the above-described level shift circuit exceeds a predetermined threshold voltage level.
  • the above-described detection signal holder includes a dynamic circuit of making a period, when the dynamic circuit operates in response to an output of the above-described noise detector, be an evaluation phase, and making periods except the above-described predetermined period be a precharge phase.
  • the above-described power supply generates a voltage that fluctuates with following the voltage fluctuation of a positive power supply or a negative power supply on the above-described power supply nets.
  • the above-described power supply noise detecting circuit generates a reset signal from a clock synchronization signal or its delayed signal
  • the above-described noise detector and the detection signal holder detect noise in a LOW period of the reset signal, and hold a detection signal
  • the above-described power supply charges a dedicated power supply in a HIGH period of the above-described reset signal.
  • FIG. 1 is a schematic diagram of a semiconductor integrated circuit chip according to a first embodiment of the present invention
  • FIG. 2 is a schematic diagram showing a circuit block according to the first embodiment of the present invention in detail
  • FIG. 3 is a flow chart showing an interruption of the first embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a semiconductor integrated circuit chip that has a duplex circuit block according to a second embodiment of the present invention
  • FIG. 5 is a flow chart showing an interruption of the second embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a semiconductor integrated circuit chip which has a duplex circuit block according to a third embodiment of the present invention.
  • FIG. 7 is an explanatory diagram showing a pipeline of instruction processing in a third embodiment of the present invention.
  • FIG. 8 is a block diagram showing an instruction operation of the third embodiment of the present invention.
  • FIG. 9 is a timing chart of an interruption of the third embodiment of the present invention.
  • FIG. 10 is a circuit diagram showing a fourth embodiment of the present invention.
  • FIGS. 11A and 11B are operational wave form charts of the fourth embodiment of the present invention.
  • FIG. 12 is a circuit diagram showing a fifth embodiment of the present invention.
  • FIG. 13 is an operational timing chart of the fifth embodiment of the present invention.
  • FIG. 14 is a circuit diagram showing a sixth embodiment of the present invention.
  • FIG. 15 is a schematic diagram showing a semiconductor integrated circuit on which conventional bypass condensers are mounted.
  • FIG. 1 is a schematic diagram showing a semiconductor integrated circuit that has a noise detecting circuit according to a first embodiment of the present invention.
  • a semiconductor integrated circuit 100 comprises a plurality of circuit blocks 110 , 111 , 112 , 113 , 114 , 115 , and 116 , noise detecting circuits 120 , 121 , 122 , 123 , 124 , 125 , and 126 corresponding to each circuit block, an interruption handling circuit 130 , and internal power supply nets 140 , and 141 .
  • FIG. 2 is a schematic diagram showing a circuit block according to the first embodiment of the present invention in detail.
  • a circuit block 210 consists of a general logic gate 220 , a noise detecting circuit 230 , and internal power supply nets 240 , 241 , and 242 .
  • the noise detecting circuit 230 is connected to the same power supply nets as those of the general logic gate 220 .
  • the noise detecting circuit 120 if detecting noise on the power supply nets having a level, which is a error-including level or more, in the circuit block 110 , 111 , 112 , 113 , 114 , 115 , 116 , or 210 , the noise detecting circuit 120 , 121 , 122 , 123 , 124 , 125 , 126 , or 230 sends a detection signal 150 , 151 , 152 , or 250 to the interruption handling circuit 130 . Then, the interruption handling circuit 130 that receives the signal performs interruption by sending an interruption signal to the circuit block relating to this signal processing, which in not shown.
  • FIG. 3 is a flow chart showing the interrupt processing of the first embodiment of the present invention.
  • a semiconductor integrated circuit of this embodiment executes an instruction after receiving the instruction, and outputs the result.
  • the interruption processing by detection of noise on the power supply nets is performed according to a flow in FIG. 3.
  • An instruction is fetched by the semiconductor integrated circuit (step 310 ).
  • noise is monitored every stage (step 330 ). If there is no noise to a final stage, the result is outputted ( 340 ). If noise is detected on any one of stages, the process moves to interruption ( 370 ). Then, a rerun by the interruption is performed after returning to the stage where the interruption arises.
  • the first embodiment of the present invention is that, in a semiconductor integrated circuit which consists of a plurality of circuit blocks performing signal processing, the semiconductor integrated circuit comprises a noise detecting circuit which detects noise on power supply nets inside at least one circuit block, and performs interruption for preventing a malfunction to the above-described circuit block itself or another circuit block relating to this signal processing with this detection signal of the above-described noise detecting circuit.
  • the interruption according to this embodiment is the processing of making the above-described circuit block itself or other circuit blocks, relating to this signal processing, rerun the signal processing by the above-described interruption if a detection signal which shows that noise on power supply nets which induces a malfunction arises in a semiconductor integrated circuit is outputted from the above-described noise detecting circuit.
  • a detection signal which shows that noise on power supply nets which induces a malfunction arises in the above-described semiconductor integrated circuit is again outputted from the above-described power supply noise detecting circuit at the time of the above-described rerun, the process shifts to system failure treatment.
  • the above-described first embodiment is effective in preventing a malfunction caused by the noise on power supply nets that increases with the acceleration and high integration. In addition, it is also effective in preventing the increase of chip size accompanying the high integration and measures against the noise.
  • FIG. 4 is a schematic diagram showing a duplex semiconductor integrated circuit that has a power supply noise detecting circuit according to a second embodiment of the present invention.
  • a semiconductor integrated circuit 400 comprises a plurality of circuit blocks 410 , 411 , and 412 , and redundant circuit blocks 413 , 414 , and 415 which have the same functions as those of the circuit blocks which correspond to each and operate in parallel.
  • the circuit blocks 410 , 411 , and 412 are equipped with noise detecting circuits 420 , 421 , and 422 respectively.
  • Detected outputs of the noise detecting circuits 440 , 441 , and 442 which detect the noise on power supply nets of respective internal power supply nets 440 and 441 are led to an interruption handling circuit 430 .
  • the semiconductor integrated circuit 400 has a function of reporting error generation by comparing mutual outputs of the circuit blocks that perform parallel operation with the same functions, and detecting the discrepancy.
  • a malfunction by the noise on power supply nets is checked by mounting each of the noise detecting circuits 420 , 421 , 422 in at least one of the pair of circuit blocks.
  • the noise detecting circuits 420 , 421 , 422 since circuits similarly operate in the pair of circuit blocks, conditions of generating noise on power supply nets also becomes the same. Hence, a malfunction can be checked by monitoring one of the pair of circuit blocks.
  • FIG. 5 is a flow chart showing the flow of the interruption of this embodiment.
  • the interruption flow by noise detection is the same as that in FIG. 3.
  • outputs of the duplex circuit block is compared at step 540 .
  • the result is outputted (step 550 ), and if not, the process shifts to interruption (step 580 ).
  • a rerun in this case is performed by returning to the fetch of the instruction (step 510 ) when interrupted.
  • FIG. 6 is a schematic diagram showing a duplex processor that has a noise detecting circuit according to a third embodiment of the present invention.
  • a processor chip 600 has two processors 610 and 611 .
  • the processor 610 comprises a buffer storage BS 630 , a buffer control unit BU 640 , a recovery unit RU 650 , duplex instruction units IU 660 and 661 , duplex general arithmetic units GU 670 and 671 , and duplex floating point execution units FU 680 and 681 .
  • the processor 611 has the same configuration as that of the processor 610 , and comprises a buffer storage BS 631 , a buffer control unit BU 641 , a recovery unit RU 651 duplex instruction units IU 662 and 663 , duplex arithmetic units GU 672 and 673 , and duplex floating point execution units FU 682 and 683 .
  • the global storage unit GSU 620 is used in common in the two processors 610 and 611 .
  • a noise detecting circuit 690 which detects noise on power supply nets every circuit block, and an interruption handling circuit 601 that constitutes a unit are provided inside each unit. However, in the duplex units, any one of them has the noise detecting circuit 690 and interruption handling circuit 601 .
  • the interruption to a unit that does not have an interruption handling circuit 601 is performed via a control signal-adjusting block 602 .
  • mesh-shaped internal power supply nets are arranged in the chip 600 , and the noise detecting circuit 690 is connected with the same power supply nets as those of general logical circuits.
  • FIG. 7 shows the pipeline of instruction processing in this embodiment.
  • An instruction is executed at seven stages, that is, a stage D where the instruction is fetched and decode preparation is performed ( 710 ), a stage A where decode and address computation are performed ( 720 ), a stage T where referring translation lookaside buffer (TLB) is performed ( 730 ), a stage B where referring buffer address array (BAA) is performed ( 740 ), a stage L where loading operands on an execution unit is performed ( 750 ), and a stage E where a result is obtained by operating an arithmetic unit ( 760 ).
  • the operation of each stage is advanced in a pipeline mode.
  • An instruction begins from a and goes to k sequentially.
  • the process shifts to interruption within the cycle where the noise is detected, and a rerun is performed in the following cycle.
  • the rerun is performed on the stage ( 760 ) where the noise is detected.
  • the rerun is performed in the cycle after the next cycle.
  • the following instruction b waits on stage L ( 750 ) while performing the rerun of the instruction a, since the process cannot move from the stage L to the stage E.
  • FIG. 8 is a block diagram of instruction operation of the above-described third embodiment of the present invention.
  • a processor 800 consists of an instruction controller 810 and a plurality of logical units 820 .
  • the instruction controller 810 decodes an instruction that an instruction register 812 fetches, and generates a signal required for an instruction sequentially.
  • the logical unit 820 comprises, for example, an execution circuit block 830 , a status register 821 which stores a state of precalculation, a register 822 for interruption, which saves information required at the time of the recovery from interruption, an instruction control circuit 823 , and an interruption handling circuit 824 .
  • the execution circuit block 830 comprises a plurality of general purpose registers 831 that store the data transmitted, an execution unit 832 , and a noise detecting circuit 833 .
  • the interruption handling circuit 824 sends the signal 825 to an on-chip control signal-adjusting block 850 so as to make it possible to perform duplex comparison after the interruption, while sending an interruption signal 826 to the instruction control circuit 823 in the logical unit.
  • the instruction control circuit 823 makes the execution circuit block 830 stop the arithmetic operation, and stores information, required at the time of the recovery from the interruption, in the register 822 for interruption.
  • the required information is values of the general purpose registers 831 , status register 821 , and program counter 811 .
  • a rerun is performed in the following cycle. Saving of the required information and preparation of the rerun are performed in an interval from interruption to the start of the following cycle. Since being performed on the stage E 760 where the noise is detected as shown in FIG. 7, the rerun is performed by restoring the values of the general purpose registers 831 .
  • FIG. 9 is a timing chart showing the timing of the interruption according to the third embodiment of the present invention. In FIG. 9, regular operation and interruption will be described in order.
  • the interruption here described is not a rerun (arithmetic operation after saving and clearing the content of registers and inputting the same contents again), but is such interruption that the contents of the registers are made to be inputs to the following cycle as it is and output results are carried over to the following cycle.
  • the gates are hardly switched, and hence the noise on power supply nets, 908 caused by the switching current also becomes small. That is, the noise 908 that exceeds the error-including level of the gates is not generated.
  • the processor which consists of a plurality of logical circuit blocks or memory circuit blocks, it is possible to prevent a malfunction by performing interruption per unit even in a processor having a plurality of units therein since the processor has a power supply noise detecting circuit inside at least one circuit block and has a circuit block performing recovery processing for the above-described logical circuit blocks or memory circuit blocks through receiving a detection signal of the above-described power supply noise detecting circuit.
  • the gates hardly operate by suspending an output of the signal processing result of the above-described circuit block in the clock cycle concerned with the above-described interruption and outputting the signal processing result in the following or later cycle if a detection signal which shows that the noise on power supply nets which induces a malfunction arises is outputted from the above-described power supply noise detecting circuit. Therefore, the noise on power supply nets becomes noise that is less than the error-including level of the gates and the malfunction is corrected to the regular operation in the interruption cycle, and hence malfunction prevention is possible.
  • FIG. 10 shows a fourth embodiment of the present invention.
  • the noise in both VDD and VSS can be detected in one circuit.
  • a condenser C 1 , transistors Tr 3 , Tr 7 , and Tr 8 , and an inverter inv 5 constitute a level shift circuit 1010 .
  • Inverters inv 1 , inv 2 , and inv 3 constitute a level discriminator 1020 .
  • the level shift circuit 1010 and level discriminator 1020 together constitute a noise detector 1030 .
  • VDD 2 is a positive power supply for the level discriminator 1020 .
  • the transistors Tr 1 and Tr 2 , and inverter inv 4 constitute a detection signal holder 1040 .
  • VSS is a grand level (0V)
  • VDD 2 is VDD/2
  • a threshold voltage of inv 1 is VDD/4
  • a precharge voltage of the inv 1 input by the level shift circuit 1010 is VDD/3.
  • VDD is 1.2 V
  • VDD 2 is 0.6 V
  • the above-described threshold voltage is 0.3 V
  • the above-described precharge voltage is 0.4 V.
  • the threshold voltage of the inverter changes if noise occurs in VDD.
  • the positive power supply of the level discriminator 1020 is supplied from the power supply VDD 2 that is different from VDD and keeps a voltage with VSS constant. Hence even if noise occurs in VDD, the threshold voltage of inv 1 is fixed.
  • the operation of the detection signal holder 1040 will be described. If the reset signal reset is HIGH and noise does not occur (that is, an output of inv 3 is LOW), Tr 1 is turned ON and Tr 2 is turned OFF. Furthermore, an input of inv 4 is precharged and becomes HIGH, and hence an output signal OUT becomes LOW. If the reset signal reset is LOW, Tr 1 is turned off, but the input of inv 4 is HIGH by the precharged charges, and the output OUT is held at LOW. Then, the level discriminator 1020 operates to turn on Tr 2 when the output of inv 3 becomes HIGH, and hence the precharged charges are discharged. In consequence, the input of inv 4 becomes LOW and OUT becomes HIGH. Once noise is detected, the output OUT can be held at HIGH, and hence this embodiment can also detect glitch-like noise. If the reset is again set to be HIGH, the output OUT can be restored to LOW.
  • the detection signal holder 1040 is a dynamic circuit that becomes a precharge phase in the period of HIGH and becomes an evaluation phase in the period of LOW.
  • FIG. 11A shows operating waveforms in this embodiment at the time when noise occurs in VDD.
  • the noise of ⁇ 0.3 V occurs in VDD (VDD drops from 1.2 V to 0.9 V).
  • the DC level of the noise waveform drops to 0.4 V (N 1 ) by the level shift circuit, and the minimum value (about 0.1 V) of the noise waveform becomes lower than the threshold voltage (0.3 V) of inv 1 .
  • the noise detection output OUT becomes HIGH.
  • FIG. 11B shows operating waveforms in this embodiment at the time when noise occurs in VSS.
  • the noise of +0.3 V occurs on VSS (VSS increases from 0.0 V to 0.3 V). Since following VDD, the voltage of N 1 does not change and is nearly constant (0.4V) even if VSS changes. On the other hand, since VDD 2 and the threshold voltage of inv 1 are changed with following VSS, the threshold voltage of inv 1 goes up from 0.3 V to 0.6 V. Since the input voltage of inv 1 is relatively less than the threshold voltage, the noise detection output OUT becomes HIGH.
  • this embodiment can detect the noise on VSS as well as VDD.
  • FIG. 12 shows a fifth embodiment of the present invention.
  • a circuit in FIG. 12 is a voltage generator for the above-described level discriminator. According to this embodiment, the voltage VDD 2 -that changes with following the voltage fluctuation of VSS can be generated.
  • this voltage generator 1200 will be described. If the reset signal reset is set to be HIGH, the voltage generator 1200 becomes in a voltage-setting mode of output VDD 2 , and if the reset signal reset is set to LOW, the voltage generator 1200 becomes in a power supply mode to the above-described level discriminator.
  • the reset signal reset is set to be HIGH. At this time, it is assumed that the noise on power supply nets on VDD and VSS is sufficiently small.
  • the reset signal reset is inputted into a transistor Tr 4 through the transistor Tr 5 and inverter inv 6 , and Tr 4 and Tr 5 are turned on. In consequence, the voltage (VDD-VSS) is divided with the on-resistance ratio of Tr 4 and Tr 5 .
  • the condenser C 2 is charged with the above-described voltage divided. It is assumed that the capacity value of C 2 is sufficiently larger than the gate capacitance of the transistor Tr 6 . Tr 6 constitutes a source follower.
  • C 3 is a bypass condenser that functions in order to stabilize VDD 2 .
  • the reset signal reset is set to be LOW at the time of noise detection. Since Tr 4 and Tr 5 become off and charges charged in the gate of Tr 6 and C 2 are not discharged, a voltage between the gate of Tr 6 and VSS is kept constant. Since Tr 6 is a source follower and just slight steady state current flows, VDD 2 becomes a voltage lower than the gate voltage of Tr 6 by the threshold voltage of Tr 6 . If the threshold voltage of Tr 6 is set to be sufficiently small, VDD 2 fluctuates with following VSS when VSS fluctuates.
  • FIG. 13 is a timing chart showing the timing of the reset signal reset and a clock signal.
  • a clock is stopped before a time interval T 1 at the time of reset for the operation of the integrated circuit to be interrupted.
  • T 1 is the time interval required for the noise on power supply nets converging.
  • a time interval T 2 is an interval required for charging the gate of Tr 6 and C 2 after setting the reset signal reset to be HIGH. After a lapse time of T 2 since setting the reset signal reset to be HIGH, the reset signal reset is set to be LOW, and the clock is resumed after that.
  • the precharge of the first stage of the above-mentioned level discriminator is also performed on this timing.
  • the voltage VDD 2 and the precharge voltage of the first stage of the noise detector are not influenced by noise.
  • the gate voltage of Tr 6 and the precharge voltage of the first stage of the level discriminator may be lowered due to leakage current over the long term. Then, VDD 2 voltage is periodically reset like refresh operation in DRAM.
  • VDD 2 generating power supply that changes with following the voltage fluctuation of VSS and keeps (VDD 2 -VSS) constant can be realized. If this embodiment is combined with the fourth embodiment, it is possible to realize a noise detecting circuit that operates with a single power supply and does not require a dedicated power supply from the outside.
  • FIG. 14 A sixth embodiment of the present invention is shown in FIG. 14. This embodiment is characterized in that noise on VSS is inputted into the first stage inv 7 of the level discriminator after level shifting, and that the voltage VSS 2 that follows the fluctuation of VDD is generated.
  • a condenser C 4 , transistors Tr 11 , Tr 12 , and Tr 13 , and an inverter inv 11 constitute a level shift circuit 1410 .
  • Inverters inv 7 , inv 8 , and inv 9 constitute a level discriminator 1420 .
  • the level shift circuit 1410 and level discriminator 1420 together constitute a noise detector 1430 .
  • VSS 2 is a negative power supply for the level discriminator 1420 .
  • Transistors Tr 9 , Tr 10 , and an inverter inv 10 constitute a detection signal holder 1440 .
  • Transistors Tr 14 , Tr 15 , and Tr 16 , an inverter inv 12 , and condensers C 5 and C 6 constitute a voltage generator 1450 .
  • the above-described voltage generator 1450 generates VSS 2 so that (VDD-VSS 2 ) may become fixed. If the reset signal reset is set to be HIGH, the voltage setup of VSS 2 , precharge voltage setup of inv 7 , and reset of the noise detection result OUT are performed. If the reset signal reset is set to be LOW, the semiconductor integrated circuit becomes in a noise detectable state.
  • VSS 2 the above-described threshold holding voltage, and above-described precharge voltage to be 0.6 V, 0.9 V, and 0.8 V respectively when VDD is 1.2 V
  • noise on VDD and VSS is detectable like the above-described fourth embodiment.
  • the above-described fourth embodiment has circuit configuration on the basis of VSS, since it is possible to consider VDD as a reference according to this embodiment, there is an effect that the degree of freedom of circuit design increases. According to the present invention, there are the following effects:

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US09/946,451 2001-01-24 2001-09-06 Semiconductor integrated circuit having noise detect circuits detecting noise on power supply nets Abandoned US20020096677A1 (en)

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US11/253,833 US7339411B2 (en) 2001-01-24 2005-10-20 Semiconductor integrated circuit having noise detect circuits detecting noise on power supply nets

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Application Number Priority Date Filing Date Title
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010018752A1 (en) * 2000-02-21 2001-08-30 Matsushita Electric Industrial Co., Ltd Apparatus and method for processing information continuously even against extraneously incoming noise
US20030226054A1 (en) * 2002-04-22 2003-12-04 Hiroshi Benno Clock generation circuit and clock generation method
US20060221531A1 (en) * 2003-08-22 2006-10-05 Makoto Nagata Circuit for detecting and measuring noise in semiconductor integrated circuit
US20100039099A1 (en) * 2008-08-12 2010-02-18 Hynix Semiconductor, Inc. Power noise detecting device and power noise control device using the same
US20100327898A1 (en) * 2009-06-29 2010-12-30 Kabushiki Kaisha Nihon Micronics Probe card and inspection apparatus
DE112008001757B4 (de) * 2007-07-06 2014-07-31 Hewlett-Packard Development Company, L.P. Systeme und Verfahren zum Bestimmen einer Aktualisierungsrate eines Speichers auf der Basis von HF-Aktivitäten

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5173216B2 (ja) * 2006-04-18 2013-04-03 パナソニック株式会社 半導体集積回路システム、半導体集積回路、オペレーティングシステム及び半導体集積回路の制御方法
US7467050B2 (en) * 2006-05-30 2008-12-16 International Business Machines Corporation Method for detecting noise events in systems with time variable operating points
US7607028B2 (en) * 2006-05-30 2009-10-20 International Business Machines Corporation Mitigate power supply noise response by throttling execution units based upon voltage sensing
KR100776751B1 (ko) * 2006-06-09 2007-11-19 주식회사 하이닉스반도체 전압 공급 장치 및 방법
JP2008072045A (ja) 2006-09-15 2008-03-27 Oki Electric Ind Co Ltd 半導体集積回路
JP5011944B2 (ja) * 2006-10-18 2012-08-29 セイコーエプソン株式会社 誤動作防止回路、半導体集積回路装置および電子機器
JP5011945B2 (ja) * 2006-10-18 2012-08-29 セイコーエプソン株式会社 半導体集積回路装置および電子機器
US7720621B2 (en) * 2007-08-30 2010-05-18 International Business Machines Corporation Application of multiple voltage droop detection
US7599808B2 (en) * 2007-08-31 2009-10-06 International Business Machines Corporation Application of multiple voltage droop detection and instruction throttling instances with customized thresholds across a semiconductor chip
US7818599B2 (en) * 2007-10-09 2010-10-19 International Business Machines Corporation Statistical switched capacitor droop sensor for application in power distribution noise mitigation
JP5051112B2 (ja) * 2008-12-05 2012-10-17 富士通株式会社 電圧変動量算出方法及びシステム並びにコンデンサ実装形態決定方法及びシステム
JP5750829B2 (ja) * 2010-03-19 2015-07-22 富士通セミコンダクター株式会社 半導体装置の試験方法
US9070776B2 (en) 2011-04-15 2015-06-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
KR101776329B1 (ko) * 2011-11-25 2017-09-08 현대자동차주식회사 접근권한코드를 이용한 디바이스 보호 시스템 및 그 보호 방법
KR101446762B1 (ko) 2013-06-26 2014-10-06 전재현 화장품 용기
KR101643456B1 (ko) * 2014-02-14 2016-07-28 주식회사 엘지생활건강 화장품 용기
KR102660729B1 (ko) 2016-10-28 2024-04-26 삼성전자주식회사 전원 잡음을 검출하는 불휘발성 메모리 장치 및 그것의 동작 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118315A (en) * 1992-12-22 2000-09-12 Sgs-Thomson Microelectronics S.A. Power-on-reset circuit providing protection against power supply interruptions
US20010018752A1 (en) * 2000-02-21 2001-08-30 Matsushita Electric Industrial Co., Ltd Apparatus and method for processing information continuously even against extraneously incoming noise
US6509768B2 (en) * 2000-01-28 2003-01-21 Stmicroelectronics S.R.L. Low-consumption power-on reset circuit for semiconductor memories

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0973400A (ja) 1995-09-05 1997-03-18 Mitsubishi Electric Corp 半導体集積回路
JP3608361B2 (ja) 1997-12-26 2005-01-12 株式会社日立製作所 低ノイズ半導体集積回路装置
JP2001125690A (ja) * 1999-10-26 2001-05-11 Mitsubishi Electric Corp マイクロコンピュータの誤動作防止装置及びマイクロコンピュータの誤動作防止方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118315A (en) * 1992-12-22 2000-09-12 Sgs-Thomson Microelectronics S.A. Power-on-reset circuit providing protection against power supply interruptions
US6509768B2 (en) * 2000-01-28 2003-01-21 Stmicroelectronics S.R.L. Low-consumption power-on reset circuit for semiconductor memories
US20010018752A1 (en) * 2000-02-21 2001-08-30 Matsushita Electric Industrial Co., Ltd Apparatus and method for processing information continuously even against extraneously incoming noise
US6721903B2 (en) * 2000-02-21 2004-04-13 Matsushita Electric Industrial Co., Ltd. Apparatus and method for processing information continuously even against extraneously incoming noise

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010018752A1 (en) * 2000-02-21 2001-08-30 Matsushita Electric Industrial Co., Ltd Apparatus and method for processing information continuously even against extraneously incoming noise
US6721903B2 (en) * 2000-02-21 2004-04-13 Matsushita Electric Industrial Co., Ltd. Apparatus and method for processing information continuously even against extraneously incoming noise
US20030226054A1 (en) * 2002-04-22 2003-12-04 Hiroshi Benno Clock generation circuit and clock generation method
US20060221531A1 (en) * 2003-08-22 2006-10-05 Makoto Nagata Circuit for detecting and measuring noise in semiconductor integrated circuit
EP1662569A4 (de) * 2003-08-22 2010-05-05 New Ind Res Organization Schaltung zum feststellen und messen von geräuschen in integrierten halbleiterschaltungen
DE112008001757B4 (de) * 2007-07-06 2014-07-31 Hewlett-Packard Development Company, L.P. Systeme und Verfahren zum Bestimmen einer Aktualisierungsrate eines Speichers auf der Basis von HF-Aktivitäten
US20100039099A1 (en) * 2008-08-12 2010-02-18 Hynix Semiconductor, Inc. Power noise detecting device and power noise control device using the same
US7952364B2 (en) * 2008-08-12 2011-05-31 Hynix Semiconductor Inc. Power noise detecting device and power noise control device using the same
US20100327898A1 (en) * 2009-06-29 2010-12-30 Kabushiki Kaisha Nihon Micronics Probe card and inspection apparatus
US8736292B2 (en) * 2009-06-29 2014-05-27 Kabushiki Kaisha Nihon Micronics Probe card and inspection apparatus

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US20060033559A1 (en) 2006-02-16

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