US20020056700A1 - Method and system for manufacturing semiconductor device - Google Patents

Method and system for manufacturing semiconductor device Download PDF

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Publication number
US20020056700A1
US20020056700A1 US09/826,038 US82603801A US2002056700A1 US 20020056700 A1 US20020056700 A1 US 20020056700A1 US 82603801 A US82603801 A US 82603801A US 2002056700 A1 US2002056700 A1 US 2002056700A1
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Prior art keywords
processing
film
measurement value
semiconductor device
etching
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Toshiaki Ohmori
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Renesas Technology Corp
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Mitsubishi Electric Corp
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Publication of US20020056700A1 publication Critical patent/US20020056700A1/en
Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MITSUBISHI DENKI KABUSHIKI KAISHA
Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MITSUBISHI DENKI KABUSHIKI KAISHA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a method and system for manufacturing a semiconductor device. More particularly, the present invention relates to a manufacturing method and system effective for increasing the yield of a semiconductor device.
  • Japanese Patent Application Laid-Open No. H7-29958 describes a technique of performing predetermined inspection before and after processing of a wafer, thereby automatically changing wafer processing requirements on the basis of an inspection result.
  • These related-art techniques are to feed back the result of inspection of a wafer before and after predetermined processing to requirements for the processing.
  • the related-art techniques are to correct processing requirements for a certain process, in accordance with the state of the wafer which has been subjected to the process. In this case, the result of inspection of a certain wafer is not reflected in the processing of the wafer.
  • the related-art techniques encounter a problem of processing errors of respective processes being accumulated in respective wafers.
  • the present invention has been conceived to solve such a problem and is aimed at providing a manufacturing method which enables high-yield manufacture of a semiconductor device of stable quality, by means of reflecting the state of a wafer in the requirements for processing the wafer through use of the feedforward technique.
  • the present invention is also aimed at providing a manufacturing system which enables high-yield manufacture of a semiconductor device of stable quality, by means of reflecting the state of a wafer in requirements for processing the wafer through use of the feedforward technique.
  • the above objects of the present invention are achieved by a method of manufacturing a semiconductor device described below.
  • the method includes a first step of acquiring a measurement value pertaining to a wafer to be subjected to a predetermined processing process.
  • the method also includes a second step of determining processing requirements for the predetermined processing process on the basis of the measurement value.
  • the method further includes third step of performing the predetermined processing process in accordance with the processing requirements determined in the second step.
  • the above objects of the present invention are achieved by a method of manufacturing a semiconductor device described below.
  • the method includes a step of wet etching a predetermined film to be processed.
  • the method also includes a step of counting a time which has elapsed since replacement of a chemical to be used for the wet etching.
  • the method further includes a step of determining processing requirements for the wet etching on the basis of the elapsed time. The wet etching is performed in accordance with the processing requirements.
  • the above objects of the present invention are achieved by a semiconductor device manufacturing system which performs a plurality of processing processes.
  • the system includes a measurement apparatus for acquiring a predetermined measurement value pertaining to a wafer to be subjected to a predetermined processing process.
  • the system also includes a recipe determination section for determining processing requirements for the predetermined processing process on the basis of the measurement value.
  • the system further includes a processing apparatus for performing the predetermined processing process in accordance with the processing requirements determined by the recipe determination section.
  • FIG. 1 is a block diagram for describing a construction of a system for manufacturing a semiconductor device according to a first embodiment of the present invention
  • FIG. 2A is a cross sectional view for describing a manufacturing method according to the first embodiment of the present invention.
  • FIG. 2B is a flowchart for describing a manufacturing method according to the first embodiment of the present invention.
  • FIG. 3A is a cross sectional view for describing a manufacturing method according to a second embodiment of the present invention.
  • FIG. 3B is a flowchart for describing a manufacturing method according to a second embodiment of the present invention.
  • FIG. 4A is a cross sectional view for describing a manufacturing method according to a third embodiment of the present invention.
  • FIG. 4B is a flowchart for describing a manufacturing method according to a third embodiment of the present invention.
  • FIG. 5A is a cross sectional view for describing a manufacturing method according to a forth embodiment of the present invention.
  • FIG. 5B is a flowchart for describing a manufacturing method according to a fourth embodiment of the present invention.
  • FIG. 6 is a graph showing a relationship between an etching rate and an impurity concentration
  • FIGS. 7A through 7D are cross sectional views for describing a manufacturing method according to a fifth embodiment of the present invention.
  • FIG. 7E is a flowchart for describing a manufacturing method according to a fifth embodiment of the present invention.
  • FIG. 8 is a block diagram for describing a construction of a system for manufacturing a semiconductor device according to a sixth embodiment of the present invention.
  • FIG. 1 is a block diagram showing the construction of a system for manufacturing a semiconductor device according to a first embodiment of the present invention.
  • the manufacturing system according to the present embodiment comprises a main computer 10 , a measurement apparatus 12 , and a processing apparatus 14 .
  • the main computer 10 , the measurement apparatus 12 , and the processing apparatus 14 are interconnected by way of a communications channel so as to effect mutual communication of information.
  • the processing apparatus 14 is to perform various processing operations to be performed during the course of manufacture of a semiconductor device.
  • the processing apparatus 14 is constituted of, for example, a film-growth machine for forming a predetermined film on a wafer, and a dry or wet etching machine for etching the film formed on the wafer. Although a plurality of pieces of processing apparatus 14 are shown in FIG. 1, the manufacturing system according to the present embodiment may comprise only one processing apparatus 14 .
  • the measurement apparatus 12 is to subject a wafer to a predetermined inspection during the course of manufacture of a semiconductor device.
  • the measurement apparatus 12 is constituted of, for example, a film thickness measurement machine for measuring the thickness of a film formed on the surface of a wafer; an impurity measurement machine for measuring the concentration of impurities contained in the film formed on the surface of the wafer; a size measurement machine for measuring the size of a pattern formed on the surface of a wafer; or an interlayer oxide film measurement machine for measuring an interlayer oxide film formed on the surface of the wafer.
  • FIG. 1 shows only one measurement machine 12 , a plurality of measurement machines 12 may be provided within the manufacturing system according to the present embodiment.
  • the main computer 10 is equipped with a measurement value receiving section 16 for receiving a value measured by the measurement apparatus 12 .
  • the measurement value received by the measurement value receiving section 16 is stored into measurement value memory 20 along with an ID assigned to a wafer which is an object of measurement, by means of a measurement value memorizing section 18 .
  • the main computer 10 is also equipped with an ID receiving section 22 .
  • the processing apparatus 14 sends to the main computer 10 the ID assigned to a wafer which is an object of processing.
  • the processing apparatus 14 that has transmitted an ID will be referred to specifically as an object-of-control processing apparatus 14 .
  • the ID receiving section 22 receives the ID transmitted by the object-of-control processing apparatus 14 and transfers the thus-received ID to a recipe determination section.
  • the recipe determination section 24 reads from the measurement value memory 20 the measurement value pertaining to the wafer to be processed by the object-of-control processing apparatus 14 ; more particularly, a measurement value measured immediately before the object-of-control processing apparatus 14 performs processing.
  • Requirements which are used by the object-of-control processing apparatus 14 to process a wafer should be set appropriately in accordance with the state of the wafer at a point in time at which the processing is commenced. More specifically, the requirements which are used by the object-of-control processing apparatus 14 to process a wafer should be set appropriately in accordance with a measured value pertaining to the wafer measured immediately before the processing.
  • a recipe memory 26 provided to the main computer 10 stores optimal processing requirements for the object-of-control processing apparatus 14 that have been determined beforehand on the basis of a relation with the above mentioned measured value.
  • the recipe determination section 24 described above reads out a measured value from the measurement value memory 20 so as to reads out optimal processing requirements from the recipe memory 26 based on the measured value.
  • the thus-read optimal processing requirements are sent to the object-of-control processing apparatus 14 by means of a recipe transmission section 28 .
  • the object-of-control processing apparatus 14 processes the wafer according to the optimal requirements thus transmitted from the main computer 10 .
  • the manufacturing system according to the present embodiment can reflect the state of the wafer measured by the measurement apparatus 12 in the processing requirements for the object-of-control processing apparatus 14 , by means of the feedforward technique. More specifically, the manufacturing system according to the present embodiment can reflect the state of a wafer measured by the measurement apparatus 12 in requirements used for processing the wafer itself. Therefore, the manufacturing system according to the present embodiment enables high-yield manufacture of a semiconductor device of stable quality without errors of respective processes being accumulated in a wafer.
  • the manufacturing system according to the present embodiment is aimed at accurately controlling a step difference between the surface of an isolation oxide film to be embedded in a trench and the surface of a silicon substrate, during the course of manufacture of an element isolation structure through use of a trench structure. During the course of manufacture of an element isolation structure using a trench isolation structure, processing described below is performed.
  • a silicon oxide film 35 , a polysilicon film 34 , and a silicon nitride film 32 are formed on the surface of a silicon substrate 31 .
  • the silicon nitride film 32 is patterned in accordance with the geometry of a trench to be formed.
  • the silicon substrate 31 is subjected to dry etching while the thus-patterned silicon nitride film 32 is used as a mask, whereby a trench structure is formed in the silicon substrate 31 .
  • An oxide film is deposited on the entire surface of the silicon substrate 31 such that the trench structure is filled with the oxide film, by means of chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • the oxide film overflowing the trench structure is removed by means of chemical-and-mechanical polishing (CMP), to thereby remain the oxide film within only the trench structure for forming an isolation oxide film 33 .
  • CMP chemical-and-mechanical polishing
  • CMP is followed by etching of the isolation oxide film 33 , etching of the silicon nitride film 32 , and etching of the polysilicon film 34 , in the sequence given.
  • etching of the isolation oxide film 33 is performed in accordance with default requirements, difficult is encountered in accurately forming a step difference between the surface of the isolation oxide film 33 and the surface of the silicon substrate 31 such that the step assumes a desired final value.
  • the thickness of the isolation oxide film 33 is measured.
  • the resultant measurement value is reflected in the requirements for etching the isolation oxide film 33 , by means of the feedforward technique.
  • a film thickness measurement apparatus used for measuring the thickness of the isolation oxide film 33 after CMP corresponds to the measurement apparatus 12 shown in FIG. 1.
  • an etching machine used for etching the isolation oxide film 33 corresponds to the object-of-control processing apparatus 14 .
  • the manufacturing system measures the thickness of the isolation oxide film 33 formed on the wafer.
  • the resultant measurement value is transmitted to the main computer 10 , and the thus-transmitted measurement value is recorded in the measurement value memory 20 along with the ID assigned to the wafer.
  • the etching machine requests the main computer 10 to transmit optimal requirements.
  • processing requirements for the etching machine are set to the optimal requirements determined by the recipe determination section 24 .
  • the isolation oxide film 33 is etched according to the optimal requirements.
  • the manufacturing method according to the present embodiment enables a step difference between the surface of the isolation oxide film 33 and the surface of the silicon substrate 31 to be accurately controlled to a desired value at all times finally, regardless of variations in the amount of abrasion attained in the course of CMP. Accordingly, the manufacturing method and system according to the present embodiment enable high-yield manufacture of a semiconductor device of stable quality.
  • an ID is set on a per-wafer basis, and requirements for etching the isolation oxide film 33 are set on a per-wafer basis.
  • the present invention is not limited to this embodiment. Specifically, an ID may be set on a per-lot basis, and etching requirements may be set on a per-lot basis.
  • processing requirements are set within the main computer 10 , and the requirements are sent from the main computer 10 to the etching apparatus (the object-of-control apparatus 14 ).
  • the present invention is not limited to this embodiment. Specifically, a plurality of processing requirements may be stored beforehand in the etching machine, and the main computer 10 may select optimal requirements from the requirements.
  • FIGS. 3A and 3B A second embodiment of the present invention will now be described by reference to FIGS. 3A and 3B.
  • FIG. 3A shows the wafer in which the silicon nitride film 32 has been removed from the polysilicon film 34 .
  • the measurement apparatus 12 measures the thickness of the isolation oxide film 33 .
  • the thus-measured thickness value is transmitted to the main computer 10 in the same manner as in the first embodiment, and the value is recorded along with an ID assigned to the wafer.
  • the isolation oxide film 33 is etched from the wafer. At this time, processing requirements for the etching machine (corresponding to the object-of -control processing apparatus 14 ) are set to optimal requirements by the main computer 10 , as in the case of the first embodiment.
  • the manufacturing method and system according to the present embodiment By means of the manufacturing method and system according to the present embodiment, variations in the thickness of the isolation oxide film 33 stemming from CMP and variations in the thickness of the isolation oxide film stemming from removal of the silicon nitride film 32 can be reflected in the requirements for etching the isolation oxide film 33 .
  • the manufacturing method and system according to the present embodiment enable more accurate control of the step between the surface of the isolation oxide film 33 and the surface of the silicon substrate 31 to a desired value than that attained in the first embodiment.
  • FIGS. 4A and 4B A third embodiment of the present invention will now be described by reference to FIGS. 4A and 4B.
  • the third embodiment is aimed at accurately controlling the thickness of an interlayer oxide film during an etching process intended for smoothing the interlayer oxide film of a semiconductor device.
  • processing is effected in the following manner during the course of manufacture of a semiconductor device.
  • various interconnection elements such as a gate electrode 38 of a transistor and a capacitor electrode 40 of a memory cell are formed on the silicon substrate 31 .
  • An interconnection oxide film 42 is deposited on the entire surface of the silicon substrate 31 so as to cover all the interconnection elements, by means of, for example, the CVD technique. At this time, on the surface of the interlayer oxide film 42 there are formed steps difference ascribable to presence/absence of the interconnection elements and structural dissimilarities between the interconnection elements.
  • an unillustrated upper interconnection is formed on the interlayer oxide film 42 .
  • the step differences formed on the surface of the interlayer oxide film 42 would induce patterning failures at the time of formation of an upper interconnection.
  • a resist film 44 is formed so as to cover recessed areas of the interlayer oxide film 42 , then the interlayer oxide film 42 is etched back while the resist film 44 is taken as a mask, before formation of an upper interconnection.
  • the thickness of the interlayer oxide film 42 is measured before a resist film 44 is formed by means of photolithography.
  • the resultantly-measured value is reflected in the requirements for etching back the interlayer oxide film 42 , by means of the feedforward technique.
  • a film thickness measurement apparatus for measuring the thickness of the interlayer oxide film 42 after deposition thereof corresponds to the measurement apparatus 12 shown in FIG. 1.
  • an etching machine used for etching back the interlayer oxide film 42 corresponds to the object-of-control processing apparatus 14 .
  • a film thickness measurement apparatus (corresponding to the measurement apparatus 12 ) measures the thickness of the interlayer oxide film 42 immediately after deposition thereof on a wafer.
  • the resultantly-measured value is transmitted to the main computer 10 , and the value is recorded in the measurement value memory 20 along with an ID assigned to the thus-measured wafer.
  • the etching machine (corresponding to the object-of-control apparatus 14 ) requests the main computer 10 to transmit optimal requirements.
  • the recipe determination section 24 of the main computer 10 sets as processing requirements for the etching machine the optimal requirements, which are determined on the basis of the thickness of the interlayer oxide film 42 .
  • the thickness of the interlayer oxide film 42 can be made uniform to high accuracy before formation of an upper interconnection.
  • the manufacturing method and system according to the present embodiment enable effective prevention of patterning failures in an upper interconnection and high-yield manufacture of a semiconductor device of stable quality.
  • an ID is set on a per-wafer basis, and requirements for etching the interlayer oxide film 42 are also set on a per-wafer basis.
  • the present invention is not limited to this embodiment. Specifically, an ID may be set on a per-lot basis, and etching requirements may be set on a per-lot basis.
  • processing requirements are set within the main computer 10 , and the thus-set processing requirements are transmitted from the main computer 10 to the etching machine (corresponding to the object-of-control processing machine 14 ).
  • the present invention is not limited to this embodiment. More specifically, a plurality of processing requirements may be stored beforehand in the etching machine, and the main computer 10 may select optimal requirements from the requirements.
  • FIGS. 5A and 5B A fourth embodiment of the present invention will now be described by reference to FIGS. 5A and 5B.
  • the present embodiment is aimed at accurately controlling the thickness of an interlayer oxide film during an etching process intended for smoothing the interlayer oxide film of a semiconductor device, as in the case of the third embodiment.
  • the following description pertains to the difference between the third and fourth embodiments.
  • an oxide film containing impurities, such as B or P is used for the interlayer oxide film 42 .
  • impurities such as B or P
  • ease of smoothing can be enhanced. Accordingly, under the manufacturing method according to the present embodiment, the interlayer oxide film 42 can be smoothed more readily than in the third embodiment.
  • FIG. 6 is a graph showing the influence of the concentration of P in an oxide film on a rate at which the oxide film is etched, during a wet etching operation using buffered hydrofluoric acid (i.e., a mixture consisting of HF 4 F and HF).
  • buffered hydrofluoric acid i.e., a mixture consisting of HF 4 F and HF.
  • the concentration of impurities contained in the interlayer oxide film 42 is one of the primary factors determining the thickness of the interlayer oxide film 42 still remaining after the etching process.
  • the concentration of impurities contained in the interlayer oxide film 42 is measured after deposition of the interlayer oxide film 42 and before the formation of the resist film 44 by means of photolithography.
  • the resultantly-measured value is reflected in the requirements for etching back the interlayer oxide film 42 , by means of the feedforward technique.
  • an impurity concentration measurement apparatus used for measuring the concentration of impurities contained in the interlayer oxide film 42 after deposition thereof corresponds to the measurement apparatus 12 shown in FIG. 1.
  • the etching machine used for etching back the interlayer oxide film 42 corresponds to the object-of-control processing apparatus 14 .
  • the manufacturing system measures the concentration of impurities contained in the interlayer oxide film 42 using the impurity measurement apparatus (i.e., the measurement apparatus 12 ) immediately after the interlayer oxide film 42 is deposited on the wafer.
  • the resultantly-measured value is transmitted to the main computer 10 , and the value is recorded in the measurement value memory 20 along with the ID assigned to the thus-measured wafer.
  • the etching machine i.e., the object-of-control processing apparatus 14
  • the recipe determination section 24 of the main computer 10 sets as processing requirements for the etching machine the optimal requirements, which are determined on the basis of the concentration of impurity in the interlayer oxide film 42 . Subsequently, the interlayer oxide film 42 is etched back under the optimal requirements.
  • the thickness of the interlayer oxide film 42 can be made uniform to high accuracy before formation of an upper interconnection.
  • the manufacturing method and system according to the present embodiment enable prevention of patterning failures in an upper interconnection, and high-yield manufacture of a semiconductor device of stable quality.
  • an ID is set on a per-wafer basis, and requirements for etching the interlayer oxide film 42 are also set on a per-wafer basis.
  • the present invention is not limited to this embodiment. Specifically, an ID may be set on a per-lot basis, and etching requirements may be set on a per-lot basis.
  • processing requirements are set within the main computer 10 , and the thus-set processing requirements are transmitted from the main computer 10 to the etching machine (corresponding to the object-of-control processing machine 14 ).
  • the present invention is not limited to this embodiment. More specifically, a plurality of processing requirements may be stored beforehand in the etching machine, and the main computer 10 may select optimal requirements from the requirements.
  • the requirements for etching the isolation oxide film 33 or the interlayer oxide film 42 are determined on the basis of the thickness of the isolation oxide film 33 or the interlayer oxide film 42 .
  • the requirements for etching the interlayer oxide film 42 are determined on the basis of the concentration of impurities contained in the interlayer oxide film 42 .
  • data used for determining the requirements for etching the isolation oxide film 33 or the interlayer oxide film 42 are not limited to the film thickness or the concentration of impurities.
  • the requirements for etching the isolation oxide film 33 or the interlayer oxide film 42 may be determined on the basis of the refractive index of the films.
  • FIGS. 7A through 7E A fifth embodiment of the present invention will now be described by reference to FIGS. 7A through 7E.
  • the fifth embodiment is aimed at accurate formation of a miniaturized interconnection pattern.
  • the processing described below is performed during the course of manufacture of a semiconductor device.
  • an interconnection layer 46 and an oxide film 48 are formed on the silicon substrate 31 .
  • the interconnection layer 46 is formed from, for example, doped polysilicon or metal material such as tungsten or tungsten silicide.
  • a resist film 50 which is slightly larger than a miniaturized pattern to be formed is patterned on the oxide film 48 by means of photolithography.
  • the oxide film 48 is dry-etched while the resist film 50 is taken as a mask. Subsequently, the resist film 50 still remaining on the oxide film 48 is removed by means of oxygen plasma processing. As a result, there is formed the wafer, as shown in FIG. 7B.
  • the outer dimension of the oxide film 48 is reduced by means of wet etching.
  • the oxide film 48 thus reduced turns into a miniaturized pattern which cannot be formed by means of dry etching.
  • the interconnection layer 46 is dry-etched while the reduced oxide film 48 is taken as a mask. Consequently, an interconnection 52 having a miniaturized pattern is formed on the silicon substrate 31 .
  • the principal reasons for causing dimensional errors in the interconnection 52 formed through the foregoing procedures are (1) dimensional errors in the resist film 50 formed by means of photolithography and (2) dimensional errors in the oxide film 48 caused by side etching, which etching would arise during the dry etching process.
  • dimensional errors in the resist film 50 and those in the oxide film 48 are corrected by means of the technique to be described below.
  • the resist film 50 is formed through use of photolithography at first. Then, the oxide film 48 is dry-etched using the resist film 50 as a mask. After removing the resist film 50 , the dimension of the patterned oxide film 48 is measured. The resultantly-measured value is reflected in the requirements for wet-etching the oxide film 48 by means of the feedforward technique.
  • the dimension measurement apparatus used for measuring the dimension of the oxide film 12 after removal of the resist film 50 corresponds to the measurement apparatus 12 . Further, the wet-etching apparatus used for wet-etching the oxide film 12 corresponds to the object-of-control processing apparatus 14 .
  • the manufacturing system measures the dimension of the oxide film 48 using the dimension measurement apparatus (i.e., the measurement apparatus 12 ) before the oxide film 48 is subjected to wet etching.
  • the resultantly-measured value is transmitted to the main computer 10 , and the value is recorded in the measurement value memory 20 along with the ID assigned to the thus-measured wafer.
  • the wet etching apparatus i.e., the object-of-control processing apparatus 14
  • the recipe determination section 24 of the main computer 10 sets the optimal requirements, which are determined on the basis of the dimension of the oxide film 48 , as processing requirements for the etching machine. Subsequently, the oxide film 48 is wet-etched under the optimal requirements.
  • the manufacturing method and system according to the present embodiment enable considerably-accurate patterning of a minute interconnection 52 and high-yield manufacture of a semiconductor device of stable quality.
  • an ID is set on a per-wafer basis, and requirements for etching the oxide film 12 are also set on a per-wafer basis.
  • the present invention is not limited to this embodiment. Specifically, an ID may be set on a per-lot basis, and etching requirements may be set on a per-lot basis.
  • processing requirements are set within the main computer 10 , and the thus-set processing requirements are transmitted from the main computer 10 to the etching machine (corresponding to the object-of-control processing machine 14 ).
  • the present invention is not limited to this embodiment. More specifically, a plurality of processing requirements may be stored beforehand in the etching machine, and the main computer 10 may select optimal requirements from the requirements.
  • FIG. 8 is a block diagram for describing the characteristic part of the manufacturing system according to the present embodiment.
  • the manufacturing system according to the present embodiment further comprises a recipe correction section 54 and an elapsed-time management section 56 .
  • the recipe correction section 54 and the elapsed-time management section 56 can be disposed within the main computer 10 or within the wet etching machine (i.e., within the processing apparatus 14 ).
  • the elapsed-time management section 56 is a unit for counting the time which has elapsed since replacement of a chemical stored in the wet etching machine with a fresh chemical.
  • the recipe correction section 54 is a unit for correcting the basic recipe for wet etching in accordance with the elapsed time.
  • a wet etching chemical deteriorates with elapse of time.
  • an etch rate of wet etching changes in accordance with the deterioration of the chemical. Therefore, it is effective for accurately etching the oxide film 48 by means of wet etching to correct wet-etching requirements in accordance with the time which has elapsed since replacement of the chemical.
  • wet-etching requirements can be corrected on the basis of the dimension of the oxide film 48 which has been dry-etched. Further, wet-etching requirements can be corrected in accordance with the time which has elapsed since replacement of a chemical.
  • the manufacturing system and method according to the present embodiment enables the interconnection 52 to be patterned more accurately than in the fifth embodiment.
  • the sixth embodiment employs two techniques in combination; that is, the technique of reflecting the dimension of the dry-etched oxide film 48 in the requirements for wet etching the oxide film 48 , by means of the feedforward technique; and the technique of reflecting the time which has elapsed since replacement of the chemical in the wet-etching requirements.
  • the present invention is not limited to this embodiment. More specifically, the technique of correcting the wet-etching requirements in accordance with the time which has elapsed since replacement of the chemical may be used solely in isolation from the technique of correcting the wet-etching requirements in accordance with the dimension of the oxide film 48 .
  • requirements for only etching are corrected by means of the feedforward technique.
  • Processing which may be corrected by means of the feedforward technique is not limited to the above-described technique.
  • film-growth requirements or CMP requirements may be corrected by means of the feedforward technique.
  • the state of a wafer which is an object of processing can be reflected in the requirements for processing the wafer, by means of the feedforward technique.
  • the present invention enables high-yield manufacture of a semiconductor device of stable quality.
  • the physical quantity of a film to be processed can be reflected in the requirements for etching the film. Accordingly, the present invention enables accurate etching of the film.
  • the thickness of a film to be processed can be reflected in etching requirements. Accordingly, the present invention enables accurate etching of the film without regard to variations in the thickness of the film.
  • the concentration of impurities contained in a film to be processed can be reflected in etching requirements.
  • the present invention enables accurate etching of the film without regard to a difference in etch rate due to a difference in concentration of impurities.
  • the refractive index of a film to be processed can be reflected in etching requirements.
  • the present invention enables accurate etching of the film without regard to a difference in etch rate due to a difference in refractive index.
  • the dimension of a film to be processed can be reflected in etching requirements.
  • the present invention enables accurate miniaturization of a film to a desired dimension without regard to the dimension of the film at a point in time at which etching of the film is commenced.
  • processing requirements according with a measurement value are determined within the main computer, and the processing requirements can be set in a processing apparatus.
  • processing requirements according with a measurement value can be determined within a processing apparatus.
  • wet-etching requirements can be corrected in accordance with the state of a chemical. Therefore, the present invention enables accurate wet-etching of a film to be processed at all times, without regard to deterioration of the chemical.

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US09/826,038 2000-11-16 2001-04-05 Method and system for manufacturing semiconductor device Abandoned US20020056700A1 (en)

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Cited By (14)

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WO2004044974A3 (en) * 2002-11-12 2004-06-17 Applied Materials Inc Method and apparatus employing integrated metrology for improved dielectric etch efficiency
US20050048800A1 (en) * 2003-07-31 2005-03-03 Wagener Thomas J. Controlled growth of highly uniform, oxide layers, especially ultrathin layers
US20050072625A1 (en) * 2003-09-11 2005-04-07 Christenson Kurt K. Acoustic diffusers for acoustic field uniformity
US20050098194A1 (en) * 2003-09-11 2005-05-12 Christenson Kurt K. Semiconductor wafer immersion systems and treatments using modulated acoustic energy
EP1492153A3 (en) * 2003-06-18 2006-05-10 Applied Materials, Inc. Method and system for monitoring an etch process
US20060202281A1 (en) * 2005-02-28 2006-09-14 Seiko Epson Corporation Semiconductor device
US20070284335A1 (en) * 2006-03-30 2007-12-13 Hiroshi Tsujimoto Etching method and etching apparatus
US20080081384A1 (en) * 2006-09-29 2008-04-03 Fujitsu Limited Semiconductor device fabrication method and semiconductor device fabrication system
EP1546876A4 (en) * 2002-08-28 2008-11-19 Tokyo Electron Ltd METHOD AND SYSTEM FOR DYNAMICALLY MODELING AND RECOVERY OPTIMIZATION OF SEMICONDUCTOR ENGRAVING PROCESS
US20080319709A1 (en) * 2007-06-21 2008-12-25 Hitachi, Ltd. Dimension measuring apparatus and dimension measuring method for semiconductor device
US7596421B2 (en) 2005-06-21 2009-09-29 Kabushik Kaisha Toshiba Process control system, process control method, and method of manufacturing electronic apparatus
CN102683195A (zh) * 2011-03-11 2012-09-19 索尼公司 制造半导体装置的装置和方法及制造电子设备的方法
US20120326076A1 (en) * 2011-06-27 2012-12-27 International Business Machines Corporation Tool for manufacturing semiconductor structures and method of use
CN104409348A (zh) * 2014-11-10 2015-03-11 成都士兰半导体制造有限公司 沟槽器件的制作方法

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US6842661B2 (en) * 2002-09-30 2005-01-11 Advanced Micro Devices, Inc. Process control at an interconnect level
JP2004319574A (ja) * 2003-04-11 2004-11-11 Trecenti Technologies Inc 半導体装置の製造方法、半導体製造装置の自動運転方法および自動運転システム、並びにｃｍｐ装置の自動運転方法
JP2006245036A (ja) * 2005-02-28 2006-09-14 Seiko Epson Corp 素子分離層の形成方法及び電子デバイスの製造方法、ｃｍｐ装置
JP4990548B2 (ja) 2006-04-07 2012-08-01 株式会社日立製作所 半導体装置の製造方法
JP5401797B2 (ja) 2008-02-06 2014-01-29 富士通セミコンダクター株式会社 半導体装置の製造方法及び半導体装置製造システム
JP2010087300A (ja) * 2008-09-30 2010-04-15 Toshiba Corp 半導体装置の製造方法
DE112017007540T5 (de) * 2017-05-15 2020-01-23 Mitsubishi Electric Corporation Verfahren zum Herstellen einer Halbleitervorrichtung

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JP2867982B2 (ja) * 1996-11-29 1999-03-10 日本電気株式会社 半導体装置の製造装置
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KR100382021B1 (ko) * 2000-02-03 2003-04-26 가부시끼가이샤 도시바 반도체 장치 제조 방법, 반도체 장치 제조 지원 시스템, 및 반도체 장치 제조 시스템

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Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1546876A4 (en) * 2002-08-28 2008-11-19 Tokyo Electron Ltd METHOD AND SYSTEM FOR DYNAMICALLY MODELING AND RECOVERY OPTIMIZATION OF SEMICONDUCTOR ENGRAVING PROCESS
WO2004044974A3 (en) * 2002-11-12 2004-06-17 Applied Materials Inc Method and apparatus employing integrated metrology for improved dielectric etch efficiency
CN100349273C (zh) * 2002-11-12 2007-11-14 应用材料股份有限公司 采用整合测量以增进介电质蚀刻效率的方法和设备
US8257546B2 (en) 2003-04-11 2012-09-04 Applied Materials, Inc. Method and system for monitoring an etch process
CN1319141C (zh) * 2003-06-18 2007-05-30 应用材料有限公司 监测方法和系统以及原位测量工具
EP1492153A3 (en) * 2003-06-18 2006-05-10 Applied Materials, Inc. Method and system for monitoring an etch process
US7235495B2 (en) 2003-07-31 2007-06-26 Fsi International, Inc. Controlled growth of highly uniform, oxide layers, especially ultrathin layers
US20070218668A1 (en) * 2003-07-31 2007-09-20 Wagener Thomas J Controlled growth of highly uniform, oxide layers, especially ultrathin layers
WO2005013349A3 (en) * 2003-07-31 2005-05-12 Fsi Int Inc Controlled growth of highly uniform, oxide layers, especially ultrathin layers
US20050048800A1 (en) * 2003-07-31 2005-03-03 Wagener Thomas J. Controlled growth of highly uniform, oxide layers, especially ultrathin layers
US20050098194A1 (en) * 2003-09-11 2005-05-12 Christenson Kurt K. Semiconductor wafer immersion systems and treatments using modulated acoustic energy
US20050072625A1 (en) * 2003-09-11 2005-04-07 Christenson Kurt K. Acoustic diffusers for acoustic field uniformity
US20060202281A1 (en) * 2005-02-28 2006-09-14 Seiko Epson Corporation Semiconductor device
US20080150039A1 (en) * 2005-02-28 2008-06-26 Hiroki Aisawa Semiconductor device
US7831330B2 (en) 2005-06-21 2010-11-09 Kabushiki Kaisha Toshiba Process control system, process control method, and method of manufacturing electronic apparatus
US7596421B2 (en) 2005-06-21 2009-09-29 Kabushik Kaisha Toshiba Process control system, process control method, and method of manufacturing electronic apparatus
US20090276078A1 (en) * 2005-06-21 2009-11-05 Kabushiki Kaisha Toshiba Process control system, process control method, and method of manufacturing electronic apparatus
US20070284335A1 (en) * 2006-03-30 2007-12-13 Hiroshi Tsujimoto Etching method and etching apparatus
US8070972B2 (en) * 2006-03-30 2011-12-06 Tokyo Electron Limited Etching method and etching apparatus
US20080081384A1 (en) * 2006-09-29 2008-04-03 Fujitsu Limited Semiconductor device fabrication method and semiconductor device fabrication system
US7947567B2 (en) * 2006-09-29 2011-05-24 Fujitsu Semiconductor Limited Method of fabricating a semiconductor device with reduced oxide film variation
US7720632B2 (en) 2007-06-21 2010-05-18 Hitachi, Ltd. Dimension measuring apparatus and dimension measuring method for semiconductor device
US20080319709A1 (en) * 2007-06-21 2008-12-25 Hitachi, Ltd. Dimension measuring apparatus and dimension measuring method for semiconductor device
CN102683195A (zh) * 2011-03-11 2012-09-19 索尼公司 制造半导体装置的装置和方法及制造电子设备的方法
US20120326076A1 (en) * 2011-06-27 2012-12-27 International Business Machines Corporation Tool for manufacturing semiconductor structures and method of use
US9005464B2 (en) * 2011-06-27 2015-04-14 International Business Machines Corporation Tool for manufacturing semiconductor structures and method of use
CN104409348A (zh) * 2014-11-10 2015-03-11 成都士兰半导体制造有限公司 沟槽器件的制作方法

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TW507266B (en) 2002-10-21
JP2002151465A (ja) 2002-05-24
JP4437611B2 (ja) 2010-03-24
KR100437221B1 (ko) 2004-06-23

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