TW507266B - Method and system for manufacturing semiconductor device - Google Patents
Method and system for manufacturing semiconductor device Download PDFInfo
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- TW507266B TW507266B TW090116345A TW90116345A TW507266B TW 507266 B TW507266 B TW 507266B TW 090116345 A TW090116345 A TW 090116345A TW 90116345 A TW90116345 A TW 90116345A TW 507266 B TW507266 B TW 507266B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 86
- 238000000034 method Methods 0.000 title claims abstract description 61
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000005530 etching Methods 0.000 claims abstract description 42
- 238000005259 measurement Methods 0.000 claims abstract description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 7
- 238000012545 processing Methods 0.000 claims description 114
- 239000012535 impurity Substances 0.000 claims description 22
- 238000001039 wet etching Methods 0.000 claims description 21
- 239000007788 liquid Substances 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 239000002689 soil Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 12
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 238000005498 polishing Methods 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 abstract 3
- 229920005591 polysilicon Polymers 0.000 abstract 2
- 235000012431 wafers Nutrition 0.000 description 47
- 239000011229 interlayer Substances 0.000 description 37
- 238000000926 separation method Methods 0.000 description 17
- 239000010410 layer Substances 0.000 description 10
- 238000011282 treatment Methods 0.000 description 9
- 238000012937 correction Methods 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 239000003814 drug Substances 0.000 description 4
- 238000007689 inspection Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 241000238631 Hexapoda Species 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 150000004820 halides Chemical class 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 241000283074 Equus asinus Species 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 241000237509 Patinopecten sp. Species 0.000 description 1
- 241000233805 Phoenix Species 0.000 description 1
- 241000282806 Rhinoceros Species 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- DHXVGJBLRPWPCS-UHFFFAOYSA-N Tetrahydropyran Chemical compound C1CCOCC1 DHXVGJBLRPWPCS-UHFFFAOYSA-N 0.000 description 1
- 230000003796 beauty Effects 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229940079593 drug Drugs 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000004945 emulsification Methods 0.000 description 1
- 239000000839 emulsion Substances 0.000 description 1
- 238000009313 farming Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002309 gasification Methods 0.000 description 1
- 230000002496 gastric effect Effects 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 230000006651 lactation Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- CSHWQDPOILHKBI-UHFFFAOYSA-N peryrene Natural products C1=CC(C2=CC=CC=3C2=C2C=CC=3)=C3C2=CC=CC3=C1 CSHWQDPOILHKBI-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 235000020637 scallop Nutrition 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Weting (AREA)
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
507266 五、發明說明（1) [發明所屬之技術頜威] 本發明有關於半導體裝置之製造方法和製造系統，以及 半導體裝置，尤其有關於可以提高半導體裝置之良率之有 效之製造方法和製造系統，以及使用該等之方法或裝置所 製造之半導體裝置。 [習知之技術] 在習知之半導體裝置之製造工程中，所提案之技術是在 钱刻處理之前後，於晶圓上進行膜厚測定，將其結果回饋 ^為蝕刻條件，用來使工程穩定化。例如，在日' ^國專利 開平1 0-275753號中記載有於指定之膜之形成後，或 =之膜之姓刻後’以任意之頻度進行膜厚測 =把握成膜裝置或姓刻裝置之隨時間之變動：： 枯f :所把握之隨時間變動之有關資訊，在上述之習 技術中，作為判斷發生警報時 ^之白知 資料，或县妯剎田从A J A展置之維護時間之基礎 資料。另外，在日太、凋整成膜或蝕刻等之條件時之基礎 之:術晶特;，，號中所揭* 結果自動的變更晶圓處理之檢測’根據其檢查 [發明所欲解決之問題] 二ί之i;之是將指定之處理之前後進行晶 述之習知技術是根據在4之技術。亦即，上 用來校正該工程之處理=處理之晶圓之狀態， 對象進行檢查之結果，不、合 ^種情況，以某一晶圓為 不會反映在該晶圓本身之處理。對 第5頁 C:\2D-C»DE\90-09\90l16345.ptd 507266507266 V. Description of the invention (1) [Technology to which the invention belongs] The present invention relates to a manufacturing method and a manufacturing system of a semiconductor device, and a semiconductor device, and more particularly to an effective manufacturing method and manufacturing method that can improve the yield of a semiconductor device. Systems, and semiconductor devices manufactured using such methods or devices. [Known technology] In the conventional semiconductor device manufacturing process, the proposed technology is to measure the film thickness on the wafer before and after the engraving process, and return the results to the etching conditions to stabilize the process. Into. For example, Japanese Patent Application No. 10-275753 states that after the formation of a specified film, or after the last name of the film is engraved, the film thickness is measured at an arbitrary frequency = grasp the film forming device or the last name. Time-dependent changes of the device :: Dry f: The relevant information that is grasped over time. In the above-mentioned learning techniques, it is used as a white-handed information to judge when an alarm occurs ^, or the maintenance of the prefectural city of Kazata from AJA. Basic information on time. In addition, the basis of the conditions when the conditions are too high, film formation, etching, etc .: Shu Jingte ;, as disclosed in No. * Results automatically change the wafer processing inspection 'based on its inspection [invented to solve the Question] Two of the i; the conventional technique of crystallizing the specified treatment is based on the technique of 4. That is, the process used to correct the process = the state of the wafer being processed, and the results of the object's inspection are not the same. If a wafer is used, it will not be reflected in the processing of the wafer itself. Yes Page 5 C: \ 2D-C »DE \ 90-09 \ 90l16345.ptd 507266
五、發明說明（2)V. Description of the invention (2)
於此點，習知技術會有使各個工程之加工誤差等累積在各 個晶圓之問題。 本發明用來解決上述之問題，其第1目的是提供製造方 法，利用前饋之方法使晶圓之狀態反映在該晶圓之處理條 件，可以以高良率製造品質穩定之半導體裝置。 另外，本發明之第2目的是提供製造系統，利用前饋之 方法使晶圓之狀態反映在違晶圓之處理條件，可以以高良 率製造品質穩定之半導體裝置。 另外，本發明之第3目的是提供使用上述製 製造系統所製造之半導體裝置。 I仏方法或 [解決問題之手段] 本發明之申請專利範圍第1項是一種半導體裳 方法’包含有多個處理工程’其特徵是包含有.“ ㈣驟’以附加在指定之處理工 用來取得指定之測定值； U邗馮對象， 來決定上述之指定之處 第2步驟，根據上述之測定值用 理工程之處理條件；和 第3步驟’依照上述之第2步騍 實行上述之指定之處理工程。 /、疋之處理條件’用來 本發明之申請專利範圍第2項县+ Λ ^ 半導體裝置之製造方法中使 明專利範圍第1項之<1 上述之指定之處理是以指 處理，和 定之被處理膜作為 對象之蝕刻 上述之指定之測定值是 用來表At this point, the conventional technology has the problem of accumulating processing errors and the like of each process on each wafer. The present invention is intended to solve the above-mentioned problems. A first object of the present invention is to provide a manufacturing method, which uses a feedforward method to reflect the state of a wafer to the processing conditions of the wafer, so that a semiconductor device with stable quality can be manufactured with a high yield. In addition, a second object of the present invention is to provide a manufacturing system that uses a feedforward method to reflect the state of a wafer to processing conditions that violate the wafer, and can manufacture a semiconductor device with stable quality at a high yield. A third object of the present invention is to provide a semiconductor device manufactured using the above manufacturing system. I. Method or [Method for Solving Problems] The first item of the scope of patent application of the present invention is a semiconductor method 'contains a plurality of processing processes', which is characterized by the inclusion of "steps" for use in the designated places To obtain the specified measured value; U 邗 Feng object, to determine the above-mentioned specified place in step 2, using the processing conditions of the engineering process based on the above-mentioned measured value; and in step 3, the above-mentioned step 2 is carried out to implement the above-mentioned Designated processing project. /, "Processing conditions for 疋" used in the patent application scope of the present invention 2nd county + Λ ^ semiconductor manufacturing method of the first patent scope < 1 The above-mentioned designated processing is Refers to the treatment, and the etching of the film to be treated as the target. The above specified measurement values are used to indicate
C:\2D-CODE\90-09\90116345.ptd 示上述被處理獏之物理量C: \ 2D-CODE \ 90-09 \ 90116345.ptd shows the physical quantities
^υ/ζ〇() 五、發明說明（3) 之值。 本發明之申請專利範圍第3 在申往 半導體裝置之穿造方、、私击 、 明專利乾圍第2項之 膜之膜厚。 值疋上述之被處理 本發明之申請專利範圍第4 半導體裝置之製造方法中使、在申吻專利範圍第2項之 上述之被處理膜是含有雜質 上述之測定值是上述之石夕J *氣化膜，·和 本發明之申請專利範圍第5乳工化曰膜所含有之雜質之濃度。 半導體裝置之製造方法中使貝疋在申請專利範圍第2項之 膜之折射率。 上述之測定值是上述之被處理 本發明之申請專利範圍 半導體裝置之製造方法中 胃疋在申請專利範圍第2項之 膜之尺寸。 上述之測定值是上述之被處理 本發明之申請專利範圍 卜 項中任一項之半導 員是在申請專利範圍第1至6 上述之第1步驟所包含 i &方法中使 取得上述之指定之測定值副步騍是使製造線之測定裝置 上述之第2步驟所包含 述之指定之測定值發訊之副步驟有：上述之測定裝置將上 腦參照預先記憶之處理接i造線之主電腦；和上述之主電 上述之處理條件；和 收，根據上述之測定值用來決定 上述之第3步驟所包含 決定之處理條件由上述甽步驟有：將上述之第2步驟所 主電腦發訊到製造線之處理裝^ υ / ζ〇 () 5. The value of invention description (3). The third aspect of the patent application scope of the present invention is the film thickness of the film applied to the semiconductor device manufacturing method, the private attack, and the second patent. It is to be noted that, in the method for manufacturing a semiconductor device No. 4 of the scope of patent application for the invention to be processed as described above, the above-mentioned processed film in the scope of the patent application No. 2 contains impurities, and the above-mentioned measured value is the above-mentioned Shi Xi J * Gasification membranes, and the concentration of impurities contained in the 5th lactation membrane of the patent application scope of the present invention. In the method of manufacturing a semiconductor device, the refractive index of the film of Behr within the scope of patent application No. 2 is used. The above-mentioned measured value is the size of the film in the patent application scope of the present invention, the semiconductor device manufacturing method, and the second item in the patent application scope of the present invention. The above-mentioned measured value is a semi-guide of any one of the above-mentioned claims for the scope of patent application of the invention being processed. The i & The designated sub-step of the measured value is the sub-step for sending the designated measured value included in the above-mentioned second step of the measuring device of the manufacturing line: the above-mentioned measuring device connects the upper brain with reference to the pre-memorized processing to make the line The host computer; and the above-mentioned processing conditions of the above-mentioned main power; and receiving, based on the above-mentioned measured values, used to determine the processing conditions included in the above-mentioned third step are determined by the above-mentioned steps: Processing equipment sent from computer to manufacturing line
五、發明說明（4) 置；和上述之處理 定之處理工程。、又照上述之處理條件實行上述之指 本發明之申請專利〜 項中任一項之半導壯圍第8項疋在申請專利範圍第1至6 上述之们步+驟^^^製造方法中使 取得上述之指定之测定3之/步驟疋使製造線之測定裝置 上述之第2步驟所包 ’ 述之指定之測定值於 剞v驟有：上述之測定裝置將上 將根據上述之測定製造線之主電腦；上述之主電腦 理裝置；和上述之處^ =定之指令信號發訊到製造線之處 先記憶之處理接收，:置根據上述之指令信號，參照預 上述之第3步驟所勺人來決定上述之處理條件；和 上述之第2步驟所決!： 3 =副步驟是上述之處理裝置依照 理工程。 、疋之處理條件，實行上述之指定之處 本發明之申請專利a 々 項中任-項之半導，，第9項是在申請專利範圍第1至6 上述之指定之ίΞϊ製造方法中使 蝕刻處理·， 疋以指定之被處理膜作為對象之濕式 上述之指定之測定 3 讀1 量之值；和 疋用來表示上述之被處理膜之物理 更包含有第4步騍， 、 藥液更換後之經過時間计數上述之濕式蝕刻所使用之 步驟根據上述之測定值和上述之經過時 用來決疋上述之濕式餘刻之處理條件；和V. Description of the Invention (4) Set up; and the above-mentioned treatments. And implement the above-mentioned processing conditions according to the above-mentioned patent application of the present invention ~ any of the semi-conducting enclaves of item 8 in the patent application scope 1 to 6 above steps + steps ^^^ manufacturing method In order to obtain the above-mentioned specified measurement 3 / step, the measurement device of the manufacturing line is included in the second step of the above-mentioned specified measurement value in step v. The above-mentioned measurement device will be based on the above-mentioned measurement by the general The host computer of the manufacturing line; the host computer management device described above; and the above place ^ = the set command signal is sent to the place where the manufacturing line is memorized and received, and it is set according to the above command signal, referring to the third step above The person in charge decides the above-mentioned processing conditions; and the above-mentioned second step is determined !: 3 = The sub-step is the above-mentioned processing device according to the rational engineering. The processing conditions of 疋, the implementation of the above-mentioned designated areas, the semi-conductor of any one of 专利-申请 in the application for patent of the present invention, and the 9th is the use of the 指定 Ξϊ manufacturing method specified in the above-mentioned patent application scope 1 to 6 Etching process: (1) Wet method for the specified film to be treated. The above specified measurement (3) reads the value of 1; and (3) The physical value of the film to be treated includes the fourth step. The elapsed time after the liquid replacement is counted. The steps used for the wet etching described above are based on the above-mentioned measured values and the elapsed time used to determine the above-mentioned wet remaining processing conditions; and
五、發明說明（5) 在上述之 理。 本發明之 方法，其特 以濕式養虫 計數上述 根據上述 件；和 依照上述 刻處理。 本發明之 系統，用來 測定裝置 用來取得指 接收決定 處理工程之 處理裝置 用來實行上 本發明之 之半導體裝 上述之指 處理；和 第3步驟，依照該處理條件實行濕式蝕刻處 申請專利範圍第1 0項是一種半導體裝置之製、生 徵是所包含之步驟有： 刻對指定之被處理膜進行處理； 之屬式|虫刻所使用之藥液更換後之經過時間. 之經過時間用來決定上述之濕式蝕刻之處理條 之步驟所決定之處理條件，實行上述之濕式餘 2請專利範圍第11項是一種半導體裝置之製造 貫行多個處理工程，其特徵是具備有： ’以附加在指定之處理工程之晶圓作為對氮， 定之測定值； 部’根據上述之測定值用來決定上述之指定之 處理條件；和 ’依照上述之接收決定部所決定之處理條件， 述之指定之處理工程。 、 申請專利範圍第1 2項是在申請專利範圍第丨丨項 置之製造系統中使 ' 定之處理是以指定之被處理膜作為對象之餘刻 上述之指定之測定值是用來表示上述被處理膜之物理量 之值。V. Description of the invention (5) Based on the above. The method of the present invention, which specifically counts the above-mentioned according to the above-mentioned items, and the treatment according to the above-mentioned, with a wet-type insect farming. The system of the present invention is used for the measuring device to obtain the processing means for receiving and deciding the processing process for performing the above-mentioned finger processing of the semiconductor device of the present invention; and the third step is to perform a wet etching application in accordance with the processing conditions. The 10th item in the patent scope is the manufacturing of a semiconductor device, and its characteristics include the following steps: processing the designated film to be processed; genre type | elapsed time after the replacement of the chemical liquid used by the insect. The elapsed time is used to determine the processing conditions determined by the steps of the above-mentioned wet etching process strips. The implementation of the above-mentioned wet-type method. The scope of the patent claim No. 11 is a semiconductor device manufacturing process which is characterized by multiple processes. It has: 'Take the wafer attached to the designated processing process as the measured value for nitrogen; the department' is used to determine the above-mentioned specified processing conditions based on the above-mentioned measured values; and 'in accordance with the above-mentioned acceptance decision department's decision Processing conditions, as stated in the designated processing works. The 12th item in the scope of patent application is used in the manufacturing system of item No. 丨 丨 in the scope of application for the patent. The specified measurement value is used to indicate that the above specified measurement value is used to indicate the above. The value of the physical quantity of the treatment film.
)0726607266
五、發明說明（6) 之利範圍第13項是在申請專利範圍第I〗項 理2= 造系統中使上述之測定值是上述之被處 ，發明之中請專利範圍第14項是在中第 之半導體裝置之製造系統中使 轨圍第12項 上述之被處理膜是含有雜質之矽氧化膜；和 士述之測定值是上述之石夕氧化膜所含有 本發明之申請專利範圍第丨5項是在 w ^之/辰度。 之半導體裝置之製造系統中使上述；二以“:圍第12項 理膜之折射率。 疋值疋上述之被處 [發明之實施形態] 下面將參照圖面用來說明本發明之實施 各個圖中，在共同之元件附加相同之元件編:J'。另夕甘卜’在 之說明則加以省略。 1千編就，而其重複 形態 1 · 圖1是方塊圖，用來表示本發明之 ?之製造系統之構造。如圖1所示， 二之半導體裝 統具備有主電腦10，測定裝置12，和本 '仃开> ·%之製造系 2 j :則f f置121處理裝置14經由通信線‘ ϊ V。、主電腦 互相進行資訊通信之方气 、路連接成為可以 處理裝置“用來進行造半導 如其構成包含有:成膜裝置：來程/實行之各 成扣疋之膜；和乾式蝕 用來在晶圓上形 貝不有夕個處理裝置14，V. Description of the invention (6) The benefit range of item 13 is in the scope of application for the patent application. The first item is 2 = the system makes the above measurement value be the above. In the manufacturing system of the medium semiconductor device, the above-mentioned processed film of the rail No. 12 is a silicon oxide film containing impurities; and the measured value is that the above-mentioned Shixi oxide film contains the patent application scope of the present invention.丨 5 items are in w ^ / chen degree. In the manufacturing system of the semiconductor device, the above is used; ": The refractive index of the twelfth physical film is described. The value 疋 is set forth above. [Embodiment of the invention] The following will explain the implementation of the present invention with reference to the drawings. In the figure, the same component code is added to the common component: J '. In addition, the description of Gambo' is omitted. One thousand is made, and its repeated form 1 · Figure 1 is a block diagram showing the present invention The structure of the manufacturing system. As shown in FIG. 1, the second semiconductor device is equipped with a host computer 10, a measuring device 12, and the manufacturing system 2 of the “仃 开”. 14 Via communication line ϊ V., the host computer performs information communication with each other, and the road connection becomes a processing device. "It is used to make semiconducting conductors. Its structure includes: film forming device: each component of the incoming / outgoing process." Film; and dry etching to form a wafer on the wafer without a processing device 14,
\\312\2d-code\90-09\90116345.ptd 第10頁 晶圓上之膜進行蝕刻。 二員;？刻裝置等，用來對\\ 312 \ 2d-code \ 90-09 \ 90116345.ptd Page 10 The film on the wafer is etched. Two members ;? Engraving device, etc.
Si 507266 五、發明說明（7) '~ --—- 但是本實施形態之系統所含之處理裝置14亦可以只有ι 個。 測定裝置1 2在半導體裝置之製造過程中，以晶圓作 象用來進行指定之檢查，例如其構成包含有··膜厚測定裝 置，用來測定形成在晶圓表面之膜之厚度；雜質測定裝 置，用來測定晶圓表面之膜所含之雜質之濃度；尺寸^定 裝置，用來測定形成在晶圓表面之圖型之尺寸；或層 化膜測定裝置等，用來測定形成在晶圓表面之膜之層間I 化膜。在圖1中，測定裝置丨2只顯示一個，但是在本實施 形悲之系統内，亦可以配置多個之測定裝置1 2。 主電腦ίο具備有測定值收訊部16，用來收訊測定裝置12 所測定到之測定值。測定值收訊部丨6所收訊到之測^值經 由測定值記憶部1 8，與附加在被測定晶圓之丨D 一 在測定值記憶器20。 ° & 主電腦10更具備有ID收訊部22。處理裝置η在開始晶圓 之處理之前，依照需要，將附加在加工對象之晶圓之I 〇發 訊到主電腦10。以下將發訊ID之處理裝置14特別稱為「_ 制對象處理裝置14」。ID收訊部22接受發訊自控制對象^ 理裝置14之ID，將其轉送到接收決定部。接收決定部24根 據其ID，讀出與在控制對象處理裝置14被加工之晶圓有關 之被δ己憶在測疋值$己憶器2 〇之測定值，亦即，讀出々制對 象處理裝置1 4之處理前所測定到之測定值。 、 控制對象處理裝置14處理晶圓時之條件最好是依照開始 該處理之時刻之晶圓之狀態，進行適當之設定。亦即，控 cSi 507266 V. Description of the invention (7) '~ ----- However, the processing device 14 included in the system of this embodiment mode may be only ι. The measuring device 12 uses a wafer as an image to perform a specified inspection during the manufacture of a semiconductor device. For example, its configuration includes a film thickness measuring device for measuring the thickness of a film formed on the surface of a wafer; impurities The measuring device is used to measure the concentration of impurities contained in the film on the wafer surface; the size setting device is used to measure the size of the pattern formed on the wafer surface; or the layered film measuring device is used to measure the Interlayer I film on the wafer surface. In FIG. 1, only one measuring device is shown, but in the system of the present embodiment, a plurality of measuring devices 12 may be arranged. The host computer includes a measured value receiving unit 16 for receiving the measured value measured by the measuring device 12. The measured value received by the measured value receiving section 6 passes through the measured value storage section 18, and the measured value memory 20 is attached to D1 attached to the wafer to be measured. ° & The host computer 10 is further provided with an ID receiving section 22. Before starting the processing of the wafer, the processing device η transmits the I0 added to the processing target wafer to the host computer 10 as needed. Hereinafter, the processing device 14 for transmitting an ID is specifically referred to as "_ target processing device 14". The ID receiving unit 22 receives the ID transmitted from the control target management device 14 and forwards it to the reception decision unit. The reception decision unit 24 reads out the measured value of the measured value δ value memorized by the memorizer 2 〇, which is related to the wafer processed in the control target processing device 14, based on the ID, that is, reads the target to be controlled. The processing device 14 measures the measured values before processing. It is preferable that the conditions when the control target processing device 14 processes the wafer are appropriately set according to the state of the wafer at the time when the processing is started. That is, control c
:\2D-roDE\90-09\90116345.ptd: \ 2D-roDE \ 90-09 \ 90116345.ptd
^υ/266 五、發明說明（8) 制對象處理裝置1 4處理曰阿η 士 A Μ曰^ « 之前，與該晶圓有；：;曰，之條件敢好是依照在該處理 ^ 關之測疋到之測定值，進行適當之設 定。 在主電腦1 0所且锯♦ & ^ 裝置14之最佳處理：；接：記憶器26，記錄控制對象處理 之預定之最佳處理條：T即’記錄與上述之測定值有關 值記憶器20讀出之測 边之接收決定部24根據從測定 值對應之最佳處理侔#以t憶益26讀出與該測定 由接收發訊部28發3二 出之最佳處理條件經 控制對象處理處理裝置14。 之最佳條件進行晶圓之^所述的使用從主電腦10發訊來 之系統可以利用; = 依!!㈣方式，本實施形態 之狀態反映在控制對象處理^ 1定到之晶圓 實施形態之系統可以# ^ 处條件。亦即，本 反映在該晶圓本：：;吏=置12所測定到之晶圓之狀態 系統時，各個工因此’依照本實施形態之 率製造品質穩定之半以：累積在晶圓上，可以以高良 下面將參照圖2用來更詳 之動作。 兄月貝她形您1之製造系統 本實施形態之製造系統之目 分離之製造工程中，P 拉=在使用溝道構造之元件 之分離氧化臈之表面二=精確度控制埋入到溝道内部 道構造之元件分離之製造工程 2差。在使用溝 如圖2⑴所示，在梦基板31之表二仃之處理。 办成矽氧化膜35， ml 第〗2頁 \\3l2\2d-code\90-09\90H6345.ptd 507266 五、發明說明（9) ^晶矽膜34，和矽氮化膜32。矽氮化膜32被圖型製作成配 合所欲形成之溝道之形狀。以圖型製作成之矽氮化膜32作 為遮罩’經由進行乾式蝕刻用來在矽基板3丨形成溝道。其 次，以埋入到溝道内部之方式，利用CVD(Chemical Vapor Deposition)法在矽基板31之全面堆積氧化膜。然後，只 在溝逼之内部殘留氧化膜用來形成分離氧化膜3 3，利用 CM P( Chemical Mechanical Polishing)法除去從溝道突出 之氧化膜。 在本實施形態中，於上述之CMP之後順序的實行分離氧 化膜33之蝕刻，矽氮化膜32之蝕刻，和多晶矽膜34之蝕 刻。在上述之一連貫之處理之過程中，CMp之研磨量容易 產生比較大之誤差。因此，在依照既定之條件實行分離氧 化膜33之蝕刻時，要使分離氧化膜33之表面和矽基板31之^ υ / 266 V. Description of the invention (8) Object processing device 1 4 Processes 阿士 A Μ 曰 ^ «Before, it had the wafer;:; The conditions are good according to the processing ^ 关The measured value obtained is set appropriately. At the host computer 10, the best processing of the & ^ device 14 :; then: the memory 26, recording the predetermined optimal processing bar for the control object processing: T means' record the value related to the above measured value memory The receiving determination unit 24 of the measuring side read out by the device 20 is controlled according to the optimal processing corresponding to the measured value. The optimal processing conditions for reading out the measurement by the receiving and transmitting unit 28 and receiving the measured result are controlled by the control unit 26. Object processing device 14. The best conditions for the use of wafers are described in the following. The system sent from the host computer 10 can be used; = According to the !! ㈣ method, the status of this embodiment is reflected in the implementation of the control object processing ^ 1 The system of patterns can be placed in conditions. That is, this wafer is reflected in the wafer: When the state of the wafer measured by the system is set, each worker therefore 'makes half of the stable quality according to the rate of this embodiment: accumulated on the wafer You can use Gao Liang to refer to Figure 2 for more detailed actions. Brother Yue Bei shape your manufacturing system 1 In the manufacturing process of the manufacturing system of this embodiment, P pull = In the surface of the element using the trench structure to separate the hafnium oxide 2 = precision control embedded in the trench The manufacturing process for the separation of the components of the internal structure is poor. As shown in FIG. 2 (a), the in-use groove is treated on the second substrate of the dream substrate 31. Create a silicon oxide film 35, ml Page 2 \\ 3l2 \ 2d-code \ 90-09 \ 90H6345.ptd 507266 5. Description of the invention (9) ^ crystalline silicon film 34, and silicon nitride film 32. The silicon nitride film 32 is patterned into a shape that matches the desired channel. The patterned silicon nitride film 32 is used as a mask 'to form a channel in the silicon substrate 3 through dry etching. Next, an oxide film is deposited on the entire surface of the silicon substrate 31 by a CVD (Chemical Vapor Deposition) method so as to be buried inside the trench. Then, an oxide film is left only inside the trench to form a separation oxide film 3, and the oxide film protruding from the channel is removed by a CMP (Chemical Mechanical Polishing) method. In this embodiment, the etching of the separation oxide film 33, the etching of the silicon nitride film 32, and the etching of the polycrystalline silicon film 34 are sequentially performed after the above-mentioned CMP. In the course of one of the above-mentioned consecutive processes, the grinding amount of CMP is prone to produce relatively large errors. Therefore, when the etching of the separation oxide film 33 is performed in accordance with predetermined conditions, the surface of the separation oxide film 33 and the surface of the silicon substrate 31 must be etched.
表面之高度差36在最後以良好之精確度成為所希望之值會 有困難。 S 在本實施形態中，如圖1(B)所示，在完成氧化膜之CMp 處理後，測定分離氧化膜3 3之膜厚。然後，利用前饋之方 法使其結果所獲得之測定值反映在分離氧化膜33之蝕刻條 件。亦即’在本實施形態中，於CMP之後用以測定分離氧 化膜33之膜厚之膜厚測定裝置與圖i所示之測定裝置12相 當，另外，分離氧化膜33之蝕刻所使用之蝕刻裝置與控制 對象處理裝置14相當。 t η $ 依知、本貝知形悲之I造系統時’每次完成晶圓之CMp處 理就測定該晶圓上之分離氧化膜3 3之膜厚。將其、纟士果所興It may be difficult for the height difference 36 of the surface to finally reach the desired value with good accuracy. S In this embodiment, as shown in FIG. 1 (B), after the CMP treatment of the oxide film is completed, the film thickness of the separation oxide film 33 is measured. Then, the measured value obtained as a result of the feedforward method is reflected in the etching conditions of the separation oxide film 33. That is, in this embodiment, the film thickness measurement device for measuring the film thickness of the separation oxide film 33 after CMP is equivalent to the measurement device 12 shown in FIG. I. In addition, the etching used for the etching of the separation oxide film 33 The device corresponds to the control target processing device 14. t η $ When I build the system according to the knowledge and the knowledge of the sadness ’Each time the CMP processing of the wafer is completed, the film thickness of the separation oxide film 3 3 on the wafer is measured. Prosper it
\\326\2d-\90-09\90116345.ptd 第13頁 五、發明說明（10) 得之測定值發訊到主電腦〗〇，盥嗲曰 定值記憶器20。另外，在該曰^ ®之ID一起記錄在測 工程墙，慮置對；二化膜33之㈣ 然後將㈣u之處理條#1^求最佳條件之發訊。 最佳條件。然η該最=收決定部24所決定之 依昭_L & β β t #條件刻分離氧化膜33。 依々述之製造方法時’與CMp之研磨量之變動無關 板31之^良好之精確度，將分離氧化膜33之表面和矽基 板31之表面之高度差’經常抑\\ 326 \ 2d- \ 90-09 \ 90116345.ptd Page 13 V. Description of the invention (10) The measured value obtained is sent to the host computer. In addition, the ID is recorded on the test wall together, and it is considered to be the right one; the second film 33 and then the processing strip # 1 of the 求 u for the best condition of the message. Optimal conditions. However, the maximum value = the oxidized film 33 is determined by the condition determined by the receiving determination unit 24 according to the conditions of the _L & β β t # condition. According to the manufacturing method described above, it has nothing to do with the change of the grinding amount of CMP. The good accuracy of the plate 31 will make the difference between the height of the surface of the oxide film 33 and the surface of the silicon substrate 31 constant.
…製造方法或製造系統；，丄K率J 仏口口貝穩定之半導體裝置。 衣 在上述之灵方也形悲1中，在每一個 個晶圓設定分離氧化膜Μ夕M U 在母一 限於此種“：言=刻條件’但是本發明並不只 設定姓刻條：。P '亦可以以批單位設定ID，以批單位 處在形態1中’在主電腦1〇之内部設定 象處理裝置14)°/件從主電腦1〇發訊到蝕刻裝置（控制對 即，亦可以在餘^是/發明並不只限於此種方式。亦 1〇從該等條件中選；最：ΐ::多個處理條件，在主電腦 實施形熊2、 :m f圖3用來說明本發明之實施形態2。 二施升y心之製造方法是以與實施形態1之情況同樣之 順序貫施CMP之處理後，如圖3⑻所示，進行矽氮化膜之 触刻。圖3(A)表示從多晶石夕膜34之上除去石夕氮化膜後之狀… Manufacturing method or manufacturing system; 丄 K 率 J 仏 口 口 口 stabilized semiconductor device. In the above-mentioned spirit square, it is also shown in Figure 1 that the separation oxide film MU MU is set on each wafer. The mother is limited to this type: "word = engraving condition ', but the present invention does not only set the surname: .P 'You can also set the ID in batch units and be in Form 1 in batch units.' Set the image processing device 14 inside the host computer 10) ° / piece Send a signal from the host computer 10 to the etching device (control is It can be used in the invention / invention and is not limited to this way. It is also 10 to choose from these conditions; the most: ΐ :: multiple processing conditions, implemented in the host computer shaped bear 2,: mf Figure 3 is used to illustrate this Embodiment 2 of the invention. The manufacturing method of the second application of the y core is performed by applying CMP in the same order as in the case of Embodiment 1. As shown in FIG. 3 (a), the silicon nitride film is etched. FIG. 3 ( A) shows the state after removing the stone nitride film from the polycrystalline stone film 34
\\326\2d-\90-09\90116345.ptd 第14頁 507266\\ 326 \ 2d- \ 90-09 \ 90116345.ptd Page 14 507266
在蝕刻矽氮化膜之後，利用測定裝置12測定分離氧化膜 發ΐίί雷二1之：定值，與實施形態1之情況同樣的，、 么汛到主電細1 〇，與附加在晶圓之丨D 一起記錄。 -ί、：該晶圓作為對象，進行分離氧化膜33之蝕刻。 :日寺’與貫施形態！之情況同樣的，利用主電腦1〇將蝕刻 衣：(與控制對象處理裝置14相當）之處理條件 之條件。取1玉 依，本發明之製造方法或製造系統時，由於CMp所造成 之为離氧化膜33之膜厚之變動，和由於矽氮化膜之除去 造成之分離氧化膜33之膜厚之變動，可以反映在分離 膜33之蝕刻條件。因此，依照本實施形態之製造方法或 造系統時，當與實施形態1之情況比較，可以以更良好、 精確度將分離氧化膜33之表面和碎基板31 控制在所希望之值。 ® <网度差 實施形態31 :面將參照圖4用來說明本發明之實施形態3。 斤實施形態3之目的是在用以使半導體裝置所具備之層間 氧化膜平坦化之蝕刻工程，以良好之精確度控制層間胃氧曰化 膜之膜厚。在本實施形態中，在半導體裝置之製造過 行以下所示之處理。 貝 如圖4(A)所示，在矽基板31之上形成電晶體之閘極電極 38和記憶單元之電容器電極4〇等之各種配線元件。其次， 以覆蓋在該等配線元件之方式，例如利用CVD法，在秒基After the silicon nitride film is etched, the measurement of the separation oxide film is performed using the measuring device 12. The fixed value is the same as in the case of the first embodiment.丨 D Record together. -: The etching of the separation oxide film 33 is performed on this wafer. : Sun Temple ’and Guan Shi Forms! In the same way, the host computer 10 is used to etch the etched clothes: (equivalent to the control target processing device 14) as the processing conditions. Take 1 Yuyi, when the manufacturing method or manufacturing system of the present invention, the change in the film thickness from the oxide film 33 due to CMP, and the change in the film thickness of the separation oxide film 33 due to the removal of the silicon nitride film, This can be reflected in the etching conditions of the separation film 33. Therefore, when the manufacturing method or system according to this embodiment is compared with the case of Embodiment 1, the surface of the separation oxide film 33 and the broken substrate 31 can be controlled to desired values with better accuracy. ® < Difference in network degree Embodiment 31: Embodiment 3 of the present invention will be described with reference to FIG. 4. The purpose of Embodiment 3 is to perform an etching process for flattening the interlayer oxide film provided in the semiconductor device, and to control the film thickness of the interlayer gastric oxygen film with good accuracy. In this embodiment, the following processing is performed during the manufacture of a semiconductor device. As shown in FIG. 4 (A), various wiring elements such as a gate electrode 38 of a transistor and a capacitor electrode 40 of a memory cell are formed on a silicon substrate 31. Secondly, by covering the wiring elements, for example, using the CVD method,
C:\2D-CODE\90-09\90116345.ptd 第15頁C: \ 2D-CODE \ 90-09 \ 90116345.ptd Page 15
507266 五、發明說明（12) 3 1 表之王面堆積層間氧化膜4 2。這時，在層間氧化膜4 2之 $成由於上述之配線元件之有無或配線元件之構造之 不同所引起之高度差。 在後工程’於層間氧化膜42之上，形成圖中未顯示之上 二，線。層間氧化膜42之表面之高度差在上層配線之形成 在、為圖型製作不良等之原因。因此，在本實施形態中， 上層配線之形成之前，以覆蓋在層間氧化臈U之凹陷區 二之方式形成抗蝕劑膜44。另外，以該抗蝕劑膜44作為遮 罩’進行層間氧化膜42之深蝕刻。 ^圖4 ( B )所示，在本實施形態中，於堆積層間氧化膜$ 2 後利用照相製版形成抗餘劑膜4 4之前，測定該層間氧 =，42之膜厚。然後，利用前饋之方法，使其測定結果所 ^仔之測定值反映在層間氧化膜42之深蝕刻條件。亦即， 實施形態中，於層間氧化膜42之堆積後，用以測定直 膜厚之膜厚測定裝置與圖1所示之測定裝置1 2相當，另 =j f間氧化膜42之深蝕刻所使用之蝕刻裝置與上述之 制對象處理裝置1 4相當。 工 膜4=i實；形態之製造系統時，在晶圓上堆積層間氧化 、2之後，利用膜厚測定裝置（測定裝置丨測定苴 將t結果所獲得之測定值發訊到主電腦1〇，與被測定：圓 錄在測定值記憶器20。另外，在該晶圓到= 間虱化M42之深蝕刻工程之階段， 』逐層 理裝置14)對主電腦1〇要求最佳條件之二:($ :對象處 主電腦1 0之接收決定部24 ’將根據；腺’利用 像層間乳化膜4 2之膜厚所 C:\2D-C0DE\90-09\90116345.ptd 第16頁 五、發明說明（13) ’c最佳條件’設定作為 以該最佳铬彼琳丄S扣〆 且〜处狂你仵。然後， ^佳條件對層間氧化膜42進行深蝕刻。 依fc、上述之製造方法時， 良好之精確声倍屏„气7、在v成上層配線之前，可以以 又使層間氧化膜4 2之膜厚均一化。 本貫施形態之製造方法 ^ ， 口此依照 層配線之圖型製作不，^糸”可以有效的防止上 導體裝置。可以以南良率製造品質穩定之半 個ίΐΐί:施形態3中，在每-個晶圓設定ID，在每- 個日日圓$又疋層間氧4卜腔^ 9 限於此種方式。言即介 刻條件，但是本發明並不只 設定姓刻條i。亦即’亦可以以批單位設定id，以批單位 卢理條#•在i ί之貫施形態3中’在主電腦1 〇之内部設定 :产=署1!條件從主電腦10發訊到蝕刻裝置(控制對 本處，置14) ’但是本發明並不只限於此種方式。亦 i兮箅I: ί t刻裝置侧記憶多個處理條件，在主電腦10 從違專之條件中選擇最佳之條件。 實施形態4. J面將參照圖5用來說明本發明實施形態4。 貫施，態4，與實施形態3之情況同樣的，其目的是在用 以使半導體裂置所具備之層間氧化膜平坦化之钱= 以良好之精確度控制層間氧化膜之膜厚。T面將 形態4與實施形態3相異之部份。 兄月貝她 在本實施形態中’層間氧化膜42使用含有β或？等之雜質 之氧化膜。在利用含有B*P之氧化膜形成層間氧化膜4 2之507266 V. Description of the invention (12) 3 1 The king surface of the table is stacked with interlayer oxide film 4 2. At this time, the difference in the height of the interlayer oxide film 42 due to the presence or absence of the above-mentioned wiring elements or the structure of the wiring elements is different. In the post-process' on the interlayer oxide film 42, lines not shown in the figure are formed. The difference in the height of the surface of the interlayer oxide film 42 is caused by the formation of the upper-layer wiring, and is caused by poor pattern production. Therefore, in this embodiment, before the formation of the upper-layer wiring, the resist film 44 is formed so as to cover the recessed area 2 of the interlayer hafnium oxide U. Further, the interlayer oxide film 42 is deeply etched using the resist film 44 as a mask '. ^ As shown in FIG. 4 (B), in this embodiment, after the interlayer oxide film $ 2 is deposited, the anti-remainder film 44 is formed by photoengraving, and the interlayer oxygen = 42 is measured. Then, the feed-forward method is used to reflect the measured value of the measurement result in the deep etching conditions of the interlayer oxide film 42. That is, in the embodiment, after the interlayer oxide film 42 is deposited, the film thickness measuring device for measuring the thickness of the straight film is equivalent to the measuring device 12 shown in FIG. The etching apparatus used is equivalent to the above-mentioned object processing apparatus 14. Working film 4 = i; in the manufacturing system of the form, after the interlayer oxidation and 2 are deposited on the wafer, a film thickness measuring device (measurement device 丨 measurement 苴) is used to send the measured value obtained by the t result to the host computer 1〇 , And measured: recorded in the measured value memory 20. In addition, at the stage of the deep etching process from the wafer to the M42, the layer-by-layer processing device 14) requires the host computer 10 for the optimal conditions. Second: ($: The receiving decision unit 24 of the host computer 10's subject will be based on; the gland 'uses the film thickness of the interlayer emulsion film 4 2 C: \ 2D-C0DE \ 90-09 \ 90116345.ptd page 16 V. Description of the invention (13) 'c optimal condition' is set to use the best chrome perylene 丄 S buckle and ~ mad you. Then, the best conditions for deep etching of the interlayer oxide film 42. According to fc, In the above-mentioned manufacturing method, a good and accurate acoustic double screen „Gas 7. Before v becomes the upper layer wiring, the film thickness of the interlayer oxide film 42 can be uniformized again. The manufacturing method of the present embodiment ^, according to this If the pattern of the layer wiring is not produced, "^ 有效" can effectively prevent the upper conductor device. The product can be manufactured at a South yield. Half of the stable quality: In the configuration 3, the ID is set in each wafer, and the interlayer oxygen is 4 in each yen per day. 9 is limited to this method. It means the immediate conditions, but this The invention does not only set the last name engraved i. That is, 'id can also be set in batch units, and in batch units Lu Li Article # • In i 之 之 consistent implementation mode 3' is set inside the host computer 10: Industry = Department 1! Conditions from the host computer 10 to the etching device (control to this place, set 14) 'But the present invention is not limited to this way. Also I: 刻 t carved device side memorizes multiple processing conditions, in the host The computer 10 selects the best condition from the illegal conditions. Embodiment 4. J-plane will be used to describe Embodiment 4 of the present invention with reference to Fig. 5. The implementation of the fourth aspect is the same as that of the third embodiment, and its purpose It is the money used to flatten the interlayer oxide film provided in the semiconductor split = to control the film thickness of the interlayer oxide film with good accuracy. The T surface is the part that is different from the embodiment 4 and the third embodiment. In this embodiment, the interlayer oxide film 42 uses an oxide film containing impurities such as β or?. An oxide film containing B * P forms an interlayer oxide film 4 of 2
507266 五、發明說明（14) 情况時，可以提高其平坦性。因此，依照本實施形能 ，，當與實施形態3之情況比較時，可以更容易的使^ 氧化膜4 2平坦化。 曰間 塑”間氧化膜42含有雜質之情況時，其雜質之濃度會影 二^ /化則2之㈣速度。圖6之圖形表示使用緩衝氟 :4和HF之混合液）之濕示蝕刻時，氧化膜所含之p之 潋度對氧化膜之蝕刻速度之影響。如圖6所示，氧化 蝕刻速度隨著P之濃度之增加而增大。因此，層間氧化 之ΐ度成為決定蝕刻工程後殘留之層間氧化 膜4Ζ之膜厚之一大因素。 之ί圖制在本實施形態中，在堆積層間氡化膜42 之後，利用照相製版形成抗蝕劑膜44之前，測 化膜42 =含之雜質之濃度。然後’利用前饋之方 果所獲仔之測定值反映在層間氧化膜42之深蝕刻條 即，在本實施形態中，在層間氧化膜42之堆積後:、用以測 定其内部之雜質濃度之雜質濃度測定裝置與圖丨 另外’層間氧化膜42之深蚀刻所使用之： 刻裝置/、控制對象處理裝置1 4相當。 Ο 依照本實施形態之製造系統時，在晶圓上堆積層間氡化 膜42 =後，1用雜質測定裝置（測定裝置12)測定其 雜質濃度。將其結果所獲得之測定值發訊到主電腦1 〇，盘 被測定晶圓之id -起記錄在測定值記憶器20。 ς 晶圓到達層間氧化膜42之深蝕刻工程之階段，名虫 μ (控制對象處理裝置14)對主電腦1〇要求最佳條件之ς訊。507266 V. Description of the invention (14) In the case, the flatness can be improved. Therefore, according to this embodiment, when compared with the case of the third embodiment, the oxide film 42 can be more easily planarized. In the case where the "interlayer" interlayer oxide film 42 contains impurities, the concentration of the impurities will affect the rate of 化 / 化 2. The figure in Figure 6 shows the wet etching using a buffered fluorine: 4 and HF mixed solution) At the same time, the influence of the degree of p contained in the oxide film on the etching rate of the oxide film. As shown in Figure 6, the rate of oxide etching increases with the increase in the concentration of P. Therefore, the degree of interlayer oxidation becomes the determining etch The film thickness of the interlayer oxide film 4Z remaining after the process is a major factor. In this embodiment, after the interlayer halide film 42 is deposited, and before the resist film 44 is formed by photoengraving, the chemical film 42 is measured. = Concentration of impurities contained. Then, the measured value of the seed obtained by using the feed-forward cube fruit is reflected in the deep-etched strip of the interlayer oxide film 42. In this embodiment, after the interlayer oxide film 42 is deposited: The impurity concentration measuring device for measuring the internal impurity concentration is equivalent to the one used in the deep etching of the interlayer oxide film 42 in the figure: the engraving device / and the control target processing device 1 4. When the manufacturing system according to this embodiment is used, Build up layers on the wafer After the halide film 42 = 1, the impurity concentration is measured by an impurity measuring device (measurement device 12). The measured value obtained from the result is transmitted to the host computer 1 0, and the id of the wafer to be measured is recorded in the measurement. Value memory 20. At the stage where the wafer reaches the deep etching process of the interlayer oxide film 42, the famous worm μ (controlling object processing device 14) requests the host computer 10 for the optimal condition.
C: \2D-0)DE\90-09\90116345. ptd 第18頁 507266 五、發明說明（15) 然後，利用主電腦10之接收決定部24，將根據層間 42内之雜質濃度所決定之最佳條件，設定作為則 之 =理條件 '然|，以該最佳條件對層間氧化則2進^深姓 =照上述之製造方法時，τ以在形成上層配線 層，氧化膜42之膜厚以良好之精確度均一化。因此， 本貫施形態之製造方法或製造系統時，可以 々: =線之圖型製作不良，可以以高良率製造 導體裝置。 貝L疋之半 在上述之實施形態4中，在每一個晶圓設 個晶圓設定ID，在每一個晶圓#宗呙„ _ yi_ 隹母一 ..a ^ , 母1U日日W δ又疋層間乳化臈42之蝕刻條 件，仁疋本杳明並不只限於此種方式。亦即，亦飩 刻裝置側預先記憶多個處理條件， 件中選擇最佳之條件。 在主電細10’從該等條 另外，在上述之實施形態J至3中，分 氧化膜42之蚀刻條件之決定是根據該=則3或層間 上达之只^浴恶4中，層間氧化膜Μ之蝕 Θ 根據其内部所含有之雜質之濃度。但是=之決^疋 層間氧化膜42之蝕刻條件之美不σ刀離氧化臈33和 ^ 'Λ ric 土楚並不限於該算之魅4、 雜質濃度。例如，分離氧 忒寺之膑犀或 件之决疋亦可以根據該等之膜之折射 之银刻條 實施形態5. 下面將參照圖7用來說明本發明之 實施形態5之目的是以良好之精 。 又〜攻械細之配線圖C: \ 2D-0) DE \ 90-09 \ 90116345. Ptd page 18 507266 5. Description of the invention (15) Then, using the reception determination section 24 of the host computer 10, it will be determined based on the impurity concentration in the layer 42. The optimal conditions are set as follows: then the logical conditions are used. Then, the interlayer oxidation is performed using the optimal conditions. ^ Surname = When the above manufacturing method is used, τ is used to form the upper wiring layer and the oxide film 42. Thickness is uniformized with good accuracy. Therefore, when the manufacturing method or the manufacturing system of the present embodiment is used, it is possible to: 不良: = The pattern of the line is poorly manufactured, and the conductor device can be manufactured with a high yield. In the fourth embodiment, a wafer setting ID is set on each wafer, and each wafer # 宗 呙 „_ yi_ 隹 mother one .. a ^, mother 1 U day day W δ In addition, the etching conditions of the interlayer emulsification 42 are not limited to this method. That is, a plurality of processing conditions are memorized in advance on the engraving device side, and the optimal conditions are selected in the main device. 10 'From these articles, in the above-mentioned embodiments J to 3, the determination of the etching conditions of the divided oxide film 42 is based on this = 3 or the interlayer oxide only ^ bath evil 4, the interlayer oxide film M is etched Θ According to the concentration of impurities contained in it. However, the beauty of the etching conditions of the interlayer oxide film 42 is not as good as the sintering oxide 33 and ^ 'Λ ric. The earth is not limited to the calculated charm 4. Impurity concentration For example, the separation of the rhinoceros or the piece of the phoenix from the temple of Oxan can also be based on the silver carved strips of the refraction of these films. Embodiment 5. The purpose of Embodiment 5 of the present invention will be described with reference to FIG. 7 below. Good fine. Also ~ fine wiring diagram
C:\2D-C0DE\90-09\90116345.ptd 第19頁 507266 五、發明說明（16) 型。在本實施形態中，在半導 以 下所示之處理。 < 表仏過私’貫行 如圖7(A)所示，在石夕其拓qi 膜48。配線層46例如以；雜 ：：：=:和氧化 金屬材料形成。在氧化膜48之卜 次鎢或鎢矽化物等之 抗：劑膜使其成為比所欲形成之微細= 作 刻=後以遮罩’對氧化膜48進行式餘 ^…、後利用軋電漿處理等除去殘留在氧化膜48夕 抗姓劑膜50。其結果是形成圖7⑻所示之狀態。、 ，次备*圖7(〇所示，利用濕式蝕 ： ‘小。氧化膜48經由如上所述之縮 形 實現會有困難之微細之圖型。 成為要以乾式蝕刻 線=D-):r以微細化後之氧化膜48作為遮罩，對配 ，曰46進仃乾式蝕刻。其結果是在矽基板31C: \ 2D-C0DE \ 90-09 \ 90116345.ptd Page 19 507266 5. Description of the invention (16) type. In this embodiment, the processing shown below the semiconductor is performed. < Performance of Superficial Privateness ' As shown in Fig. 7 (A), a film 48 is formed in Shi Xiqi. The wiring layer 46 is formed of, for example, :::: = and an oxidized metal material. Resistance of the tungsten film or tungsten silicide in the oxide film 48: the agent film makes it finer than what is desired to be formed = engraved = after masking the oxide film 48 ^ ... The anti-surname agent film 50 remaining on the oxide film 48 is removed by a slurry treatment or the like. As a result, the state shown in FIG. 7 (a) is formed. Figure 7 (shown as 0, using wet etching: 'small. The fine pattern of the oxide film 48 will be difficult to achieve through the shrinkage as described above. It will become a dry etching line = D-) : r Uses the finely oxidized oxide film 48 as a mask, and it is paired with 46, which is dry etching. The result is on the silicon substrate 31
細之圖型之配線52。 ❿风，、有U 右二Ιίΐ步驟形成之配線52產生尺寸誤差之因素主要的 ;)利用照相製版形成之抗蝕劑膜50之尺寸誤差，和 + 1由/乾式姓刻時產生侧向蝕刻所造成之氧化膜48之尺 。在本實施形態中，為著使最後之配線5 2之尺寸以 良好=精確度成為所希望之值，所以利用以下所示之方法 用來校正抗蝕劑膜5〇和氧化膜48之尺寸誤差。 ^ ^在本貫施形態中，如圖7 ( Β)所示，利用照相製版 杬蝕劑膜50，以抗蝕劑膜5〇作為遮罩，進行氧化膜48 之乾式蝕刻，和完成抗蝕劑膜5〇之除去之後，進行被圖型 C:\2D-CQDE\90-09\90116345.ptd 第20頁 507266 ίι1丨丨 圓 五、發明說明（17) f作之氧化膜48之尺寸測定。然後，利用前饋 m'!之測定值反映在氧化膜48之濕式蝕刻條件。； 即，在本實施形態中，在除去抗蝕劑膜5〇n 5 二匕㈣之尺寸之尺寸測定裝置與圖!所示之：用= 另夕卜，對氧化賴進行濕式㈣之濕 ； 上述之控制對象處理裝置！ 4相當。 』裝置與 依照本實施形態之製造系統時， =尺寸測定裝置(測定裝置12)測定二前將 I二=值發訊到主電腦10，與被測定晶圓之 起s己錄在測疋值記憶器20。另外’在該晶 f 程之階段，濕式蚀刻裝置（控制對象處理裝置丨-二 電月尚10要求最佳條件之發訊。然後 接 收決定部24，將根據氧化膜48之尺寸斯也〜，細10之接 定作為濕式蝕刻裝置之處理條件❶然’、二：最：：：設 氧化膜48進行濕式蝕刻。 ，、後以最佳條件對 依照上述之製造方法時，可以利用濕式蝕刻用 …由於側向姓刻所造成之氧化膜 時，可以：好製造方法或製造系統 以高良率製^質穩；以微細之配線52’可以 個f ί施形態5 ’ ’在每-個晶圓設定ID，在每一 :二固=化膜48之赚刻條件，但是本發明並不只 亦'p ’亦可以以批單位設定id，以批單位 设疋廣式蚀刻之條件。 干m 第21頁 讀 C: \2D-®DE\90-09\90116345. ptd )υ7266 五、發明說明（18) 另外’在上述之實施形態5中，在主電腦丨〇之内部設定 處理條件，將該條件從主電腦】0發訊到濕式蝕刻裝置（控 制對象處理裝置1 4 )，但是本發明並不只限於此種方式。 亦即，亦可以在濕式蝕刻裝置側預先記憶多個處理條件， 在主電腦1 〇從該等之條件中選擇最佳之條件。 life幵1態6 · 下面胃將參照圖8用來說明本發明之實施形態6。 圖8是^方塊圖，用來說明本實施形態之製造系統之特徵 ;卜：ί I:: ί、之製造系統，除了實施形態5之製造系統 更八備有圖8所示之接收校正部54和經過時間管理 。接收校正部54和經過時間管理部56可以配置在主電腦 何^ ^ 卩和濕式蝕刻裝置之内部（處理裝置1 4之内部）之任 更d: ϋ :;56用t計數從濕式#刻裝置内之藥液被 間，用來^、、晶二°丨$外’接收校正部54依照該經過時 液隨接收進行校正。濕式㈣之藥 蝕刻速度隨著荦r夕過而變質。另夕卜，濕式蝕刻之 以良變質而變化…，要利用濕式姓刻 /月萑度餘刻氧化膜4 8時，可以佑驢苗 經過時間，用來；4 ^ μ 了以依照樂液更換後之 依照本實：idr;條Γ。 膜48之尺寸，用來4 σ以根據乾式蝕刻後之氧化 更換後之經過時η ^ I ζ刻之條件，和可以根據藥液 態之製造系統==正=二^ 田，、只％形態5之情況比較Fine patterned wiring 52. The main factors that cause the dimensional error of the wiring 52 formed by the U right two steps are:) The dimensional error of the resist film 50 formed by photoengraving, and the lateral etching when +1 is made by / dry type. The resulting scale of the oxide film is 48 feet. In this embodiment, in order to make the size of the last wiring 5 2 good = accurate, a desired value is used, so the method shown below is used to correct the size error of the resist film 50 and the oxide film 48. . ^ ^ In this embodiment, as shown in FIG. 7 (B), dry etching of the oxide film 48 is performed using the photoresist film 50 with the resist film 50 as a mask, and the resist is completed. After removal of the agent film 50, the size of the oxide film 48 made by the pattern C: \ 2D-CQDE \ 90-09 \ 90116345.ptd page 20 507266 is described in the fifth aspect of the invention (17) f. . Then, the measured value using the feedforward m ′! Is reflected in the wet etching conditions of the oxide film 48. That is, in this embodiment, the size measurement device and the figure of the size of the resist film 50n 5 are removed. As shown in FIG. ; The above-mentioned control target processing device! 4 is quite. "When the device and the manufacturing system according to this embodiment, = the size measuring device (measurement device 12) sends the value of I2 = to the host computer 10 before the second measurement, and s is recorded in the measured value from the measured wafer. Memory 20. In addition, at the stage of the crystal process, a wet etching device (control target processing device 丨 -Electricity Co., Ltd. 10 requires the best conditions to be sent. Then the receiving decision unit 24 will determine the size of the oxide film 48. The fine 10 is set as the processing condition of the wet etching device. The second is the most: The wet etching is performed with the oxide film 48. When the manufacturing method according to the above is used under the best conditions, it can be used. For wet etching ... When the oxide film is caused by the lateral name engraving, it can be: good manufacturing method or manufacturing system with high yield ^ stable quality; with fine wiring 52 'can be applied 5 ′ 5 Each wafer is set with an ID, and the conditions for each engraving = chemical film 48 are engraved, but the present invention is not limited to setting the id in batch units and the conditions for wide-type etching in batch units. Dry m page 21 Read C: \ 2D-®DE \ 90-09 \ 90116345. Ptd) υ7266 V. Description of the invention (18) In addition, in the fifth embodiment described above, the processing conditions are set inside the host computer. Send the condition from the host computer] to the wet etching device (control Processing apparatus 14), but the present invention is not limited to this embodiment. That is, a plurality of processing conditions may be memorized in advance on the side of the wet etching apparatus, and the host computer 10 may select an optimal condition from among these conditions. Life 幵 1 State 6 · The stomach will be used to explain Embodiment 6 of the present invention with reference to FIG. 8. FIG. 8 is a block diagram for explaining the characteristics of the manufacturing system of this embodiment; I :: The manufacturing system of FIG. 8 is provided with a receiving correction unit shown in FIG. 8 in addition to the manufacturing system of Embodiment 5. 54 and elapsed time management. The reception correction section 54 and the elapsed time management section 56 may be arranged in the host computer and the interior of the wet etching apparatus (the interior of the processing apparatus 14). D: ϋ: 56 The medicinal solution in the engraving device is used for receiving and correcting by the receiving correction section 54 according to the elapsed time and receiving correction. Wet-type medicine The etching rate deteriorates with the passage of time. In addition, the wet etching changes with good deterioration ... To use the wet name engraving / monthly degree to etch the oxide film 4 8 o'clock, you can use the donkey seedlings to elapse time to use; 4 ^ μ to follow the music After the replacement of the liquid, it is in accordance with this reality: idr; Article Γ. The size of the film 48 is used for 4 σ according to the condition of η ^ I ζ engraved according to the elapsed time after the oxidation after dry etching, and can be based on the manufacturing system of the drug liquid == positive = two ^ field, only% form 5 Compare the situation
I 第22頁 C:\2D-roDE\9〇.〇9\90116345.ptd 507266 五、發明說明（19) 時在：=ϊ Ϊ好之精確度圖型製作配線5 2。 f 述之貝轭形態6中，利用前饋之 士氧化膜48之尺寸反映在氧化膜48之/乞式钱刻後 樂液更換後之經過時間反映在上述之濕'二=條件，和使 該兩種方法之組合’但是本發明並條件’使用 即：根據藥液更換後之經過時間用來;方式。亦 之方法，亦可以與根據氧化膜48之尺寸刻之條件 之方法分離，可以單獨的使用。 又，“、、式蝕刻條件 d次濕式蝕刻）之處理，亦可以以 I知式蝕 件，但是可利用前饋校正之處理^饋之方法权正其條 例如，亦可以利用’於夕士、並不只限於此處所述者。 CMP之條件等。月貝 法用來校正成膜處理之條件或 [發明之效果] ΐ t::i以i述方式構成’所以具有以下所之效果。 方範圍第1或11項時，利用前饋之 理條件。因此，：昭之狀？反映在該晶圓之處 之半導體裝置。，、χ 以高良率製造品質穩定 可以使被處 ，依照本發明 =知本發明之中請專利範圍第2或^ 2項時， =之物理量反映在該膜之钱刻條件。因此 守二：良好之精確度進行被處理膜之蝕刻。 ^發明之申請專利範圍第3或13項時，可以使被處 膜之膜厚反映在蝕刻條件。因此，依照本發明時，可以I Page 22 C: \ 2D-roDE \ 9〇.〇9 \ 90116345.ptd 507266 V. Description of the invention (19) At: = ϊ Ϊ Good accuracy pattern production wiring 5 2. f. In the yoke form 6 described above, the size of the feedforward oxide film 48 is reflected in the oxide film 48 / beginning money after the music fluid is replaced. The elapsed time is reflected in the above wet conditions. The combination of these two methods 'but the present invention does not apply to conditions', that is, according to the elapsed time after the replacement of the liquid medicine; Alternatively, the method may be separated from the method according to the size of the oxide film 48, and may be used alone. In addition, ", and etching conditions d times wet etching) processing can also be I-type etching, but the feed forward correction processing can be used ^ feed method is justified, for example, you can also use '于 夕It is not limited to those described here. The conditions of CMP, etc. The scallop method is used to correct the conditions of the film formation process or [effect of the invention] ΐ t :: i is constituted in the manner described above, so it has the following effects When the item 1 or 11 of the square range is used, the feed-forward rationale is used. Therefore, "Zhao Zong?" Is a semiconductor device reflected on the wafer., Χ Manufacturing with high yield and stable quality can make it work, according to this Invention = When knowing the second or second item of the patent scope of the present invention, the physical quantity of = is reflected in the film's engraving conditions. Therefore, Shou 2: Good etching of the treated film. ^ Patent application for invention When the range is 3 or 13, the thickness of the film to be treated can be reflected in the etching conditions. Therefore, according to the present invention,
第23頁 \\312\2d-code\90-09\90l16345.ptd 507266 無關的 之申請 質濃度 質濃度 精確度 之申請 反映在 不同所 被處理 之申請 #刻條 刻之尺 至所希 之申請 對應之 五、發明說明（20) 與膜厚之變動 依照本發明 理膜所含之雜 時，可以與雜 的，以良好之 依照本發明 理膜之折射率 以與折射率之 之精碟度餘刻 依照本發明 之尺寸反映在 刻處理開始時 被處理膜縮小 依照本發明 決定與測定值 置。 依照本發明 之内部決定與 依照本發明 液之狀態校正 以與藥液之變 進行濕式蝕刻 另外，依照 有能夠以高良 ’以良 專利範 反映在 之不同 I虫刻被 專利範 蝕刻條 引起之 膜。 專利範 件。因 寸之不 望之尺 專利範 處理條 之申請專利範 測定值對應之 之申請專利範 濕式蝕刻之條 質無關的，經 〇 本發明時，可 率製造之特性 好之精確度餘刻被處理膜。 圍第4或14項時，可以使被處 蝕刻條件。因此，依照本發明 所引起之蝕刻速度不同益關 處理膜。 圍第5或1 5項時，可以使被處 件。因此，依照本發明時，可 蝕刻速度不同無關的，以良好 圍第6項時，可以使被處理膜 此，依照本發明時，可以與蝕 2無關的，以良好之精確度將 T 0 :第7項日夺，可以在主電腦内 ，將該條件設定在處理裝 ^第8項時’可以在處理裝置 處理條件。 ^第9或10項日寺，可以依照藥 ^因此’依照本發明時，可 吊以良好之精確度對被處理膜 :T現具有穩定之品質，和且 之半導體裝置。 八Page 23 \\ 312 \ 2d-code \ 90-09 \ 90l16345.ptd 507266 Irrelevant applications Mass concentration Mass concentration accuracy applications are reflected in the different applications being processed #etched carved ruler to the desired application Corresponding Fifth, the description of the invention (20) and the change of the film thickness According to the impurities contained in the physical film of the present invention, it can be mixed with the good, the refractive index of the physical film according to the present invention, and the precision of the refractive index. The size of the remaining moment according to the present invention reflects the shrinkage of the film to be treated at the beginning of the engraving process and is determined and set according to the present invention. According to the internal decision of the present invention and the correction of the state of the liquid according to the present invention to perform wet etching with the change of the chemical liquid. In addition, according to the fact that it can be reflected in Gaoliang 'Yiliang patent scope, it is caused by the patent etched strip. membrane. Patent Model. Due to the size of the unseen ruler, the measured value of the patent application process corresponds to the quality of the patent application wet etching, which is irrelevant. After the present invention, the accuracy of the good manufacturing characteristics can be etched in a moment. Treatment film. If it is around item 4 or 14, the etching conditions can be adjusted. Therefore, the difference in etching speed caused by the present invention is related to the treatment film. If it is surrounded by items 5 or 15, it can be treated. Therefore, according to the present invention, the etchable speed is different regardless of the etch rate. When the item 6 is good, the film to be treated can be made. According to the present invention, the etch 2 can be made independent of T2 with good accuracy: For the seventh item, the condition can be set in the processing device in the host computer. When the eighth item is used, the condition can be processed in the processing device. ^ The 9th or 10th temple, according to the medicine ^ Therefore, according to the present invention, the processed film can be suspended with good accuracy: T now has a stable quality, and the semiconductor device. Eight
507266 五、發明說明（21) [元件 •編號 之 說 明 ] 10 主 電 腦 12 測 定 裝 置 14 處 理 裝 置 16 測 定 值 收 訊 部 18 測 定 值 記 憶 部 20 測 定 值 記 憶 器 22 ID 收 訊 部 24 接 收 決 定 部 26 接 收 發 訊 部 31 矽 基 板 33 分 離 氧 化 膜 38 閘 極 電 極 40 電 容 器 電 極 42 層 間 氧 化 膜 44, 5C 丨抗 蝕 劑 膜 46 配 線層 48 氧 化 膜 52 配 線 54 接 收 校 正 部 56 經 過 時 間 管 理部507266 V. Description of the invention (21) [Description of components and numbers] 10 Host computer 12 Measuring device 14 Processing device 16 Measured value receiving section 18 Measured value storage section 20 Measured value memory 22 ID Receiving section 24 Receiving decision section 26 Receiving and transmitting section 31 Silicon substrate 33 Separate oxide film 38 Gate electrode 40 Capacitor electrode 42 Interlayer oxide film 44, 5C 丨 Resist film 46 Wiring layer 48 Oxide film 52 Wiring 54 Receive correction section 56 Elapsed time management section
C:\2D-C0DE\90-09\90116345.ptd 第25頁 507266 圖式簡单說明 圖1是方塊圖，用來說明本發明之實施形態1之製造系統 之構造。 圖2 (A )、（ B)是剖面圖和流程圖，用來說明本發明之實 施形態1之製造方法。 圖3 (A )、（ B)是剖面圖和流程圖，用來說明本發明之實 施形態2之製造方法。 圖4 (A )、（ B)是剖面圖和流程圖，用來說明本發明之實 施形態3之製造方法。 圖5 (A )、（ B)是剖面圖和流程圖，用來說明本發明之實 施形態4之製造方法。 圖6表示蝕刻速度和雜質濃度之關係。 圖7 ( A )〜（E )是剖面圖和流程圖，用來說明本發明之實 施形態5之製造方法。 圖8是方塊圖，用來說明本發明之實施形態6之製造系統 之構造。C: \ 2D-C0DE \ 90-09 \ 90116345.ptd Page 25 507266 Brief Description of Drawings Figure 1 is a block diagram for explaining the structure of a manufacturing system according to the first embodiment of the present invention. Figs. 2 (A) and (B) are sectional views and flowcharts for explaining the manufacturing method of the first embodiment of the present invention. Figs. 3 (A) and (B) are sectional views and flowcharts for explaining the manufacturing method of the second embodiment of the present invention. 4 (A) and 4 (B) are sectional views and flowcharts for explaining the manufacturing method of the third embodiment of the present invention. 5 (A) and 5 (B) are sectional views and flowcharts for explaining the manufacturing method of the fourth embodiment of the present invention. FIG. 6 shows the relationship between the etching rate and the impurity concentration. 7 (A) to (E) are sectional views and flowcharts for explaining the manufacturing method of the fifth embodiment of the present invention. Fig. 8 is a block diagram for explaining the structure of a manufacturing system according to a sixth embodiment of the present invention.
\\312\2d-code\90-09\90116345.ptd 第26頁\\ 312 \ 2d-code \ 90-09 \ 90116345.ptd Page 26
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000349027A JP4437611B2 (en) | 2000-11-16 | 2000-11-16 | Manufacturing method of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| TW507266B true TW507266B (en) | 2002-10-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW090116345A TW507266B (en) | 2000-11-16 | 2001-07-04 | Method and system for manufacturing semiconductor device |
Country Status (4)
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| US (1) | US20020056700A1 (en) |
| JP (1) | JP4437611B2 (en) |
| KR (1) | KR100437221B1 (en) |
| TW (1) | TW507266B (en) |
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| AU2003278750A1 (en) * | 2002-08-28 | 2004-03-19 | Tokyo Electron Limited | Method and system for dynamic modeling and recipe optimization of semiconductor etch processes |
| US6842661B2 (en) * | 2002-09-30 | 2005-01-11 | Advanced Micro Devices, Inc. | Process control at an interconnect level |
| US7265382B2 (en) * | 2002-11-12 | 2007-09-04 | Applied Materials, Inc. | Method and apparatus employing integrated metrology for improved dielectric etch efficiency |
| JP2004319574A (en) * | 2003-04-11 | 2004-11-11 | Trecenti Technologies Inc | Method of manufacturing semiconductor device, method and system for automatically operating semiconductor manufacturing device, and method of automatically operating cmp device |
| US8257546B2 (en) * | 2003-04-11 | 2012-09-04 | Applied Materials, Inc. | Method and system for monitoring an etch process |
| JP2007500941A (en) * | 2003-07-31 | 2007-01-18 | エフエスアイ インターナショナル インコーポレイテッド | Controlled growth of highly uniform oxide layers, especially ultrathin layers |
| EP1663534A1 (en) * | 2003-09-11 | 2006-06-07 | FSI International, Inc. | Acoustic diffusers for acoustic field uniformity |
| WO2005027202A1 (en) * | 2003-09-11 | 2005-03-24 | Fsi International, Inc. | Semiconductor wafer immersion systems and treatments using modulated acoustic energy |
| JP4305401B2 (en) * | 2005-02-28 | 2009-07-29 | セイコーエプソン株式会社 | Semiconductor device |
| JP2006245036A (en) * | 2005-02-28 | 2006-09-14 | Seiko Epson Corp | Forming method of element isolation layer, manufacturing method of electronic device, and cmp apparatus |
| US7596421B2 (en) | 2005-06-21 | 2009-09-29 | Kabushik Kaisha Toshiba | Process control system, process control method, and method of manufacturing electronic apparatus |
| US8070972B2 (en) * | 2006-03-30 | 2011-12-06 | Tokyo Electron Limited | Etching method and etching apparatus |
| JP4990548B2 (en) | 2006-04-07 | 2012-08-01 | 株式会社日立製作所 | Manufacturing method of semiconductor device |
| JP5076426B2 (en) | 2006-09-29 | 2012-11-21 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
| JP4971050B2 (en) | 2007-06-21 | 2012-07-11 | 株式会社日立製作所 | Semiconductor device dimension measuring device |
| JP5401797B2 (en) | 2008-02-06 | 2014-01-29 | 富士通セミコンダクター株式会社 | Semiconductor device manufacturing method and semiconductor device manufacturing system |
| JP2010087300A (en) * | 2008-09-30 | 2010-04-15 | Toshiba Corp | Method of manufacturing semiconductor device |
| JP5853382B2 (en) * | 2011-03-11 | 2016-02-09 | ソニー株式会社 | Semiconductor device manufacturing method and electronic device manufacturing method |
| US9005464B2 (en) * | 2011-06-27 | 2015-04-14 | International Business Machines Corporation | Tool for manufacturing semiconductor structures and method of use |
| CN104409348B (en) * | 2014-11-10 | 2017-08-08 | 成都士兰半导体制造有限公司 | The preparation method of trench device |
| US11538921B2 (en) * | 2017-05-15 | 2022-12-27 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device |
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| JPS6060731A (en) * | 1983-09-14 | 1985-04-08 | Hitachi Ltd | Manufacture of semiconductor device |
| US5399229A (en) * | 1993-05-13 | 1995-03-21 | Texas Instruments Incorporated | System and method for monitoring and evaluating semiconductor wafer fabrication |
| KR19980014172A (en) * | 1996-08-08 | 1998-05-15 | 김광호 | Method of overlay measurement of semiconductor manufacturing process |
| JP2867982B2 (en) * | 1996-11-29 | 1999-03-10 | 日本電気株式会社 | Semiconductor device manufacturing equipment |
| US6148239A (en) * | 1997-12-12 | 2000-11-14 | Advanced Micro Devices, Inc. | Process control system using feed forward control threads based on material groups |
| KR100251279B1 (en) * | 1997-12-26 | 2000-04-15 | 윤종용 | Method for controlling a thickness of a layer deposited in a semiconductor fabricating equipment |
| KR100382021B1 (en) * | 2000-02-03 | 2003-04-26 | 가부시끼가이샤 도시바 | Semiconductor device manufacturing method, manufacturing support system and manufacturing apparatus for manufacturing the same |
-
2000
- 2000-11-16 JP JP2000349027A patent/JP4437611B2/en not_active Expired - Fee Related
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2001
- 2001-04-05 US US09/826,038 patent/US20020056700A1/en not_active Abandoned
- 2001-07-04 TW TW090116345A patent/TW507266B/en not_active IP Right Cessation
- 2001-07-12 KR KR10-2001-0041821A patent/KR100437221B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US20020056700A1 (en) | 2002-05-16 |
| JP2002151465A (en) | 2002-05-24 |
| JP4437611B2 (en) | 2010-03-24 |
| KR20020038458A (en) | 2002-05-23 |
| KR100437221B1 (en) | 2004-06-23 |
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