TW202018872A - Ferroelectric memory and manufacturing method thereof - Google Patents

Abstract

A ferroelectric memory is provided. The ferroelectric memory includes a substrate and one or more trench are formed the substrate. A first conductive layer, a second conductive layer, and a ferroelectric thin film layer disposed between the first conductive layer and the second conductive layer disposed on a surface of the trench. A first filling material layer, a second filling material layer and a third filling material layer disposed on the second conductive layer. The second filling material layer of a thermal expansion coefficient is more than the first filling material layer and the third filling material layer of the thermal expansion coefficient. When the ferroelectric thin film layer is subjected to heat treatment process to form a crystalline state, and a compressive stress is applied to the ferroelectric thin film layer by the first filling material layer, the second filling material layer, and the third filling material layer in response to heat treatment expansion characteristics. The invention further a ferroelectric memory of manufacturing method is provided.

Description

Ferroelectric memory and its manufacturing method

The invention relates to a ferroelectric memory and a manufacturing method thereof.

In non-volatile memory, it is difficult to shrink the floating gate (Floating Gate) flash memory or the metal/oxide/nitride/oxide/silicon (MONOS) flash memory. Therefore, there is a constant search for miniaturization using different operating principles from these memories. Such as ferroelectric random access memory (FeRAM), resistance random access memory (ReRAM), phase change random access memory (PCRAM), magnetic random access memory (MRAM) or three-dimensional memory have been used. Among these memories, in FeRAM, such as FeFET (ferroelectric field effect transistor), FTJ (ferroelectric tunnel structure), chain-type FeRAM (ferroelectric random access memory) and other ferroelectric memory, such as the use of lead-containing ferroelectric memory It is difficult to reduce the thickness.

In a deadlock like FeRAM, a ferroelectric film that does not contain lead is easy to manufacture, and low-voltage operation enables long-term recording. Therefore, it is possible to use a hafnium oxide film to realize a ferroelectric memory with a large capacity.

The purpose of the present invention is to use two kinds of fillers with different thermal expansion coefficients during the heat treatment process of the ferroelectric materials to produce deformation due to the different thermal expansion coefficients, to apply a compressive stress to the ferroelectric materials, so that the ferroelectric materials undergo pressure and After the temperature is rearranged, the ferroelectric Sex has thus been greatly improved.

The invention provides a ferroelectric memory, including a substrate, and a groove is formed on the substrate, a first conductive layer and a second conductive layer are provided on the surface of the groove, and the first conductive layer and the A ferroelectric thin film layer between the second conductive layers, a first filling material layer, a second filling material layer and a third filling material layer stacked on the second conductive layer, the thermal expansion coefficient of the second filling material layer is greater than the A coefficient of thermal expansion of a filler material layer and a third filler material layer; and when the ferroelectric thin film layer undergoes heat treatment to form a crystalline state, the first filler material layer, the second filler material layer, and the third filler material layer are subjected to heat treatment The expansion characteristic applies a compressive stress to the ferroelectric thin film layer.

The heat treatment temperature is 200°C-900°C, preferably 300°C-600°C.

Preferably, the material of the first filling material layer and the third filling material layer is titanium nitride or titanium with a small thermal expansion coefficient, and the material of the second filling material layer is tantalum nitride with a large thermal expansion coefficient material. The material thermal expansion coefficient of the second filling material layer is greater than the material thermal expansion coefficients of the first filling material layer and the third filling material layer.

Preferably, during heat treatment, the second sandwich structure formed by the first filling material layer, the second filling material layer and the third filling material layer, the first conductive layer, the ferroelectric thin film layer and the The first sandwich structure of the second conductive layer forms pressure and applies pressure to the ferroelectric thin film layer.

The invention also provides a method for manufacturing a ferroelectric memory. The steps include: providing a substrate; forming a first oxide layer on the substrate, forming a metal layer on the first oxide layer, and patterning to form a lower electrode; forming A second oxide layer is formed on the lower electrode, and one or more trenches are formed in the second oxide layer; a first conductive layer, a ferroelectric thin film layer and a second conductive layer are formed On the surfaces of the trench and the second oxide layer, the first conductive layer is in contact with the lower electrode; a first filling material layer, a second filling material layer and a third filling material layer are formed on the first On the two conductive layers; and forming an upper electrode on the third filling material layer, and performing heat treatment.

Preferably, a second oxide layer is formed on the lower electrode and the first oxide layer at a low temperature.

Preferably, the step of the present invention further includes a step of grinding the second oxide layer to planarize it.

Preferably, the manufacturing steps of the first conductive layer, the ferroelectric thin film layer and the second conductive layer are: the first conductive layer is formed on the surface of the trench, and the ferroelectric thin film layer is formed on the first On the surface of the conductive layer, the second conductive layer is formed on the surface of the ferroelectric thin film layer so that the first conductive layer can be in contact with the lower electrode.

Preferably, the manufacturing steps of the first filling material layer, the second filling material layer and the third filling material layer are: the first filling material layer is formed on the surface of the second conductive layer, and the second filling The material layer is formed on the surface of the first filling material layer, and the third filling material layer is formed on the surface of the second filling material layer and fills the trench.

Preferably, the material of the first filling material layer and the material of the third filling material layer may be the same or different, wherein the material of the second filling material layer has a coefficient of thermal expansion greater than that of the first filling material layer and the third filling material The material thermal expansion coefficient of the material layer.

Preferably, the heat treatment temperature is 200°C-900°C, preferably 300°C-600°C.

Preferably, the steps of the present invention further include the upper electrode, the first conductive layer, the ferroelectric thin film layer and the second conductive layer and the first filling material layer, the first on the surface of the second oxide layer A gap wall is formed between the two filling material layers and the two sides of the third filling material layer, the gap The material of the wall is silicon dioxide.

Preferably, the steps of the present invention further include: forming an upper metal layer on the uppermost surface; patterning to form a metal pad on the upper end surface of the via hole, and forming an upper metal pad above the upper electrode and the spacer.

10‧‧‧ substrate

12‧‧‧Groove

14‧‧‧The first sandwich structure

142‧‧‧The first conductive layer

144‧‧‧Ferroelectric thin film layer

146‧‧‧Second conductive layer

16‧‧‧Second sandwich structure

162‧‧‧First filling material layer

164‧‧‧Second filling material layer

166‧‧‧third filling material layer

102‧‧‧ substrate

104‧‧‧First oxide layer

106‧‧‧Metal layer

108‧‧‧Lower electrode

110‧‧‧second oxide layer

112‧‧‧Groove, hole

114‧‧‧Upper electrode

116‧‧‧Gap

118‧‧‧Guide hole

120‧‧‧Metal pad

122‧‧‧Upper metal pad

Figure 1 is a schematic side sectional view of the ferroelectric memory of the present invention.

2A-2K are schematic diagrams of the manufacturing process of the ferroelectric memory of the present invention.

This section describes the best way to implement the present invention, the purpose is to illustrate the spirit of the present invention and not to limit the scope of protection of the present invention, the scope of protection of the present invention shall be subject to the scope of the attached patent application shall prevail .

Please refer to FIG. 1, which is a schematic side sectional view of the ferroelectric memory of the present invention. The ferroelectric memory of the present invention includes a substrate 10, and a groove 12 is formed on the substrate 10. The material of the substrate 10 may be silicon dioxide material (SiO ₂ Material). A first conductive layer 142 and a second conductive layer 146 and a ferroelectric thin film layer 144 between the first conductive layer 142 and the second conductive layer 146 are sequentially formed on the surface of the trench 12 to form a first three Meiji structure 14. A first filling material layer 162, a second filling material layer 164, and a third filling material layer 166 are sequentially stacked on the second conductive layer 146 to form a second sandwich structure 16. The thermal expansion coefficient of the second filling material layer 164 is greater than the thermal expansion coefficients of the first filling material layer 162 and the third filling material layer 166. The present invention utilizes the first filling material layer 162, the second filling material layer 164, and the first The second sandwich structure 16 of the three-filled material layer 166 encounters thermal expansion characteristics and adds a compressive stress to the ferroelectric thin film layer 144 to increase its ferroelectric properties.

Since the materials of the first filling material layer 162 and the third filling material layer 166 and the second filling material layer 164 have different thermal expansion coefficients, deformation will occur during the heat treatment process and there will be a compressive stress on the ferroelectric material layer 144 Through the heat treatment and a compressive stress, the ferroelectric thin film layer 144 further increases its ferroelectric properties.

The materials of the first conductive layer 142 and the second conductive layer 146 may be titanium nitride (TiN), tantalum nitride (TaN), titanium tungsten (TiW), hafnium nitride (HfN), zirconium nitride (ZrN) ), tantalum aluminum nitride (TaAlN), tungsten aluminum nitride (WAlN), hafnium aluminum nitride (HfAlN), zirconium aluminum nitride (ZrAlN) and other metals.

The material of the ferroelectric thin film layer 144 may be hafnium zirconium oxide (HfZrOx), strontium titanium oxide (SrTiOx), strontium calcium titanium oxide (SrCaTiOx), silver niobium tantalum oxide (Ag(Nb1-xTax) Ox), barium strontium titanium oxide (BaSrTiO3), barium titanium oxide (BaTiO3), etc.

The material of the first filling material layer 162 and the third filling material layer 166 may be a material with a small thermal expansion coefficient (TEC) such as titanium nitride (TiN), titanium (Ti), and the second filling material The material of the layer 164 may be a material with a large thermal expansion coefficient (TEC) such as tantalum nitride (TaN). The first sandwich structure 14 of the first conductive layer 142, the ferroelectric thin film layer 144 and the second conductive layer 146 is pressed by heat treatment.

In the present invention, when the ferroelectric thin film layer 144 undergoes heat treatment to form a crystalline state, filler materials (such as the second filler material layer 162, the second filler material layer 164, and the third filler material layer 166 are used Governance structure 16) Directly apply vertical pressure to the 144 layer of the ferroelectric thin film in order to increase its ferroelectric characteristics in case of thermal expansion. The crystalline state is, for example, Pbc2.

The material thermal expansion coefficient of the second filler material layer 164 is greater than that of the first filler material The material thermal expansion coefficients of the material layer 162 and the third filling material layer 166. The material of the first filling material layer 162 and the material of the third filling material layer 166 may be the same or different.

The present invention is an improved invention of a vertical metal layer/insulating layer/metal layer (MIM) ferroelectric memory (vertical MIM FeRAM), which is pointed out in the literature (Effect of external stress on polarization in ferroelectric tin films, APL (1998)) Applying a compressive stress (Compress stress) to the ferroelectric material will help its ferroelectric properties, so the ferroelectric materials will get good ferroelectric properties after a stack of heat treatment. When the second sandwich structure 16 composed of the first filling material layer 162, the second filling material layer 164 and the third filling material layer 166 is heat-treated, the first conductive layer 142 and the ferroelectric thin film The layer 144 forms pressure with the first sandwich structure 14 of the second conductive layer 146, and at the same time, it also applies pressure to the ferroelectric thin film layer 144, so that better ferroelectric characteristics can be obtained.

Since the ferroelectric thin film layer 144 is a stress-sensitive material, and its characteristics are different due to the stress of various thin films formed on the upper part of the ferroelectric capacitor, its crystal lattice arrangement is different. When stress in the compression direction is applied to the ferroelectric thin film layer 144, characteristics such as leakage current and residual dielectric polarization are improved.

Please refer to FIGS. 2A-2K for a schematic diagram of the manufacturing process of the ferroelectric memory of the present invention. As shown in FIG. 2A, a first oxide layer 104, such as silicon dioxide, is formed on a silicon wafer substrate 102 (SiO ₂ ), the first oxide layer 104 is formed in a furnace tube. Next, a metal layer 106 is formed on the first oxide layer 104, and the metal layer 106 is, for example, Ti/TiN.

As shown in FIG. 2B, the metal layer 106 is covered with a first photomask layer (not shown in the figure, the photomask layer is not shown in the drawings below), and the metal layer 106 is patterned to make the metal Layer 106 forms lower electrode 108. Then the first mask layer is removed.

As shown in FIG. 2C, a second oxide layer 110 (Low Temperature Oxide Department, LTO Dep.) is formed on the lower electrode 108 and the first oxide layer 104 at a low temperature. The second oxide layer 110 may be silicon dioxide (SiO ₂ ), silicon oxide (SiOx), or the like. As shown in FIG. 2D, the second oxide layer 110 is polished to be planarized.

As shown in FIG. 2E, the second oxide layer 110 after being planarized is covered with a second photomask layer, and the second oxide layer 110 is dry-etched to etch one or more trenches 112 (Trench ), or one or more holes 112 (Hole pattemed) are patterned in the second oxide layer 110. The trench 112 or the hole 112 is located on the lower electrode 108. In the following, the groove 112 is used for representative description. Next, the second mask layer is removed.

As shown in FIG. 2F, a first sandwich structure 14 of a first conductive layer 142, a ferroelectric thin film layer 144, and a second conductive layer 146 is formed on the surface of the trench 112 and the second oxide layer 110 on. The first sandwich layer 14 of the first conductive layer 142, the ferroelectric thin film layer 144, and the second conductive layer 146 may be formed by forming the first conductive layer 142 on the surface of the trench 112, and then, The ferroelectric thin film layer 144 is formed on the surface of the first conductive layer 142, and then the second conductive layer 146 is formed on the surface of the ferroelectric thin film layer 144. This step can be made by ALD (atomic layer chemical vapor deposition), CVD (chemical vapor deposition), PVD (physical vapor deposition) and other methods. Therefore, the first conductive layer 142 may be in contact with the lower electrode 108. A first filling material layer 162, a second filling material layer 164 and a third are formed on the first sandwich layer 14 of the first conductive layer 142, the ferroelectric thin film layer 144 and the second conductive layer 146 The second sandwich structure 16 constituted by the filling material layer 166. The manufacturing step of the second sandwich structure 16 of the first filling material layer 162, the second filling material layer 164 and the third filling material layer 166 may be that the first filling material layer 162 is formed on the second conductive layer 146 surface, and then, the second filling material layer 164 is formed on the surface of the first filling material layer 162 Then, the third filling material layer 166 is formed on the surface of the second filling material layer 164 and fills the trench. This step can be made by ALD (atomic layer chemical vapor deposition), CVD (chemical vapor deposition), PVD (physical vapor deposition) and other methods. In order to obtain better ferroelectric properties, during heat treatment, the second sandwich structure 16 formed by the first filling material layer 162, the second filling material layer 164 and the third filling material layer 166 is conductive to the first The layer 142, the first sandwich structure 14 formed by the ferroelectric thin film layer 144 and the second conductive layer 146 form a pressure, and at the same time, the pressure is also applied to the ferroelectric thin film layer 144 to achieve better ferroelectric characteristics. The material of the first filling material layer 142 and the material of the third filling material layer 146 may be the same or different.

As shown in FIG. 2G, the filler material (the second sandwich structure 16 composed of the first filler material layer 162, the second filler material layer 164, and the third filler material layer 166) is polished and planarized. However, the second sandwich structure 16 formed by the first filling material layer 162, the second filling material layer 164 and the third filling material layer 166 is not completely ground away.

As shown in FIG. 2H, the first sandwich structure 14 on the first conductive layer 142, the ferroelectric thin film layer 144, and the second conductive layer 146, the first filling material layer 162, and the second filling material An upper electrode 114 is formed on the surface of the second sandwich structure 16 formed by the layer 164 and the third filling material layer 166. A third mask layer is formed on the surface of the upper electrode 114, and after patterning, the first three layers of the upper electrode 114, the first conductive layer 142, the ferroelectric thin film layer 144 and the second conductive layer 146 are retained The second sandwich structure 16 formed by the governance structure 14, the first filling material layer 162, the second filling material layer 164 and the third filling material layer 166 protrudes from the surface of the second oxide layer 110.

As shown in FIG. 2I, the first electrode of the upper electrode 114, the first conductive layer 142, the ferroelectric thin film layer 144 and the second conductive layer 146 protruding on the surface of the second oxide layer 110 A gap 116 (Spacer) is formed on both sides of the second sandwich structure 16 formed by the governance structure 14 and the first filling material layer 162, the second filling material layer 164 and the third filling material layer 166, The material of the spacer 116 may be an oxide such as silicon dioxide. The process of the spacer 116 may be to form an oxide layer on the surface of the upper electrode 114 and the second oxide 110, and then etch the upper electrode 114 and the first on the surface of the second oxide layer 110 after etching The conductive layer 142, the ferroelectric thin film layer 144 and the second conductive layer 146 are formed by the first sandwich structure 14 and the first filling material layer 162, the second filling material layer 164 and the third filling material layer 166 The two sides of the second sandwich structure 16 form the partition wall 116.

As shown in FIG. 2J, a fourth mask layer is formed on the uppermost surface of the aforementioned structure, and a via hole 118 (Via) is formed on the position of the lower electrode 108 and on the side of the trench 112, so that The via hole 118 contacts the lower electrode 108. Remove the fourth mask layer.

As shown in FIG. 2K, an upper metal layer is formed on the uppermost surface of the aforementioned structure, and then, a fifth mask layer is formed on the surface of the upper metal layer, and a metal pad is formed on the upper surface of the via 118 by patterning 120, and an upper metal pad 122 is formed above and on both sides of the upper electrode 114 and the spacer 116. Remove the fifth mask layer.

Finally, heat treatment is performed to form the crystalline state of the ferroelectric thin film layer 144, and the expansion characteristics of the first filling material layer 162, the second filling material layer 164, and the third filling material layer 166 are heat treated to the iron The electric thin film layer 144 applies pressure, so that better ferroelectric characteristics can be obtained.

The above paragraphs use multiple levels of description. Obviously, the teachings in this article can be implemented in many ways, and any specific architecture or function disclosed in the examples is a representative situation. According to the teaching of this article, anyone who is familiar with this skill should understand that each level disclosed in this article can be independent Implementation or two or more levels can be combined and implemented.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and modifications within the spirit and scope of the present invention, so the protection of the present invention The scope shall be as defined in the appended patent application scope.

10‧‧‧ substrate

12‧‧‧Groove

14‧‧‧The first sandwich structure

142‧‧‧The first conductive layer

144‧‧‧Ferroelectric thin film layer

146‧‧‧Second conductive layer

16‧‧‧Second sandwich structure

162‧‧‧First filling material layer

164‧‧‧Second filling material layer

166‧‧‧third filling material layer

Claims (20)

A ferroelectric memory includes a substrate, and a groove is formed on the substrate, a first conductive layer and a second conductive layer are provided on the surface of the groove, and the first conductive layer and the second conductive A ferroelectric thin film layer between the layers, a first filling material layer, a second filling material layer and a third filling material layer stacked on the second conductive layer, the thermal expansion coefficient of the second filling material layer is greater than the first filling material Thermal expansion coefficients of the layer and the third filling material layer; and when the ferroelectric thin film layer undergoes heat treatment to form a crystalline state, the first filling material layer, the second filling material layer, and the third filling material layer are subjected to thermal expansion expansion characteristics A compressive stress is applied to the ferroelectric thin film layer. The ferroelectric memory as described in item 1 of the patent application range, wherein the heat treatment temperature is 200°C-900°C, preferably 300°C-600°C. The ferroelectric memory as described in item 1 of the patent application scope, wherein the material of the substrate is silicon dioxide material (SiO ₂ Material). The ferroelectric memory as described in item 1 of the patent application scope, wherein the materials of the first conductive layer and the second conductive layer are titanium nitride, tantalum nitride, titanium tungsten, hafnium nitride, zirconium nitride, Tantalum aluminum nitride, tungsten aluminum nitride, hafnium aluminum nitride, or zirconium aluminum nitride. The ferroelectric memory as described in item 1 of the patent application range, wherein the material of the ferroelectric thin film layer is hafnium zirconium oxide, strontium titanium oxide, strontium calcium titanium oxide, silver niobium tantalum oxide, barium strontium titanium oxide or barium titanium oxide . The ferroelectric memory as described in item 1 of the patent application range, wherein the material of the first filling material layer and the third filling material layer is a material with a small thermal expansion coefficient of titanium nitride or titanium, and the second filling material The material of the layer is a material with a large thermal expansion coefficient of tantalum nitride, wherein the material thermal expansion coefficient of the second filling material layer is greater than the material thermal expansion coefficients of the first filling material layer and the third filling material layer. The ferroelectric memory as described in item 1 of the patent scope, wherein the first filling material layer, the first During heat treatment, the second sandwich structure formed by the two filling material layers and the third filling material layer exerts pressure on the first sandwich structure of the first conductive layer, the ferroelectric thin film layer and the second conductive layer And apply pressure to the ferroelectric thin film layer. A method for manufacturing a ferroelectric memory, the steps of which include: providing a substrate; forming a first oxide layer on the substrate, forming a metal layer on the first oxide layer, patterning to form a lower electrode; and forming a second oxide A layer on the lower electrode and forming one or more trenches in the second oxide layer; forming a first conductive layer, a ferroelectric thin film layer and a second conductive layer on the trench and the second oxide layer On the surface, the first conductive layer is in contact with the lower electrode; forming a first filling material layer, a second filling material layer and a third filling material layer on the second conductive layer; and forming an upper electrode On the third filling material layer, heat treatment is performed. The method for manufacturing a ferroelectric memory as described in item 8 of the patent application, wherein the substrate is a silicon wafer substrate. The method for manufacturing a ferroelectric memory as described in item 8 of the patent application, wherein the first oxide layer is a silicon dioxide, and the metal layer is a titanium or a titanium nitride. The method for manufacturing a ferroelectric memory as described in item 8 of the patent application scope, wherein a second oxide layer is formed on the lower electrode and the first oxide layer at a low temperature, and the second oxide layer is silicon dioxide Or silicon oxide. The method for manufacturing a ferroelectric memory as described in item 8 of the patent application further includes a step of polishing the second oxide layer to planarize it. The method for manufacturing a ferroelectric memory as described in item 8 of the patent application, wherein the groove is located on the lower electrode. The method for manufacturing a ferroelectric memory as described in item 8 of the patent application scope, wherein the manufacturing steps of the first conductive layer, the ferroelectric thin film layer and the second conductive layer are: the first conductive layer is formed on the On the surface of the trench, the ferroelectric thin film layer is formed on the surface of the first conductive layer, and the second conductive layer is formed on the surface of the ferroelectric thin film layer so that the first conductive layer can contact the lower electrode. The method for manufacturing a ferroelectric memory as described in item 8 of the patent application scope, wherein the manufacturing steps of the first filling material layer, the second filling material layer and the third filling material layer are: A layer is formed on the surface of the second conductive layer, the second filling material layer is formed on the surface of the first filling material layer, and the third filling material layer is formed on the surface of the second filling material layer and fills the trench . The method for manufacturing a ferroelectric memory as described in item 8 of the patent application scope, wherein the material of the first filling material layer and the material of the third filling material layer may be the same or different, wherein the material of the second filling material layer The material thermal expansion coefficient is greater than the material thermal expansion coefficients of the first filling material layer and the third filling material layer. The method for manufacturing a ferroelectric memory as described in item 8 of the patent application range, wherein the heat treatment temperature is 200°C-900°C, preferably 300°C-600°C. The method for manufacturing a ferroelectric memory as described in item 8 of the patent application scope further includes the upper electrode, the first conductive layer, the ferroelectric thin film layer and the second conductive layer on the surface of the second oxide layer And the first filling material layer, the second filling material layer and the third filling material layer are formed on both sides of the gap wall, the gap wall material is silicon dioxide. A method for manufacturing a ferroelectric memory as described in item 8 of the patent application, wherein a via hole is formed at a position on the lower electrode and located on one side of the trench, so that the via hole contacts the lower electrode. The method for manufacturing a ferroelectric memory as described in item 8 of the patent application scope further includes: forming an upper metal layer on the uppermost surface; patterning to form a metal pad on the upper end surface of the via hole, and the upper electrode and An upper metal pad is formed above the partition wall.

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