US20010050423A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US20010050423A1
US20010050423A1 US09/876,396 US87639601A US2001050423A1 US 20010050423 A1 US20010050423 A1 US 20010050423A1 US 87639601 A US87639601 A US 87639601A US 2001050423 A1 US2001050423 A1 US 2001050423A1
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interconnect
cell
cells
semiconductor device
chip
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Syuuichi Kariyazaki
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Renesas Electronics Corp
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NEC Corp
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Assigned to NEC CORPORATION reassignment NEC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KARIYAZAKI, SYUUICHI
Publication of US20010050423A1 publication Critical patent/US20010050423A1/en
Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NEC CORPORATION
Priority to US12/730,336 priority Critical patent/US20100176504A1/en
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: NEC ELECTRONICS CORPORATION
Priority to US13/305,404 priority patent/US8680691B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the present invention relates to an area-array semiconductor device having arranged external electrode terminals on the bottom surface of a chip or the bottom surface of a package, and more in detail to the semiconductor device having a reduced size of the chip or the package and to increase the number of the external electrode terminals.
  • the miniaturization of the chip or the package is advanced to reduce the size of the pitch between the terminals of internal electrode terminals. Accordingly, the pitch of the interconnect pads formed on a packaging substrate or a mounting board for packaging the chip thereon is also reduced, and the reduced pitch makes it difficult to arrange the interconnects on the packaging substrate or mounting board. As a result, the miniaturization of the chip and the package is hardly realized.
  • a semiconductor device 101 as shown in FIG. 1 is an example of forming internal electrode terminals on the bottom surface of a chip 103 which is mounted on a packaging substrate 102 .
  • a plenty of ball electrodes 131 acting as external electrode terminals are arranged on the bottom surface of the chip 103 in a BGA (ball grid array) arrangement.
  • the packaging substrate 102 includes, on the top surface thereof, interconnect pads 121 corresponding to the ball electrodes 131 of the chip 103 and interconnect lines 122 for connecting the respective interconnect pads 121 .
  • packaging ball electrodes 124 connected to the interconnect pads 121 and the interconnect lines 122 through intermediary of via-plugs 123 .
  • the chip 103 is mounted over the packaging substrate 102 and covered and sealed with resin 105 , and the ball electrodes 131 of the chip 103 are connected to the interconnect pads 121 by soldering.
  • the semiconductor device 101 is mounted on a substrate 104 , and the packaging ball electrodes 124 are connected to interconnects pads 141 formed on the top surface of the substrate 104 .
  • the interconnect pads 121 arranged on the packaging substrate 102 surface as shown in FIG. 2 are substantially identical with the ball electrodes 131 formed on the bottom surface of the chip 103 with respect to their arrangements.
  • the conventional interconnect pad arrangement has so-called peripherals including a signal line terminal (S-terminal), a power source terminal (V-terminal) and a ground terminal (G-terminal) arranged on a single line and disposed in a region corresponding to the outer peripheral of the chip 103 .
  • the respective interconnect pads 121 including the S-terminal, the V-terminal and the G-terminal are arranged in the shape of a lattice by keeping specified intervals.
  • Each of interconnect lines 122 is connected to each of the interconnect pads 121 , and extends toward the outer region of the chip.
  • the interconnect lines 122 connected to the interconnect pads 121 existing in the inner part outwardly extend between the interconnect pads 121 existing in the outer part, and the front end of the interconnect line 122 is electrically connected to the packaging ball electrodes 124 on the bottom surface of the packaging substrate 102 through intermediary of the via-plugs 123 as shown in FIG. 1.
  • interconnect pads 121 having a diameter of 100 ⁇ m are arranged at a pitch of 250 ⁇ m
  • only two interconnect lines 122 can be drawn when the line width of the interconnect lines 122 is 30 ⁇ m and the line interval is 30 ⁇ m.
  • only 12 interconnect lines 122 can be arranged in an area having a width of 1 mm in the above structure of the interconnect pads 121 , and the density of the interconnect lines is 12 lines/mm.
  • the pitch of the interconnect pads is required to be larger than 250 ⁇ m as described above or the chip size is required to be larger, thereby hardly realizing the miniaturization of the chip and the packaging substrate because the larger area is necessary to arrange the interconnect pads
  • JP-A-10(1998)-116859 describes a technique in which interconnects pads for a standard power and a standard current which do not receive nor supply signals are disposed inside a package (chip) and the interconnects pads are connected to external connecting terminals just below the chip.
  • the interconnect pad which does not receive nor supply signals is not required to be connected to the interconnect line, the interconnect line to be arranged among the interconnect pads is unnecessary, thereby reducing the interval between the adjacent interconnect pads.
  • the number of the interconnect pads can be increased and the miniaturization of the chip can be attained.
  • JP-A-9(1997)-69568 describes a technique in which an input-output buffer is disposed in an open region occurring in an inner circuit block-disposing area by not distinguishing an input-output buffer disposing area from the inner circuit block-disposing area in order to realize the configuration which effectively utilizes the open area occurring in the inner circuit blocks without deteriorating the fundamental algorism of a tool for automatically disposing interconnects when the input-output buffer and the inner circuit block are disposed on the chip.
  • the technique is applied on the chip or the package, at least the freedom of the disposition with respect to the disposition of the interconnect pads is elevated to effectively implement the miniaturization.
  • the number of the input-output buffers depends on the open area occurring among the inner circuit blocks, and when the open areas are concentrated, it is uncertain that the interconnect lines are drawn from the input-output buffers Accordingly, the interconnect pads must be designed for every floor plan to increase a period of time. When the drawing-out of the interconnect lines is hardly attained, the effective means for responding thereto does not exist.
  • the interconnect line formed on the packaging substrate is assumed to be a single layer.
  • the interconnect line formed on the packaging substrate is made to be a multi-layered structure having two or more layers, the structure increases the freedom of arranging the interconnect lines to assist to solve the above problem.
  • the multi-layered structure may make the interconnect lines of the upper layer and the lower layer crossed with each other to hardly perform the impedance matching among the interconnect lines, thereby affecting larger adverse effects on the semiconductor device.
  • an object of the present invention is to provide a semiconductor device in which a chip or a package is miniaturized and the number of terminals of external connection terminals is increased.
  • the present invention provides a semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group.
  • the higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.
  • the interconnect pads and the interconnect lines corresponding to the I/O cell is made by the single conductive film, the interconnect lines connected to the single I/O cell are not crossed in the vertical direction to easily perform the impedance matching on each of the interconnect lines.
  • FIG. 1 is a sectional view showing a conventional semiconductor device.
  • FIG. 2 is a schematic view showing interconnect pads and interconnect lines arranged on a packaging substrate of the conventional semiconductor device and an enlarged view showing a part of the arrangement.
  • FIG. 3 is a schematic view showing the density of the conventional interconnect pads and interconnect lines.
  • FIG. 4 is a vertical sectional view showing a semiconductor device in accordance with a first embodiment of the present invention and an enlarged view thereof.
  • FIG. 5 is a schematic view showing interconnect pads and interconnect lines arranged on a packaging substrate of the first embodiment.
  • FIG. 6 is a schematic view showing the density of the interconnect pads and the interconnect lines of FIG. 5.
  • FIG. 7 is a vertical sectional view showing a semiconductor device in accordance with a second embodiment and an enlarged view thereof.
  • FIG. 8 is a schematic view showing interconnect pads and interconnect lines arranged on a packaging substrate of the second embodiment.
  • FIGS. 9A to 9 C are a schematic views showing first modified examples of ball electrodes and the interconnect pads of the second embodiment.
  • FIGS. 10A to 10 D are schematic views showing second modified examples of the ball electrodes and the interconnect pads of the second embodiment.
  • FIGS. 11A to 11 D are schematic views showing third modified examples of the ball electrodes and the interconnect pads of the second embodiment.
  • FIGS. 12A to 12 D are schematic views showing fourth modified examples of the ball electrodes and the interconnect pads of the second embodiment.
  • FIG. 13 is a flow chart sequentially showing steps for fabricating the semiconductor device of the present invention.
  • a semiconductor device 11 includes a packaging substrate 12 and a chip 13 mounted thereon.
  • the packaging substrate 12 is formed by a dielectric plate material and includes, on the top surface thereof, a plenty of interconnect pads 21 and interconnect lines 22 formed by etching a conductive film made of copper
  • the interconnect pads 21 and the interconnect lines 22 are connected to for mounting ball electrodes 24 on the bottom surface of the packaging substrate 12 through intermediary of via-plugs 23 formed through the packaging substrate 12 .
  • a flame-like spacer 25 is fixed to the periphery of the top surface of the packaging substrate 12 by using an adhesive agent, and accommodates the chip in the region surrounded the spacer 25 .
  • a covering plate 27 is fixed on the spacer 25 by using another adhesive agent 26 to seal the chip 13 .
  • the chip 13 is formed by a semiconductor substrate such as silicon, and various elements such as a transistor not shown in the drawing are formed on the bottom main surface of the chip 13 and are covered with a protective dielectric film such as a passivation film.
  • a protective dielectric film such as a passivation film.
  • ball electrodes 31 made of solder, connected to the above elements, acting as internal electrodes.
  • the ball electrodes 31 are soldered to the interconnect pads 21 formed on the packaging substrate 12 to mount the chip 13 on the packaging substrate 12 in a face-down manner, and the elements in the chip 13 are electrically connected to the ball electrodes 24 on the bottom surface of the packaging substrate 12 through intermediary of the ball electrodes 31 and the interconnect pads 21 .
  • the chip 13 is sealed is sealing resin 28 .
  • the semiconductor device 11 is mounted on a mounting substrate 14 .
  • a specified interconnect pattern is formed on a dielectric substrate by using a conductive film to prepare the mounting substrate 14 .
  • the interconnect pattern includes interconnects pads 41 connected to the ball electrodes 24 of the semiconductor device 11 and interconnect lines, not shown in the drawings, for connecting the interconnect pads 41 among one another on the mounting substrate 14 or the interconnect pad 41 with interconnect lines not shown in the drawings for connecting the interconnect pad 41 to an external circuit.
  • the interconnect pads 21 formed on the top surface of the packaging substrate 12 shown in FIG. 5 are disposed corresponding to the ball electrodes 31 on the bottom surface of the chip 13 .
  • the ball electrodes 31 on the bottom surface of the chip 13 are arranged in the shape of a lattice and the interconnect pads 21 are also arranged in the shape of the lattice corresponding to the ball electrodes 31 .
  • the specified number of the ball electrodes 31 and the interconnect pads 21 are grouped as a single I/O cell as shown in FIG. 5 in which only the interconnect pads 21 are shown, and these are arranged as the I/O cell unit. In the embodiment, the plenty of the interconnect pads 21 are divided such that the single I/O cell includes an array of 4 ⁇ 3 interconnect pads 21 .
  • the I/O cell is, for example, a single group including a single unit having one or more input-output buffers formed in the chip 13 and an S-terminal (signal line terminal), a V-terminal (power source terminal) and a G-terminal (ground terminal) connected to the input-output buffers, or the single I/O cell may include only the S-terminal.
  • the number of the terminals and the arrangement are not restricted to the above, and an I/O cell having an arbitrary array can be formed.
  • part of the I/O cells are disposed on the periphery of the chip 13 similarly to the conventional chip, and the remaining cells (CELL-B) are internally disposed from the above I/O cells (CELL-A) at a specified interval.
  • the adjacent I/O cells (CELL-A) disposed on the periphery have a specified space therebetween.
  • peripherals (PL) conventionally used are also disposed on the chip. The peripherals are present in the open space in the 4 ⁇ 3 array.
  • two outer peripheral I/O cells (CELL-A) on the chip 13 are disposed with a specified interval along the periphery, and one inner I/O cell (CELL-B) is disposed in a space opposing to the location between the two outer peripheral. I/O cells (CELL-A).
  • the interconnect lines 22 a are connected to each of the interconnect pads 21 a of the two outer peripheral I/O cells (CELL-A), and are drawn between the interconnect pads 21 a to regions external to the chip 13 .
  • the interconnect lines 22 b are connected to each of the interconnect pads 21 b of the inner peripheral I/O cell (CELL-B), and are drawn similarly to the preceding example in the region of the peripheral I/O cell (CELL-B), and are bundled at a specified interval, at a region out of the inner peripheral I/O cell (CELL-B), to be drawn between the outer peripheral I/O cells (CELL-A) to regions external to the chip 13 .
  • the density of arranging the interconnect lines 21 a at the I/O cells (CELL-A) arranged on the outer periphery of the chip 13 is substantially same as the density of the conventional device shown in FIG. 3.
  • the density of arranging the interconnect lines 21 b connected to the interconnect pad 21 b of the I/O cells (CELL-B) arranged inside of the chip 13 can be increased because of the absence of the interconnect pads.
  • the dimension of arranging the 12 bundled interconnect lines 22 i is 750 ⁇ m.
  • the number of the interconnect lines 22 in the region having a size of 2 mm along the outer periphery of the chip is 27 calculated by adding the number of the interconnect lines 22 a of the outer peripheral I/O cells (CELL-A) to the number of the interconnect lines 22 b of the inner I/O cells (CELL-B).
  • the density of the interconnect lines 22 is 13.5 lines/mm in the embodiment, and is increased compared with conventional density of 12 lines/mm shown in FIG. 3.
  • the higher integration of the semiconductor device having the higher performances can be realized by dividing the ball electrodes 31 disposed on the chip 13 and the interconnect pads arranged on the packaging substrate 12 into the plurality of the I/O cells and disposing part of the I/O cells at the outer periphery of the chip 13 and the remaining I/O cells at the corresponding inner sections of the chip 13 because the drawing-out of the interconnect lines 22 to the peripheral outer regions of the chip on the top surface of the packaging substrate 12 is possible.
  • the I/O cells (CELL-B) may be formed endlessly or annually to enable the arrangement of the extremely larger number of the ball electrodes 31 and the interconnect pads 21 .
  • An interval may exist between the I/O cells (CELL-B) disposed on the inner section.
  • the ball electrodes 31 and the interconnect pads 21 of the outer peripheral I/O cells (CELL-A) may be freely disposed so long as the spaces through which the interconnect lines 22 of the I/O cells (CELL-B) disposed on the inner section pass may be secured, thereby promoting the higher integration of the semiconductor device having the higher performances.
  • the I/O cells can be freely disposed in the regions of the chip so long as the above requisites are satisfied to increase the freedom of the chip design and the package design.
  • the interconnect pads 21 and the interconnect lines 22 in the embodiment are made by the conductive film having the single layer, the interconnect lines connected to the single I/O cell are not crossed in the vertical direction to easily perform the impedance matching on each of the interconnect lines. Especially, when the interconnect pads and the interconnect lines corresponding to the plurality of the input-output buffers are intermingled in the single I/O cell, the proper impedance matching is possible by preventing the mutual intervention between the interconnect lines of each of the input-output buffers.
  • a second embodiment of the present invention is shown in FIG. 7 in which the same numerals as those of the first embodiment designate the same elements.
  • a semiconductor device 11 includes a packaging substrate 12 A and a chip 13 mounted thereon.
  • the packaging substrate 12 A includes a central core layer 211 sandwiched between a pair of buildup layers 212 , 213 , and a plenty of interconnect pads 21 made of a conductive film are formed on the top buildup layer 212 .
  • the interconnect pads 21 are connected to the interconnect lines in each of the multi-layers of the top buildup layer 212 , further connected to the bottom buildup layer 213 through intermediary of via plugs, and still further connected to ball electrodes 24 formed on the bottom surface of the bottom buildup layer 213 or the bottom surface of the packaging substrate 12 A.
  • Each of the buildup layers is multi-layered, and the top buildup layer 212 includes five interconnect layers in which a first layer includes the interconnect pads 21 and a GND layer, a third layer includes a GND layer 3 G and a VDD layer 3 V, and a fifth layer includes a GND layer 5 G and a VDD layer 5 V connected to the via plugs of the above core layer.
  • a second layer and a fourth layer are formed as independent interconnect lines 22 a , 22 b for signals.
  • the interconnect lines formed in the single layer in the first embodiment are divided into the first to fifth interconnect layers 201 to 205 .
  • the interconnect lines connected to the interconnect pad 21 acting as the S-terminal (signal terminal) can be drawn as the interconnect lines 22 of the second and fourth layers separately from the others.
  • the grouped I/O cell in the arrangement of the interconnect pads 21 as well as the ball electrodes 31 of the chip 13 can be divided into a first I/O cell (CELL- 1 ) and a second I/O cell (CELL- 2 ). Part of the first I/O cell (CELL- 1 ) or I/O cells (CELL- 1 A) are disposed on the outer peripheral region of the chip 13 , and the remaining I/O cells (CELL- 1 B) are disposed on the inner sections of the chip 13 .
  • Intervals are secured between the first I/O cells (CELL- 1 A) remaining on the outer periphery for passing the interconnect lines 22 drawn from the inner I/O cells (CELL- 1 B).
  • the first I/O cells (CELL- 1 ) disposed on the outer periphery are alternately disposed on outer sections (CELL- 1 A) and inner parts (CELL- 1 B) in the outer periphery.
  • the second I/O cells (CELL- 2 ) are disposed on the sections inside of the other I/O cells (CELL- 1 ), and part of the second I/O cell (CELL- 2 ) or I/O cells (CELL- 2 B) are disposed inside of the remaining I/O cells (CELL- 2 A) and intervals are secured between the outer second I/O cells (CELL- 2 A) for passing the interconnect lines drawn from the inner second I/O cells (CELL- 2 B).
  • the second I/O cells (CELL- 2 ) are alternately disposed on outer sections (CELL- 2 A) and inner parts (CELL- 2 B).
  • the interconnect line 22 - 1 connected to the interconnect pad 21 - 1 of the first I/O cell (CELL- 1 ) is connected in its outer region to the second interconnect layer 202 of the top buildup layer 212 and drawn to the outer region by the second interconnect layer 202 .
  • the interconnect line 22 - 2 connected to the interconnect pad 21 - 2 of the second I/O cell (CELL- 2 ) is connected in the area between its outer region and the first I/O cell (CELL- 1 ) to the fourth interconnect layer 204 of the top buildup layer 212 and drawn to the outer region by the fourth interconnect layer 204 .
  • interconnect line 22 - 2 connected to the second I/O cell (CELL- 2 ) is never drawn to the outer region through the first I/O cells (CELL- 1 ).
  • the interconnect lines 202 , 204 of the second and the fourth layers are connected to the via plugs 23 of the core layer 211 at specified positions and further connected to the ball electrodes 24 on the bottom surface of the packaging substrate 12 A through intermediary of the bottom buildup layer 213 .
  • the configuration of the interconnect pads 21 and the interconnect lines 22 on the top surface of the packaging substrate 12 A obtained in this manner is similar to that shown in FIG. 6 for each of the first I/O cell (CELL- 1 ) and the second I/O cell (CELL- 2 ), and enables to elevate the density of the interconnect pads 21 and the interconnect lines 22 of the first I/O cell (CELL- 1 ) and the second I/O cell (CELL- 2 ). Since the first I/O cell (CELL- 1 ) and the second I/O cell (CELL- 2 ) are double-disposed in the second embodiment, the density almost twice that of the first embodiment can be obtained. Thereby, even when the chip is miniaturized or the numbers of the ball electrodes and the interconnect pads are increased, the higher integration of the semiconductor device having the higher performances can be realized by drawing the interconnect lines of each of the I/O cells.
  • the interconnect lines 22 - 1 of the first I/O cell (CELL- 1 ) is drawn by the second interconnect layer 202 and the interconnect lines 22 - 2 of the second I/O cell (CELL- 2 ) is drawn by the fourth interconnect layer 204 in the second embodiment, the interconnect lines connected to the respective I/O cells are drawn to the single interconnect layer and are not crossed in the vertical direction to easily perform the impedance matching on each of the interconnect lines.
  • the proper impedance matching is possible by preventing the mutual intervention between the interconnect lines of each of the input-output buffers similarly to the first embodiment.
  • FIGS. 9A to 9 C Modified first examples of arranging the first I/O cell (CELL- 1 ) and the second I/O cell (CELL- 2 ) in the second embodiment are shown in FIGS. 9A to 9 C.
  • FIG. 9A only for the first I/O cell (CELL- 1 ), the outer I/O cell (CELL- 1 A) and the inner I/O cell (CELL- 1 B) are disposed.
  • FIG. 9B only for the second I/O cell (CELL- 2 ), the outer I/O cell (CELL- 2 A) and the inner I/O cell (CELL- 2 B) are disposed.
  • each of the first I/O cell (CELL- 1 ) and the second I/O cell (CELL- 2 ) may be disposed in a single row.
  • FIGS. 10A to 10 D Modified second examples of arranging the I/O cells in the second embodiment are shown in FIGS. 10A to 10 D in which either of the first I/O cell (CELL- 1 ) and the second I/O cell (CELL- 2 ) is not the I/O cell but the conventional peripherals.
  • the outer peripheral section is formed by peripherals PL and the inner section is formed by the second I/O cell (CELL- 2 ).
  • FIG. 10B the inner second I/O cell (CELL- 2 ) of FIG. 10A is formed by the outer I/O cell (CELL- 2 A) and the inner I/O cell (CELL- 2 B).
  • FIG. 10A the outer peripheral section is formed by peripherals PL and the inner section is formed by the second I/O cell (CELL- 2 ).
  • the inner second I/O cell (CELL- 2 ) of FIG. 10A is formed by the outer I/O cell (CELL- 2 A) and the inner I/O cell (CELL- 2 B
  • the outer peripheral section is formed by the first I/O cell (CELL- 1 ) and the inner section is formed by the peripherals PL.
  • the outer first I/O cell (CELL- 1 ) of FIG. 10C is formed by the outer I/O cell (CELL- 1 A) and the inner I/O cell (CELL- 1 B).
  • part of the first I/O cell (CELL- 1 ) or the second I/O cell (CELL- 2 ) is formed by the peripherals PL to intermingle the I/O cells and the peripherals PL.
  • part of the first I/O cells (CELL- 1 A, CELL- 1 B) or the second I/O cells (CELL- 2 A, CELL- 2 B) formed by the inner I/O cells and the outer I/O cells may be formed by the peripherals PL.
  • the higher integration of the semiconductor device having the higher performances can be realized compared with the conventional configuration as shown in FIG. 2 because the ball electrodes and the number of the interconnect pads can be increased.
  • the method of disposing the ball electrodes 31 and the interconnect pads 21 as the I/O cells are substantially same for the semiconductor devices of the first and the second embodiments.
  • the method for disposing the semiconductor device in the first embodiment will be described referring to a flow chart shown in FIG. 13.
  • a template having I/O cells and peripherals to be disposed on a chip along the outer periphery of the chip is fabricated (S 101 ). Then, the judgment is conducted whether or not the numbers of the balls electrodes and the interconnect pads of the I/O cell and the peripherals, and the number of required terminals reach to specified values (S 102 ). When the numbers reach to the required values, the judgment is conducted whether or not the request for disposing I/O cells at the center of the chip (S 103 ). In absence of the request, the disposal is finished (S 104 ). In present of the request for disposing the I/O cells at the center of the chip, the cell is moved in accordance with a floor plan (S 105 ).
  • step (S 104 ) is again executed after the floor plan and the I/O cells are modified.
  • step (S 108 ) is initiated.
  • the number of the terminals does not reach to the required number in the step (S 102 )
  • the number of the I/O cells disposed on the inner sections of the chip is calculated (S 107 ) for increasing the number to the required one.
  • another new template having a reduced interval between the I/O cells is fabricated (S 108 ).
  • the I/O cell is moved in accordance with a floor plan (S 109 ).
  • the disposal is finished (S 104 ) because the I/O cells can be disposed on the outer periphery and on the inner section of the chip.
  • the step (S 109 ) is again executed after a further template having a reduced interval between the I/O cells is fabricated (S 110 ). Or, depending on necessity, the step (S 109 ) is again executed after the modification of the floor plan and the I/O cells.
  • the disposal of all the I/O cells is not finished after the plurality of the re-executions, the disposal is recognized to be failed, and the procedures are started from the first step (S 101 ) after the chip is enlarged or the number of the interconnects is increased.
  • a process of diving the I/O cell into the first I/O cell and the second I/O cell is inserted between the steps (S 107 ) and (S 108 ), and the processes are conducted on and after the step (S 108 ) for each of the I/O cells.
  • the method of disposing the interconnect pads of the I/O cell and drawing the interconnect lines connected to the interconnect pads is determined in advance.
  • the propriety of drawing the interconnect lines at the time of preparing the floor plan can be easily judged to advantageously reduce a length of processing time (TAT).
  • the method can be easily customized for every kind of the semiconductor devices by suitably using the I/O cells having different usages after the usages of each of the I/O cells are stored as information.
  • the I/O cells can be arranged in an array having an arbitrary number.
  • the I/O cell may be formed by disposing the plurality of the conventional peripherals.
  • the present invention may be also applied to the ball electrodes 24 of the semiconductor device 11 and the interconnect pads 41 and the interconnect lines on the mounting substrate 14 .
  • the ball electrodes 24 on the bottom surface of the packaging substrate 12 , 12 A and the interconnect pads 41 on the top surface of the mounting substrate 14 are disposed as the I/O cells to increase the density of the ball electrodes 24 and the interconnect pads 41 to achieve the miniaturization of the chip and further to increase the number of the terminals, the higher integration of the semiconductor device having the higher performances can be realized.
  • the mounting substrate 14 is multi-layered.

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070187808A1 (en) * 2006-02-16 2007-08-16 Easic Corporation Customizable power and ground pins
US20080136047A1 (en) * 2004-09-29 2008-06-12 Rohm Co., Ltd. Semiconductor device
US20100176504A1 (en) * 2000-06-08 2010-07-15 Nec Electronics Corporation Semiconductor device
US20100252830A1 (en) * 2007-12-28 2010-10-07 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method thereof
US20100327452A1 (en) * 2008-03-05 2010-12-30 Hirotsugu Kobayashi Mounting structure and method of manufacturing the same
US9054120B2 (en) 2011-04-28 2015-06-09 Renesas Electronics Corporation Semiconductor device, semiconductor device design method, semiconductor device design apparatus, and program
US20180130730A1 (en) * 2016-09-19 2018-05-10 Nanya Technology Corporation Method for forming semiconductor package
US20190206788A1 (en) * 2017-12-28 2019-07-04 Texas Instruments Incorporated Lattice bump interconnect

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040003941A1 (en) * 2000-06-19 2004-01-08 Duxbury Guy A. Technique for electrically interconnecting electrical signals between an electronic component and a multilayer signal routing device
US7281326B1 (en) 2000-06-19 2007-10-16 Nortel Network Limited Technique for routing conductive traces between a plurality of electronic components of a multilayer signal routing device
US7259336B2 (en) 2000-06-19 2007-08-21 Nortel Networks Limited Technique for improving power and ground flooding
US7256354B2 (en) 2000-06-19 2007-08-14 Wyrzykowska Aneta O Technique for reducing the number of layers in a multilayer circuit board
JP4025044B2 (ja) * 2001-09-27 2007-12-19 株式会社東芝 半導体集積回路装置
JP3780996B2 (ja) * 2002-10-11 2006-05-31 セイコーエプソン株式会社 回路基板、バンプ付き半導体素子の実装構造、バンプ付き半導体素子の実装方法、電気光学装置、並びに電子機器
JP6118652B2 (ja) * 2013-02-22 2017-04-19 ルネサスエレクトロニクス株式会社 半導体チップ及び半導体装置
JP2015088539A (ja) * 2013-10-29 2015-05-07 株式会社デンソー 半導体パッケージ、および、これを実装する配線基板
KR102245132B1 (ko) * 2014-05-14 2021-04-28 삼성전자 주식회사 트레이스를 가지는 인쇄회로기판 및 볼 그리드 어레이 패키지
WO2018045167A1 (en) * 2016-09-02 2018-03-08 Octavo Systems Llc Substrate for use in system in a package (sip) devices

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5777383A (en) * 1996-05-09 1998-07-07 Lsi Logic Corporation Semiconductor chip package with interconnect layers and routing and testing methods
US6111756A (en) * 1998-09-11 2000-08-29 Fujitsu Limited Universal multichip interconnect systems
US6225694B1 (en) * 1997-09-02 2001-05-01 Oki Electric Industry Co, Ltd. Semiconductor device
US6271478B1 (en) * 1997-11-19 2001-08-07 Shinko Electric Industries Co., Ltd. Multi-layer circuit board
US6285560B1 (en) * 1999-09-20 2001-09-04 Texas Instruments Incorporated Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified
US6310398B1 (en) * 1998-12-03 2001-10-30 Walter M. Katz Routable high-density interfaces for integrated circuit devices
US20020014691A1 (en) * 1997-04-26 2002-02-07 Chong Kwang Yoon Multiple line grid array package
US20020063318A1 (en) * 2000-11-29 2002-05-30 Motorola, Inc. Ball grid array (BGA) mounting device
US6459039B1 (en) * 2000-06-19 2002-10-01 International Business Machines Corporation Method and apparatus to manufacture an electronic package with direct wiring pattern
US6492715B1 (en) * 2000-09-13 2002-12-10 International Business Machines Corporation Integrated semiconductor package

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02244755A (ja) 1989-03-17 1990-09-28 Hitachi Ltd Ｌｓｉ
JP2872825B2 (ja) * 1991-05-13 1999-03-24 三菱電機株式会社 半導体装置用パッケージ
JP2959444B2 (ja) 1995-08-30 1999-10-06 日本電気株式会社 フリップチップ型半導体装置の自動配置配線方法
US5686764A (en) * 1996-03-20 1997-11-11 Lsi Logic Corporation Flip chip package with reduced number of package layers
US6034427A (en) * 1998-01-28 2000-03-07 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
JP2000100851A (ja) * 1998-09-25 2000-04-07 Sony Corp 半導体部品及びその製造方法、半導体部品の実装構造及びその実装方法
JP3407025B2 (ja) * 2000-06-08 2003-05-19 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5777383A (en) * 1996-05-09 1998-07-07 Lsi Logic Corporation Semiconductor chip package with interconnect layers and routing and testing methods
US20020014691A1 (en) * 1997-04-26 2002-02-07 Chong Kwang Yoon Multiple line grid array package
US6225694B1 (en) * 1997-09-02 2001-05-01 Oki Electric Industry Co, Ltd. Semiconductor device
US6271478B1 (en) * 1997-11-19 2001-08-07 Shinko Electric Industries Co., Ltd. Multi-layer circuit board
US6111756A (en) * 1998-09-11 2000-08-29 Fujitsu Limited Universal multichip interconnect systems
US6310398B1 (en) * 1998-12-03 2001-10-30 Walter M. Katz Routable high-density interfaces for integrated circuit devices
US6285560B1 (en) * 1999-09-20 2001-09-04 Texas Instruments Incorporated Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified
US6459039B1 (en) * 2000-06-19 2002-10-01 International Business Machines Corporation Method and apparatus to manufacture an electronic package with direct wiring pattern
US6492715B1 (en) * 2000-09-13 2002-12-10 International Business Machines Corporation Integrated semiconductor package
US20020063318A1 (en) * 2000-11-29 2002-05-30 Motorola, Inc. Ball grid array (BGA) mounting device

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100176504A1 (en) * 2000-06-08 2010-07-15 Nec Electronics Corporation Semiconductor device
US8680691B2 (en) 2000-06-08 2014-03-25 Renesas Electronics Corporation Semiconductor device having semiconductor member and mounting member
US9006885B2 (en) 2004-09-29 2015-04-14 Rohm Co., Ltd. Semiconductor device having electrode pads arranged between groups of external electrodes
US11901251B2 (en) 2004-09-29 2024-02-13 Rohm Co., Ltd Semiconductor device having electrode pads arranged between groups of external electrodes
US11410900B2 (en) 2004-09-29 2022-08-09 Rohm Co., Ltd. Semiconductor device having electrode pads arranged between groups of external electrodes
US10665518B2 (en) 2004-09-29 2020-05-26 Rohm Co., Ltd. Semiconductor device having electrode pads arranged between groups of external electrodes
US20110042833A1 (en) * 2004-09-29 2011-02-24 Rohm Co., Ltd. Semiconductor device
US8134238B2 (en) 2004-09-29 2012-03-13 Rohm Co., Ltd. Semiconductor device having a wafer level chip size package structure
US8405208B2 (en) 2004-09-29 2013-03-26 Rohm Co., Ltd. Semiconductor device having semiconductor substrate electrode pads, and external electrodes
US10134653B2 (en) 2004-09-29 2018-11-20 Rohm Co., Ltd. Semiconductor device having electrode pads arranged between groups of external electrodes
US8653656B2 (en) 2004-09-29 2014-02-18 Rohm Co., Ltd. Semiconductor device having multiple external electrodes
US9391033B2 (en) 2004-09-29 2016-07-12 Rohm Co., Ltd. Semiconductor device
US7851929B2 (en) * 2004-09-29 2010-12-14 Rohm Co., Ltd. Semiconductor device
US9691678B2 (en) 2004-09-29 2017-06-27 Rohm Co., Ltd. Semiconductor device having electrode pads arranged between groups of external electrodes
US20080136047A1 (en) * 2004-09-29 2008-06-12 Rohm Co., Ltd. Semiconductor device
US20070187808A1 (en) * 2006-02-16 2007-08-16 Easic Corporation Customizable power and ground pins
US20100252830A1 (en) * 2007-12-28 2010-10-07 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method thereof
US8519551B2 (en) 2007-12-28 2013-08-27 Fujitsu Semiconductor Limited Semiconductor device with I/O cell and external connection terminal and method of manufacturing the same
US20100327452A1 (en) * 2008-03-05 2010-12-30 Hirotsugu Kobayashi Mounting structure and method of manufacturing the same
US9589893B2 (en) 2011-04-28 2017-03-07 Renesas Electronics Corporation Semiconductor device, semiconductor device design method, semiconductor device design apparatus, and program
US9054120B2 (en) 2011-04-28 2015-06-09 Renesas Electronics Corporation Semiconductor device, semiconductor device design method, semiconductor device design apparatus, and program
US20180130730A1 (en) * 2016-09-19 2018-05-10 Nanya Technology Corporation Method for forming semiconductor package
US10037937B2 (en) * 2016-09-19 2018-07-31 Nanya Technology Corporation Method for forming semiconductor package
US20190206788A1 (en) * 2017-12-28 2019-07-04 Texas Instruments Incorporated Lattice bump interconnect
US11145598B2 (en) * 2017-12-28 2021-10-12 Texas Instruments Incorporated Lattice bump interconnect

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US8680691B2 (en) 2014-03-25

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