US12167694B2 - Method for transferring a piezoelectric layer onto a support substrate - Google Patents

Method for transferring a piezoelectric layer onto a support substrate Download PDF

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US12167694B2
US12167694B2 US17/041,355 US201917041355A US12167694B2 US 12167694 B2 US12167694 B2 US 12167694B2 US 201917041355 A US201917041355 A US 201917041355A US 12167694 B2 US12167694 B2 US 12167694B2
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substrate
layer
piezoelectric
nitride
forming
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US20210020826A1 (en
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Djamel Belhachemi
Thierry Barge
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Soitec SA
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/05—Manufacture of multilayered piezoelectric or electrostrictive devices, or parts thereof, e.g. by stacking piezoelectric bodies and electrodes
    • H10N30/057—Manufacture of multilayered piezoelectric or electrostrictive devices, or parts thereof, e.g. by stacking piezoelectric bodies and electrodes by stacking bulk piezoelectric or electrostrictive bodies and electrodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/025—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks comprising an acoustic mirror
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Definitions

  • the present disclosure relates to a process for producing a donor substrate for the transfer of a piezoelectric layer, and a process for transferring such a piezoelectric layer.
  • the present disclosure is applicable, in particular, to the production of radiofrequency devices, such as resonators or filters.
  • a radiofrequency (RF) device such as a resonator or filter
  • a substrate comprising, successively, from its base to its surface, a carrier substrate, generally made of a semiconductor material such as silicon, an electrically insulating layer and a piezoelectric layer.
  • RF radiofrequency
  • Bulk acoustic wave (BAW) devices typically comprise a thin piezoelectric layer (i.e., with a thickness generally substantially less than 1 ⁇ m) and two electrodes arranged on each main face of the thin layer.
  • An electrical signal typically a voltage variation, applied to an electrode is converted into an elastic wave, which propagates through the piezoelectric layer. The propagation of this elastic wave is promoted if the frequency of the wave corresponds to the frequency band of the filter. This wave is converted into an electrical signal again when it reaches the electrode located on the opposite face.
  • the piezoelectric layer is typically obtained by transferring a thick substrate of a piezoelectric material (for example, obtained by slicing an ingot) to a carrier substrate.
  • the carrier substrate is, for example, a silicon substrate.
  • the transfer of the piezoelectric layer entails bonding the thick piezoelectric substrate to the carrier substrate, followed by thinning the thick piezoelectric substrate so as to leave only a thin piezoelectric layer on the carrier substrate, of the desired thickness for producing the RF device.
  • a layer of oxide for example, a silicon oxide SiO 2
  • a silicon oxide SiO 2 is generally deposited on each of the two substrates, and the substrates are bonded via the oxide layers.
  • the consolidating anneal is typically carried out at a temperature of between 100° C. and 300° C.
  • a donor virtual substrate that is to say a heterostructure in which the thick piezoelectric substrate is bonded to a handle substrate.
  • the thick piezoelectric substrate is held between the handle substrate and the carrier substrate.
  • the donor virtual substrate could thus be produced by joining the thick piezoelectric substrate and a silicon substrate, each covered with an oxide layer.
  • depositing an oxide layer on the thick piezoelectric substrate causes the piezoelectric substrate to curve (bow) substantially, which is not very compatible with the later steps of the process, which are designed for flat substrates.
  • the heterostructure cannot undergo the consolidating anneal because of the differences in thermal expansion coefficients between the thick piezoelectric substrate and the handle substrate.
  • the bonding energy of the oxide layers of the two substrates remains very low, such that the mechanical strength of the donor virtual substrate is insufficient. Consequently, a break at the bonding interface may occur during the step of thinning the thick piezoelectric substrate.
  • One object of the present disclosure is to overcome the aforementioned drawbacks and, in particular, to design a donor substrate for the transfer of a thin piezoelectric layer from a thick substrate to a carrier substrate, which is less expensive to produce, which has better mechanical strength and/or which has a lower curvature than existing substrates.
  • the present disclosure provides a process for producing a donor substrate for the transfer of a piezoelectric layer to a carrier substrate, the process comprising the following steps:
  • the proposed production process has the following various features, which may be implemented alone or in technically feasible combinations thereof:
  • Another subject of the present disclosure relates to a process for transferring a piezoelectric layer to a carrier substrate, comprising:
  • the proposed transfer process has the following various features, which may be implemented alone or in technically feasible combinations thereof:
  • Another subject of the present disclosure relates to a process for producing a bulk acoustic wave device, comprising the deposition of electrodes on two opposite faces of a piezoelectric layer.
  • This process comprises producing the piezoelectric layer by means of a transfer process described above.
  • the present disclosure also relates to a donor substrate for the transfer of a piezoelectric layer, consisting of a heterostructure comprising a piezoelectric substrate bonded to a handle substrate.
  • the substrate comprises, at the interface between the piezoelectric substrate and the handle substrate, a polymerized adhesive layer.
  • FIG. 1 schematically illustrates the step of depositing the photopolymerizable adhesive layer on the handle substrate
  • FIG. 2 schematically illustrates the step of providing the thick piezoelectric substrate
  • FIG. 3 schematically illustrates a heterostructure obtained by bonding the piezoelectric substrate to the handle substrate by means of the adhesive layer;
  • FIG. 4 schematically illustrates the step of polymerizing the adhesive layer in the heterostructure so as to form the donor virtual substrate, simply called the donor substrate, according to the present disclosure
  • FIG. 5 schematically illustrates the step of implanting atomic species into the donor substrate of FIG. 4 so as to form a weakened zone therein;
  • FIG. 6 schematically illustrates a carrier substrate on which a dielectric layer has been deposited
  • FIG. 7 schematically illustrates the step of bonding the weakened donor substrate to the carrier substrate
  • FIG. 8 illustrates the substrate obtained after splitting and separating the donor substrate along the weakened zone
  • FIG. 9 is a schematic illustration of a bulk acoustic wave filter according to one embodiment of the present disclosure.
  • a first subject of the present disclosure relates to a process for producing a donor substrate for the transfer of a piezoelectric layer to a carrier substrate.
  • the donor substrate is produced by bonding a piezoelectric substrate to a handle substrate.
  • the handle substrate comprises a material whose thermal expansion coefficient is close to that of the material of the carrier substrate to which the piezoelectric layer is intended to be transferred. What is meant by “close” is that a difference in thermal expansion coefficient between the material of the handle substrate and the material of the carrier substrate is less than or equal to 5%, and preferably equal to or close to 0%.
  • Suitable materials are, for example, silicon, sapphire, polycrystalline aluminum nitride (AlN), or gallium arsenide (GaAs). In the present disclosure, it is the thermal expansion coefficient in a plane parallel to the main surface of the substrates that is of interest.
  • a photopolymerizable adhesive layer 1 is deposited on an exposed face of the handle substrate 2 or of the piezoelectric substrate 3 .
  • the deposition is performed on the handle substrate 2 .
  • the photopolymerizable adhesive layer 1 is advantageously deposited by spin coating. This technique involves rotating the substrate on which the photopolymerizable layer is to be deposited at a substantially constant and relatively high speed in order to spread the photopolymerizable layer uniformly over the entire surface of the substrate by centrifugal force. To this end, the substrate is typically placed and held by vacuum chuck on a turntable.
  • a person skilled in the art is capable of determining the operating conditions, such as the volume of adhesive deposited on the surface of the substrate, the speed of rotation of the substrate, and the minimum deposition time according to the desired thickness for the adhesive layer.
  • the thickness of the photopolymerizable adhesive layer is typically between 2 and 8 ⁇ m.
  • the photopolymerizable adhesive layer sold under the reference “NOA 61” by NORLAND PRODUCTS may be used in embodiments of the present disclosure.
  • the piezoelectric substrate 3 is then bonded to the handle substrate via the adhesive layer 1 , in order to form a heterostructure 4 , one embodiment of which is shown in FIG. 3 .
  • the heterostructure 4 is thus formed from the superposition of the handle substrate 2 , of the adhesive layer 1 , and of the piezoelectric substrate 3 , the adhesive layer 1 being located at the interface between the handle substrate and the piezoelectric substrate.
  • the bonding is preferably carried out at ambient temperature, i.e., at about 20° C. It is, however, possible to carry out the bonding at a temperature of between 20° C. and 50° C., and more preferably between 20° C. and 30° C.
  • the bonding step is advantageously carried out under vacuum, which makes it possible to desorb water from the surfaces forming the bonding interface, i.e., the surface of the adhesive layer and the surface of the handle substrate or of the piezoelectric substrate.
  • the heterostructure 4 is then subjected to irradiation with a light flux 5 , in order to polymerize the adhesive layer 1 .
  • the irradiation of the heterostructure is shown in FIG. 4 .
  • the light source is preferably a laser.
  • the light radiation, or light flux is preferably ultra-violet (UV) radiation.
  • UV radiation having a wavelength of between 320 nm (nanometers) and 365 nm will preferably be chosen.
  • the irradiation is carried out by exposing the free face 30 of the piezoelectric substrate 3 to the incident light radiation.
  • the light flux 5 penetrates into the heterostructure 4 from the free face 30 of the piezoelectric substrate 3 , passes through the piezoelectric substrate 3 , until reaching the adhesive layer 1 , thus causing the polymerization of the adhesive layer.
  • the polymerization of the adhesive layer 1 makes it possible to form a polymer layer 10 , which ensures the mechanical cohesion of the heterostructure, keeping the handle substrate 2 and the piezoelectric substrate 3 , which form the donor substrate, bonded together.
  • the irradiation of the heterostructure gives rise to a thermal process via which the piezoelectric layer 3 , through which the radiation passes, is able to partially absorb the energy of the radiation and to heat up. Too much heating could destabilize the structure of the piezoelectric layer, which could lead to a degradation of the physical and chemical properties of the piezoelectric layer. In addition, too much heating could cause the piezoelectric layer and the handle substrate to deform due to their difference in thermal expansion coefficient, resulting in an overall deformation, called “bow,” of the heterostructure and therefore of the resulting donor substrate.
  • bow overall deformation
  • the irradiation is advantageously pulsed, i.e., the heterostructure is exposed to a plurality of pulses of light rays. Each pulse lasts a set irradiation time, which may be equal or different from one pulse to the next. The pulses are spaced apart in time by a determined rest time during which the heterostructure is not exposed to light rays.
  • a donor substrate 40 comprising the heterostructure 4 with a polymerized adhesive layer 10 is obtained.
  • the polymerized adhesive layer 10 makes it possible to bond the piezoelectric substrate and the handle substrate without exposing them to a thermal budget that would be liable to deform them, which makes it possible to endow the donor substrate 40 with sufficient mechanical strength for the subsequent transfer of a piezoelectric layer.
  • the thickness of the polymerized adhesive layer 10 is preferably between 2 ⁇ m (microns) and 8 ⁇ m. This thickness depends, in particular, on the constituent material of the photopolymerizable adhesive layer deposited before bonding, on the thickness of the photopolymerizable adhesive layer, and on the experimental conditions of irradiation.
  • the donor substrate 40 is subjected to a surface treatment that aims to make the exposed surface of the piezoelectric layer planar and to decrease its roughness.
  • a second subject of the present disclosure relates to a process for transferring a piezoelectric layer to a carrier substrate.
  • a donor substrate comprising the piezoelectric layer to be transferred is initially provided.
  • the donor substrate is preferably obtained by means of the production process described above according to the first subject of the present disclosure.
  • a carrier substrate 6 capable of receiving the piezoelectric layer to be transferred is also provided.
  • the carrier substrate is preferably made of silicon.
  • a weakened zone 7 is formed in the piezoelectric substrate 3 , so as to delimit the piezoelectric layer 31 to be transferred.
  • the depth of the weakened zone 7 relative to the exposed surface of the piezoelectric substrate determines the thickness of the piezoelectric layer to be transferred.
  • the weakened zone is formed by implanting atomic species into the piezoelectric substrate, the implantation being shown in FIG. 5 by the arrows 9 .
  • the atomic species are implanted at a determined depth of the piezoelectric substrate, which determines the thickness of the piezoelectric layer to be transferred.
  • the implanted atomic species are preferably hydrogen ions and/or helium ions.
  • a dielectric layer 8 is then formed on a main face of the carrier substrate 6 and/or of the piezoelectric substrate.
  • FIG. 6 shows the carrier substrate 6 on which a dielectric layer 8 has been deposited.
  • the dielectric layer is a glass layer deposited by spin coating on the piezoelectric substrate, referred to as “spin-on glass” (SOG).
  • SOG spin-on glass
  • the free face 30 or 60 to be bonded on which the dielectric layer has not been deposited, of the donor substrate 40 or of the carrier substrate 6 undergoes a suitable treatment to subsequently allow hydrophilic molecular bonding of this surface with the other respective surface.
  • a suitable treatment involves forming, on the carrier substrate, an oxide layer, or a nitride layer, or a layer comprising a combination of nitride and oxide, or a superposition of an oxide layer and of a nitride layer.
  • a layer of silicon oxide SiO 2 , or a layer of silicon nitride Si 3 N 4 a layer comprising a combination of silicon nitride and oxide SiOxNy, or a superposition of a layer of silicon oxide SiO 2 and of a layer of silicon nitride Si 3 N 4 could be formed.
  • a layer of silicon oxide will preferably be formed when the carrier substrate is made of silicon.
  • the donor substrate 40 is bonded to the carrier substrate 6 , as illustrated in FIG. 7 .
  • the bonding is carried out such that the dielectric layer 8 is located at the bonding interface.
  • the multilayer structure 20 formed then successively comprises the carrier substrate 6 , the dielectric layer 8 , the piezoelectric layer 31 to be transferred from the piezoelectric substrate 3 , the polymer layer 10 , and the handle substrate 2 .
  • the multilayer structure 20 is subjected to a thermal anneal and the donor substrate 40 is detached from the carrier substrate 6 along the weakened zone 7 , thus allowing the piezoelectric layer 31 to be transferred to the carrier substrate 6 .
  • FIG. 8 illustrates the final structure obtained after splitting and separating the donor virtual substrate along the weakened zone, comprising the transferred piezoelectric layer 31 arranged on the carrier substrate 6 , with the dielectric layer 8 located at the interface of the transferred piezoelectric layer 31 and the carrier substrate 6 .
  • the step of splitting and separating the donor substrate is carried out at a temperature such that the polymerized adhesive layer is not degraded.
  • a temperature of less than or equal to 300° C. makes it possible to prevent such degradation of the polymerized adhesive layer.
  • a temperature of the order of 160° C. is sufficient to split the piezoelectric substrate along the weakened zone.
  • the piezoelectric substrate is held between two substrates (namely the handle substrate and the carrier substrate) whose thermal expansion coefficients are close, it does not experience a differential deformation during the implementation of the anneal.
  • a third subject of the present disclosure relates to a non-limiting application of the transfer process according to the second subject of the present disclosure.
  • a process is proposed for producing a bulk acoustic wave device comprising the deposition of electrodes on two opposite faces of a piezoelectric layer produced according to the transfer process according to the second subject of the present disclosure.
  • FIG. 9 is a schematic of a bulk acoustic wave resonator.
  • the resonator 70 comprises a thin piezoelectric layer 31 (i.e., with a thickness of generally less than 1 ⁇ m, preferably less than 0.2 ⁇ m) and two electrodes 71 , 72 arranged on either side of the piezoelectric layer 31 .
  • the piezoelectric layer 31 rests on a carrier substrate 6 .
  • a Bragg mirror 73 is interposed between the electrode 71 and the substrate 6 .
  • this isolation could be achieved by providing a cavity between the substrate and the piezoelectric layer.
  • the carrier substrate may not be optimal for the final application. It may then be advantageous to transfer the layer 31 to a final substrate (not shown), the properties of which are chosen according to the intended application, by bonding it to the final substrate and by removing the carrier substrate by means of any suitable technique.
  • a first electrode is deposited on the free surface of the layer 31 to be transferred from the donor substrate, this first electrode 71 ( FIG. 9 ) being buried in the final stack.
  • a second electrode 72 is deposited on the free surface of the layer 31 , opposite the first electrode 71 .
  • Another option is to transfer the layer 31 to a final substrate as mentioned above and to form the electrodes before and after the transfer.
  • an isolation means which may be, for example, a Bragg mirror (as illustrated in FIG. 9 ) or a cavity previously etched into the carrier substrate or into the final substrate, as applicable.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Piezo-Electric Transducers For Audible Bands (AREA)
US17/041,355 2018-03-26 2019-03-21 Method for transferring a piezoelectric layer onto a support substrate Active 2041-10-22 US12167694B2 (en)

Applications Claiming Priority (3)

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FR1852573 2018-03-26
FR1852573A FR3079346B1 (fr) 2018-03-26 2018-03-26 Procede de fabrication d'un substrat donneur pour le transfert d'une couche piezoelectrique, et procede de transfert d'une telle couche piezoelectrique
PCT/FR2019/050645 WO2019186032A1 (fr) 2018-03-26 2019-03-21 Procede de transfert d'une couche piezoelectrique sur un substrat support

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EP (1) EP3776641B1 (de)
JP (1) JP7256204B2 (de)
KR (1) KR102671192B1 (de)
CN (1) CN111919290B (de)
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Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12081188B2 (en) 2018-10-16 2024-09-03 Skyworks Solutions, Inc. Acoustic wave devices
FR3108789B1 (fr) * 2020-03-24 2023-12-08 Soitec Silicon On Insulator Procédé de fabrication d’une structure piézoélectrique pour dispositif radiofréquence et pouvant servir pour le transfert d’une couche piézoélectrique, et procédé de transfert d’une telle couche piézoélectrique
FR3108788B1 (fr) * 2020-03-24 2026-01-23 Soitec Silicon On Insulator Procédé de fabrication d’une structure piézoélectrique pour dispositif radiofréquence et pouvant servir pour le transfert d’une couche piézoélectrique, et procédé de transfert d’une telle couche piézoélectrique
FR3120985B1 (fr) * 2021-03-19 2023-03-31 Soitec Silicon On Insulator Procédé de fabrication d’une hétérostructure
CN113394338A (zh) * 2021-04-28 2021-09-14 上海新硅聚合半导体有限公司 一种异质单晶薄膜的制备方法及异质单晶薄膜
FR3131436B1 (fr) * 2021-12-23 2025-04-25 Soitec Silicon On Insulator Procede de fabrication d’un substrat donneur
FR3131979B1 (fr) 2022-01-17 2025-03-21 Soitec Silicon On Insulator Procédé de fabrication d’un substrat donneur pour le transfert d’une couche piézoélectrique et procédé de transfert d’une couche piézoélectrique sur un substrat support
FR3131980B1 (fr) 2022-01-17 2024-01-12 Soitec Silicon On Insulator Procédé de fabrication d’un substrat donneur pour le transfert d’une couche piézoélectrique et procédé de transfert d’une couche piézoélectrique sur un substrat support
US20260040907A1 (en) 2022-07-19 2026-02-05 Soitec Method for manufacturing a support substrate for a radiofrequency application
FR3138239B1 (fr) 2022-07-19 2024-06-21 Soitec Silicon On Insulator Procédé de fabrication d’un substrat support pour application radiofréquences
WO2024051945A1 (en) * 2022-09-08 2024-03-14 Huawei Technologies Co., Ltd. Surface acoustic wave device, and radio frequency filter and multiplexer comprising the same
FR3140474B1 (fr) 2022-09-30 2024-11-01 Soitec Silicon On Insulator Substrat donneur et Procédé de fabrication d’un substrat donneur pour être utilisé dans un procédé de transfert de couche mince piézoélectrique.
FR3159877B1 (fr) * 2024-03-04 2026-02-20 Soitec Silicon On Insulator Procédé de fabrication d'un substrat, et substrat
FR3160295B1 (fr) 2024-03-14 2026-03-06 Soitec Silicon On Insulator Hétérostructure comprenant une portion exposée rugueuse d’un substrat de support
FR3160509B1 (fr) 2024-03-22 2026-03-20 Soitec Silicon On Insulator Procédé de fabrication d’une couche ferroélectrique reportée sur un substrat et de polarisation à homogénéité améliorée
FR3160477B1 (fr) 2024-03-22 2026-03-20 Soitec Silicon On Insulator Procédé de fabrication d’une couche ferroélectrique reportée sur un substrat et de polarisation à homogénéité améliorée
FR3162098A1 (fr) 2024-05-11 2025-11-14 Soitec Procédé de fabrication ou détermination d’un substrat multicouche pour un dispositif à ondes élastiques
FR3162103A1 (fr) 2024-05-11 2025-11-14 Soitec Structure multicouche pour un dispositif à onde élastique
FR3162101A1 (fr) 2024-05-11 2025-11-14 Soitec Structure multicouche pour un dispositif à ondes élastiques
FR3162100A1 (fr) 2024-05-11 2025-11-14 Soitec Structure multicouche pour un dispositif à ondes élastiques
FR3162102A1 (fr) 2024-05-11 2025-11-14 Soitec Structure multicouche pour un dispositif à onde élastique
FR3162099A1 (fr) 2024-05-11 2025-11-14 Soitec Structure multicouche pour un dispositif à onde élastique
FR3162019A1 (fr) 2024-05-13 2025-11-14 Soitec Structure multicouche pour un dispositif à ondes élastiques
FR3164874A1 (fr) * 2024-07-19 2026-01-23 Soitec Procédé de préparation d’un substrat comprenant une couche mince en matériau piézoélectrique reportée sur un support

Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0924769A1 (de) * 1997-07-03 1999-06-23 Seiko Epson Corporation Verfahren um dünnschichtbauelemente zu transferieren, dünnschichtbauelemet, dünnschicht integriertes schaltkreisbauelement, aktivmatrixsubstrat, flüssigkristallanzeige und elektronisches gerät
US20030082889A1 (en) * 2001-10-30 2003-05-01 Junya Maruyama Semiconductor device and method of manufacturing the same
US20030186521A1 (en) * 2002-03-29 2003-10-02 Kub Francis J. Method of transferring thin film functional material to a semiconductor substrate or optimized substrate using a hydrogen ion splitting technique
US20030199105A1 (en) * 2002-04-22 2003-10-23 Kub Francis J. Method for making piezoelectric resonator and surface acoustic wave device using hydrogen implant layer splitting
US20050048738A1 (en) 2003-08-28 2005-03-03 Shaheen Mohamad A. Arrangements incorporating laser-induced cleaving
JP2005229455A (ja) 2004-02-16 2005-08-25 Shin Etsu Chem Co Ltd 複合圧電基板
CN1864326A (zh) 2003-10-06 2006-11-15 皇家飞利浦电子股份有限公司 谐振器结构及其制造方法
US20070200458A1 (en) 2006-02-24 2007-08-30 Ngk Insulators, Ltd. Piezoelectric thin film device
CN100483666C (zh) * 2003-01-07 2009-04-29 S.O.I.Tec绝缘体上硅技术公司 施主晶片以及重复利用晶片的方法和剥离有用层的方法
US20100190000A1 (en) 2008-01-21 2010-07-29 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating a composite structure with a stable bonding layer of oxide
CN102097298A (zh) 2009-12-11 2011-06-15 S.O.I.Tec绝缘体上硅技术公司 薄soi器件的制造方法
WO2012004250A1 (fr) * 2010-07-06 2012-01-12 Commissariat à l'énergie atomique et aux énergies alternatives Procede d'implantation d'un materiau piezoelectrique
US8142593B2 (en) * 2005-08-16 2012-03-27 Commissariat A L'energie Atomique Method of transferring a thin film onto a support
US8252663B2 (en) * 2009-06-18 2012-08-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method of transferring a thin layer onto a target substrate having a coefficient of thermal expansion different from that of the thin layer
JP5547682B2 (ja) 2004-11-12 2014-07-16 サムスン エレクトロニクス カンパニー リミテッド ブロードキャスト暗号化のためのユーザキー管理方法
CN104175738A (zh) 2013-05-28 2014-12-03 三星显示有限公司 供体衬底及制造方法和使用供体衬底形成转印图案的方法
US20160043269A1 (en) 2013-03-25 2016-02-11 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for manufacturing multi-junction structure for photovoltaic cell
WO2017052646A1 (en) * 2015-09-25 2017-03-30 Intel Corporation Island transfer for optical, piezo and rf applications
FR3045933A1 (fr) * 2015-12-22 2017-06-23 Soitec Silicon On Insulator Substrat pour un dispositif a ondes acoustiques de surface ou a ondes acoustiques de volume compense en temperature
US10325926B2 (en) * 2010-03-02 2019-06-18 Micron Technology, Inc. Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures
US11159140B2 (en) * 2016-06-30 2021-10-26 Soitec Hybrid structure for a surface acoustic wave device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2788176B1 (fr) * 1998-12-30 2001-05-25 Thomson Csf Dispositif a ondes acoustiques guidees dans une fine couche de materiau piezo-electrique collee par une colle moleculaire sur un substrat porteur et procede de fabrication
US8507361B2 (en) * 2000-11-27 2013-08-13 Soitec Fabrication of substrates with a useful layer of monocrystalline semiconductor material
JP2002217666A (ja) * 2001-01-24 2002-08-02 Hitachi Ltd 弾性表面波素子およびその製造方法
JP4069640B2 (ja) * 2002-02-12 2008-04-02 セイコーエプソン株式会社 電気光学装置、及び電子機器
JP4686342B2 (ja) * 2005-11-30 2011-05-25 株式会社日立メディアエレクトロニクス 弾性表面波装置及びこれを搭載した通信端末。
JP2009166309A (ja) * 2008-01-15 2009-07-30 Konica Minolta Holdings Inc インクジェットヘッド及びインクジェットヘッドの製造方法
JP5429200B2 (ja) * 2010-05-17 2014-02-26 株式会社村田製作所 複合圧電基板の製造方法および圧電デバイス
WO2012043615A1 (ja) * 2010-09-28 2012-04-05 株式会社村田製作所 圧電デバイスの製造方法
JP5814774B2 (ja) * 2010-12-22 2015-11-17 日本碍子株式会社 複合基板及び複合基板の製造方法
JP5783256B2 (ja) * 2011-08-26 2015-09-24 株式会社村田製作所 圧電デバイス、および、圧電デバイスの製造方法
FR2983342B1 (fr) * 2011-11-30 2016-05-20 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure limitant la formation de defauts et heterostructure ainsi obtenue
FR3032555B1 (fr) * 2015-02-10 2018-01-19 Soitec Procede de report d'une couche utile
FR3042647B1 (fr) * 2015-10-20 2017-12-01 Soitec Silicon On Insulator Structure composite et procede de fabrication associe
FR3045678B1 (fr) * 2015-12-22 2017-12-22 Soitec Silicon On Insulator Procede de fabrication d'une couche piezoelectrique monocristalline et dispositif microelectronique, photonique ou optique comprenant une telle couche
TWI660580B (zh) * 2016-03-25 2019-05-21 日商日本碍子股份有限公司 接合方法

Patent Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0924769A1 (de) * 1997-07-03 1999-06-23 Seiko Epson Corporation Verfahren um dünnschichtbauelemente zu transferieren, dünnschichtbauelemet, dünnschicht integriertes schaltkreisbauelement, aktivmatrixsubstrat, flüssigkristallanzeige und elektronisches gerät
US20030082889A1 (en) * 2001-10-30 2003-05-01 Junya Maruyama Semiconductor device and method of manufacturing the same
US20030186521A1 (en) * 2002-03-29 2003-10-02 Kub Francis J. Method of transferring thin film functional material to a semiconductor substrate or optimized substrate using a hydrogen ion splitting technique
US20030199105A1 (en) * 2002-04-22 2003-10-23 Kub Francis J. Method for making piezoelectric resonator and surface acoustic wave device using hydrogen implant layer splitting
CN100483666C (zh) * 2003-01-07 2009-04-29 S.O.I.Tec绝缘体上硅技术公司 施主晶片以及重复利用晶片的方法和剥离有用层的方法
US20050048738A1 (en) 2003-08-28 2005-03-03 Shaheen Mohamad A. Arrangements incorporating laser-induced cleaving
CN1864326A (zh) 2003-10-06 2006-11-15 皇家飞利浦电子股份有限公司 谐振器结构及其制造方法
JP2005229455A (ja) 2004-02-16 2005-08-25 Shin Etsu Chem Co Ltd 複合圧電基板
JP5547682B2 (ja) 2004-11-12 2014-07-16 サムスン エレクトロニクス カンパニー リミテッド ブロードキャスト暗号化のためのユーザキー管理方法
US8142593B2 (en) * 2005-08-16 2012-03-27 Commissariat A L'energie Atomique Method of transferring a thin film onto a support
US20070200458A1 (en) 2006-02-24 2007-08-30 Ngk Insulators, Ltd. Piezoelectric thin film device
US20100190000A1 (en) 2008-01-21 2010-07-29 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating a composite structure with a stable bonding layer of oxide
US8252663B2 (en) * 2009-06-18 2012-08-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method of transferring a thin layer onto a target substrate having a coefficient of thermal expansion different from that of the thin layer
CN102097298A (zh) 2009-12-11 2011-06-15 S.O.I.Tec绝缘体上硅技术公司 薄soi器件的制造方法
US10325926B2 (en) * 2010-03-02 2019-06-18 Micron Technology, Inc. Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures
WO2012004250A1 (fr) * 2010-07-06 2012-01-12 Commissariat à l'énergie atomique et aux énergies alternatives Procede d'implantation d'un materiau piezoelectrique
KR20140008286A (ko) 2010-07-06 2014-01-21 꼼미사리아 아 레네르지 아토미끄 에뜨 옥스 에너지스 앨터네이티브즈 압전물질 주입에 대한 방법
US20160043269A1 (en) 2013-03-25 2016-02-11 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for manufacturing multi-junction structure for photovoltaic cell
CN104175738A (zh) 2013-05-28 2014-12-03 三星显示有限公司 供体衬底及制造方法和使用供体衬底形成转印图案的方法
WO2017052646A1 (en) * 2015-09-25 2017-03-30 Intel Corporation Island transfer for optical, piezo and rf applications
FR3045933A1 (fr) * 2015-12-22 2017-06-23 Soitec Silicon On Insulator Substrat pour un dispositif a ondes acoustiques de surface ou a ondes acoustiques de volume compense en temperature
US11159140B2 (en) * 2016-06-30 2021-10-26 Soitec Hybrid structure for a surface acoustic wave device

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
Chinese Second Office Action for Application No. 201980021982.3 dated Oct. 13, 2023, 3 pages.
Chinese Second Search Report for Application No. 201980021982.3 dated Oct. 13, 2023, 2 pages.
International Search Report for International Application No. PCT/FR2019/050645 dated May 22, 2019, 2 pages.
International Written Opinion for International Application No. PCT/FR2019/050645 dated May 22, 2019, 8 pages.
Korean Office Action for Application No. 10-2020-7029598 dated Dec. 12, 2023, 10 pages with machine translation.

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