US11901185B2 - Etching method - Google Patents

Etching method Download PDF

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US11901185B2
US11901185B2 US17/473,418 US202117473418A US11901185B2 US 11901185 B2 US11901185 B2 US 11901185B2 US 202117473418 A US202117473418 A US 202117473418A US 11901185 B2 US11901185 B2 US 11901185B2
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layer
region
substrate
forming
main surface
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US20220301877A1 (en
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Mitsuo Sano
Susumu Obata
Kazuhito Higuchi
Takayuki Tajima
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1603—Process or apparatus coating on selected surface areas
    • C23C18/1605—Process or apparatus coating on selected surface areas by masking
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/42—Coating with noble metals
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Definitions

  • Embodiments described herein relate generally to an etching method.
  • MacEtch Metal-assisted chemical etching is a method of etching a semiconductor surface using a noble metal as a catalyst. According to MacEtch, for example, a recess with a high aspect ratio can be formed on a semiconductor substrate.
  • FIG. 1 is a top view showing an example of a capacitor that can be manufactured by a method according to first and second embodiments;
  • FIG. 2 is a cross-sectional view taken along a line II-II of the capacitor shown in FIG. 1 ;
  • FIG. 3 is a cross-sectional view showing a step of a capacitor manufacturing method according to the first embodiment
  • FIG. 4 is a cross-sectional view showing another step of the capacitor manufacturing method according to the first embodiment
  • FIG. 5 is a top view showing a structure obtained by the step of FIG. 4 ;
  • FIG. 6 is a cross-sectional view showing still another step of the capacitor manufacturing method according to the first embodiment
  • FIG. 7 is a cross-sectional view showing still another step of the capacitor manufacturing method according to the first embodiment
  • FIG. 8 is a top view showing a structure obtained by the step of FIG. 7 ;
  • FIG. 9 is a cross-sectional view showing still another step of the capacitor manufacturing method according to the first embodiment.
  • FIG. 10 is a cross-sectional view showing still another step of the capacitor manufacturing method according to the first embodiment
  • FIG. 11 is a cross-sectional view showing a structure obtained by the steps of FIGS. 9 and 10 ;
  • FIG. 12 is an electron micrograph showing an example of a structure obtained when a second layer is omitted
  • FIG. 13 is an electron micrograph showing an example of a structure obtained when a second layer is provided.
  • FIG. 14 is a cross-sectional view showing a step of a capacitor manufacturing method according to a second embodiment
  • FIG. 15 is a top view showing a structure obtained by the step of FIG. 14 ;
  • FIG. 16 is a cross-sectional view showing another step of the capacitor manufacturing method according to the second embodiment.
  • FIG. 17 is a cross-sectional view showing still another step of the capacitor manufacturing method according to the second embodiment.
  • FIG. 18 is a cross-sectional view showing a modified example of the capacitor manufacturing method according to the second embodiment.
  • An etching method comprises forming a first layer on a substrate, the substrate containing a semiconductor material and having a main surface, the main surface including a first region and a second region adjacent to each other, the first layer covering the first region and the second region, a portion of the first layer covering the first region being provided with a plurality of openings or one or more openings defining a plurality of island-shaped portions, and a portion of the first layer covering the second region being a continuous layer; forming a catalyst layer containing a noble metal on a portion(s) of the main surfaces exposed in the plurality of openings or the one or more openings by a plating method; forming a second layer to cover a portion of the catalyst layer adjacent to a boundary between the first region and the second region and expose a portion of the catalyst layer spaced apart from the boundary; and etching the substrate with an etching agent containing an oxidizer and hydrogen fluoride in a presence of the catalyst layer and the second layer.
  • a method for manufacturing a structural body according to the first embodiment comprises forming one or more recesses on the substrate by the above etching method.
  • a method for manufacturing a semiconductor device comprises forming one or more recesses on the substrate by the above etching method; forming a lower electrode on side walls of the one or more recesses; forming a dielectric layer on the lower electrode; and forming an upper electrode on the dielectric layer.
  • a method for manufacturing a structural body, specifically a capacitor, which is an example of a semiconductor device, utilizing the above etching method is described below.
  • FIGS. 1 and 2 show an example of a capacitor that can be manufactured by the method according to the first embodiment.
  • a capacitor 1 shown in FIGS. 1 and 2 includes a conductive substrate CS, a conductive layer 20 b , and a dielectric layer 30 , as shown in FIG. 2 .
  • an X direction is a direction parallel to a main surface of the conductive substrate CS
  • a Y direction is a direction parallel to the main surface of the conductive substrate CS and perpendicular to the X direction
  • a Z direction is a thickness direction of the conductive substrate CS, i.e., a direction perpendicular to the X direction and the Y direction.
  • the conductive substrate CS includes a semiconductor material such as silicon.
  • the conductive substrate CS is a substrate having electrical conductivity at least in its surface facing the conductive layer 20 b . At least a portion of the conductive substrate CS serves as a lower electrode of the capacitor.
  • the conductive substrate CS has a first main surface S 1 , a second main surface S 2 , and an end face extending from an edge of the first main surface S 1 to an edge of the second main surface S 2 .
  • the conductive substrate CS has a flat and approximately right-angled parallelepiped shape.
  • the conductive substrate CS may have other shapes.
  • the first main surface S 1 i.e., a top surface of the conductive substrate CS in this embodiment, includes a first region A 1 and a second region A 2 .
  • the first region A 1 corresponds to a portion of the conductive substrate CS on which recesses TR described later are provided.
  • the second region A 2 is equal to the first region A 1 in height.
  • the second region A 2 is adjacent to the first region A 1 .
  • the first region A 1 has a rectangular shape
  • the second region A 2 surrounds the first region A 1 .
  • a portion that corresponds to the first region A 1 of the conductive substrate CS is provided with a plurality of recesses TR, each having a shape extending in one direction and arranged in the width direction.
  • the recesses TR are open in the first region A 1 .
  • the recesses TR are spaced apart from one another.
  • the recesses TR are trenches extending in the Y direction and arranged in the X direction.
  • Portions of the conductive substrate CS each sandwiched between one and the other of adjacent recesses TR are projections.
  • the projections each have a shape extending in the Y direction and are arranged in the X direction. That is, the portion of the conductive substrate CS that corresponds to the first region A 1 is provided with a plurality of wall parts each having a shape extending in the Y direction and the Z direction and arranged in the X direction as the projections.
  • the “length direction” of the recesses or the projections is a length direction of orthogonal projections of the recesses or the projections onto a plane perpendicular to the thickness direction of the conductive substrate.
  • a length of an opening of each recess TR is within a range of 10 ⁇ m to 500 ⁇ m according to an example, and within a range of 50 ⁇ m to 100 ⁇ m according to another example.
  • a width of the opening of the recess TR i.e., a distance between the projections adjacent in the width direction, is preferably 0.3 ⁇ m or more. If this width or distance is reduced, a larger electric capacitance can be achieved. However, if this width or distance is reduced, it becomes difficult to form a stacked structure including the dielectric layer 30 and the conductive layer 20 b in the recesses TR.
  • a depth of the recesses TR or a height of the projections is within a range of 10 ⁇ m to 300 ⁇ m according to an example, and within a range of 50 ⁇ m to 100 ⁇ m according to another example.
  • a distance between the recesses TR adjacent in the width direction i.e., a thickness of the projection, is preferably 0.1 ⁇ m or more. If this distance or thickness is reduced, a larger electric capacitance can be achieved. However, if this distance or thickness is reduced, the projections are likely to be damaged.
  • cross sections of the recesses TR perpendicular to the length directions are rectangular.
  • these cross sections need not be rectangular and may have, for example, a tapered shape.
  • the conductive substrate CS includes a substrate 10 and a conductive layer 20 a.
  • the substrate 10 has the same shape as that of the conductive substrate CS.
  • the substrate 10 is a substrate containing a semiconductor material, for example, a semiconductor substrate.
  • the substrate 10 is preferably a substrate containing silicon such as a silicon substrate. Such a substrate can be processed using semiconductor processes.
  • the conductive layer 20 a is provided on the substrate 10 .
  • the conductive layer 20 a serves as a lower electrode of the capacitor.
  • the conductive layer 20 a is made of, for example, polysilicon doped with impurities to improve the electrical conductivity, or a metal such as molybdenum, aluminum, gold, tungsten, platinum, nickel, or copper, or an alloy thereof.
  • the conductive layer 20 a may have a single-layer structure or a multi-layer structure.
  • a thickness of the conductive layer 20 a is preferably within a range of 0.05 ⁇ m to 1 ⁇ m, and more preferably within a range of 0.1 ⁇ m to 0.3 ⁇ m. If the conductive layer 20 a is thin, the possibility exists that a discontinuous portion may be generated in the conductive layer 20 a , or a sheet resistance of the conductive layer 20 a may be excessively increased. When the conductive layer 20 a is thickened, manufacturing costs increase.
  • the substrate 10 is a semiconductor substrate such as a silicon substrate
  • the conductive layer 20 a is a high-concentration doped layer that is a surface region of the semiconductor substrate doped with impurities at a high concentration.
  • the projections, if thin enough, can be entirely doped with impurities at a high concentration.
  • the conductive layer 20 a may be omitted, and the substrate 10 may be used as the conductive substrate CS.
  • the substrate 10 is a semiconductor substrate made of a semiconductor doped with P-type or N-type impurities, or a metal substrate
  • the conductive layer 20 a can be omitted.
  • at least a surface region of the substrate 10 e.g., the entire substrate 10 , serves as the conductive layer 20 a.
  • the conductive layer 20 b serves as an upper electrode of the capacitor.
  • the conductive layer 20 b is provided on the first region A 1 , and covers sidewalls and bottom surfaces of the recesses TR.
  • the conductive layer 20 b is made of, for example, polysilicon doped with impurities to improve the electrical conductivity, or a metal such as molybdenum, aluminum, gold, tungsten, platinum, nickel, or copper, or an alloy thereof.
  • the conductive layer 20 b may have a single-layer structure or a multi-layer structure.
  • a thickness of the conductive layer 20 b is preferably within a range of 0.05 ⁇ m to 1 ⁇ m, and more preferably within a range of 0.1 ⁇ m to 0.3 ⁇ m. If the conductive layer 20 b is thin, the possibility exists that a discontinuous portion may be generated in the conductive layer 20 b , or a sheet resistance of the conductive layer 20 b may be excessively increased. If the conductive layer 20 b is thick, it may be difficult to form the conductive layer 20 a and the dielectric layer 30 with sufficient thicknesses.
  • the conductive layer 20 b is provided so that the recesses TR are completely filled with the conductive layer 20 b and the dielectric layer 30 .
  • the conductive layer 20 b may be a layer that is conformal to a surface of the conductive substrate CS. That is, the conductive layer 20 b may be a layer having an approximately uniform thickness. In this case, the recesses TR are not completely filled with the conductive layer 20 b and the dielectric layer 30 .
  • the dielectric layer 30 is interposed between the conductive substrate CS and the conductive layer 20 b .
  • the dielectric layer 30 is a layer that is conformal to the surface of the conductive substrate CS.
  • the dielectric layer 30 electrically insulates the conductive substrate CS and the conductive layer 20 b from each other.
  • the dielectric layer 30 is made of, for example, an organic dielectric or an inorganic dielectric.
  • the organic dielectric for example, polyimide can be used.
  • the inorganic dielectric a ferroelectric can be used. Paraelectrics such as silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, and tantalum oxide, are preferable. These paraelectrics have a small change in dielectric constant with temperature. Therefore, when the paraelectrics are used for the dielectric layer 30 , the heat resistance of the capacitor 1 can be improved.
  • a thickness of the dielectric layer 30 is preferably within a range of 0.005 ⁇ m to 0.5 ⁇ m, and more preferably within a range of 0.01 ⁇ m to 0.1 ⁇ m.
  • the dielectric layer 30 is thin, the possibility exists that a discontinuous portion may be generated in the dielectric layer 30 , and the conductive substrate CS and the conductive layer 20 b may be short-circuited. Further, if the dielectric layer 30 is thinned, a withstand voltage is lowered even if there is no short circuit, and a possibility of short-circuiting when a voltage is applied is increased. When the dielectric layer 30 is thickened, the withstand voltage increases, but the electric capacitance decreases.
  • a portion of the dielectric layer 30 located above the second region A 2 is opened such that the opening surrounds the first region A 1 . That is, the dielectric layer 30 allows the conductive layer 20 a to be exposed at this position.
  • the portion of the dielectric layer 30 that is provided on the first main surface S 1 is opened in a frame shape.
  • This capacitor 1 further includes an insulating layer 60 , a first internal electrode 70 a , a second internal electrode 70 b , a first external electrode 70 c , and a second external electrode 70 d.
  • the first internal electrode 70 a is provided on the first region A 1 .
  • the first internal electrode 70 a is electrically connected to the conductive layer 20 b .
  • the first internal electrode 70 a is a rectangular electrode located at a center of the first main surface S 1 .
  • the second internal electrode 70 b is provided on the second region A 2 .
  • the second internal electrode 70 b is in contact with the conductive substrate CS at a position of the opening provided in the dielectric layer 30 . Thereby, the second internal electrode 70 b is electrically connected to the conductive substrate CS.
  • the second internal electrode 70 b is a frame-shaped electrode arranged to surround the first internal electrode 70 a.
  • the first internal electrode 70 a and the second internal electrode 70 b may have a single-layer structure or a multi-layer structure.
  • Each layer constituting the first internal electrode 70 a and the second internal electrode 70 b is made of, for example, a metal such as molybdenum, aluminum, gold, tungsten, platinum, copper, nickel, or an alloy containing one or more of them.
  • the insulating layer 60 covers portions of the conductive layer 20 b and the dielectric layer 30 that are located on the first main surface S 1 , and further covers the first internal electrode 70 a and the second internal electrode 70 b .
  • the insulating layer 60 is partially opened at a position of a part of the first internal electrode 70 a and a position of a part of the second internal electrode 70 b.
  • the insulating layer 60 may have a single-layer structure or a multi-layer structure.
  • Each layer constituting the insulating layer 60 is made of, for example, an inorganic insulator such as silicon nitride and silicon oxide, or an organic insulator such as polyimide and novolac resin.
  • the first external electrode 70 c is provided on the insulating layer 60 .
  • the first external electrode 70 c is in contact with the first internal electrode 70 a at a position of one or more openings provided in the insulating layer 60 . Thereby, the first external electrode 70 c is electrically connected to the first internal electrode 70 a .
  • a region 70 R 1 is a region where the first external electrode 70 c and the first internal electrode 70 a are in contact with each other.
  • the second external electrode 70 d is provided on the insulating layer 60 .
  • the second external electrode 70 d is in contact with the second internal electrode 70 b at a position of the remaining opening(s) provided in the insulating layer 60 .
  • the second external electrode 70 d is electrically connected to the second internal electrode 70 b .
  • a region 70 R 2 is a region where the second external electrode 70 d and the second internal electrode 70 b are in contact with each other.
  • the first external electrode 70 c has a stacked structure including a first metal layer 70 c 1 and a second metal layer 70 c 2 .
  • the second external electrode 70 d has a stacked structure including a first metal layer 70 d 1 and a second metal layer 70 d 2 .
  • the first metal layers 70 c 1 and 70 d 1 are made of, for example, copper.
  • the second metal layers 70 c 2 and 70 d 2 cover upper and end surfaces of the first metal layers 70 c 1 and 70 dl , respectively.
  • the second metal layers 70 c 2 and 70 d 2 are constituted by, for example, a stacked film of a nickel or nickel alloy layer and a gold layer.
  • the second metal layers 70 c 2 and 70 d 2 can be omitted.
  • the first external electrode 70 c or the first internal electrode 70 a may further include a barrier layer at a position adjacent to an interface therebetween.
  • the second external electrode 70 d or the second internal electrode 70 b may further include a barrier layer at a position adjacent to an interface therebetween, too.
  • As a material of the barrier layer for example, titanium can be used.
  • This capacitor 1 is, for example, manufactured by the following method. Hereinafter, an example of a method of manufacturing the capacitor 1 will be described with reference to FIGS. 3 to 11 .
  • the substrate 10 shown in FIG. 3 is first prepared.
  • the conductive layer 20 a is formed by doping the surface region of the substrate 10 with impurities at a high concentration as will be described later. Accordingly, one main surface and the other main surface of the substrate 10 respectively correspond to the first main surface S 1 and the second main surface S 2 which have been explained with reference to FIG. 2 .
  • the first main surface S 1 includes the first region A 1 and the second region A 2 which have been explained with reference to FIG. 2 .
  • the substrate 10 is a single-crystal silicon wafer.
  • a plane orientation of the single-crystal silicon wafer is not particularly limited, but in this embodiment, a silicon wafer whose first main surface S 1 is a (100) plane is used.
  • a silicon wafer whose first main surface S 1 is a (110) plane can also be used.
  • a first layer 90 is formed on the first main surface S 1 of the substrate 10 .
  • the openings are a plurality of slits 90 S arranged in the width direction.
  • the slits 90 S have a length direction parallel to the Y direction, and are arranged in the X direction.
  • a portion of the first layer 90 that covers the second region A 2 is a continuous layer.
  • the first layer 90 is a first mask layer that prevents the portions of the first main surface S 1 that are covered with the first layer 90 from coming into contact with a noble metal, which will be described later.
  • the openings in the first layer 90 may have a form other than the slit.
  • the first layer 90 may include a plurality of through holes each opened in a circular, elliptical, or polygonal shape and arranged in two directions intersecting each other.
  • the first layer 90 may be provided with one or more openings that define a plurality of island-shaped portions, instead of a plurality of openings.
  • pillar-shaped projections can be generated at the positions corresponding to the island-shaped portions by etching, which will be described later.
  • Examples of the material of the first layer 90 include organic materials such as polyimide, fluororesin, phenol resin, acrylic resin, and novolac resin, and inorganic materials such as silicon oxide and silicon nitride.
  • the first layer 90 can be formed by, for example, existing semiconductor processes.
  • the first layer 90 made of an organic material can be formed by, for example, photolithography.
  • the first layer 90 made of an inorganic material can be formed by, for example, deposition of an inorganic material layer by vapor deposition, formation of a mask by photolithography, and patterning of the inorganic material layer by etching.
  • the first layer 90 made of an inorganic material can be formed by oxidation or nitriding of the surface region of the substrate 10 , formation of a mask by photolithography, and patterning of an oxide or nitride layer by etching.
  • a catalyst layer 80 containing a noble metal is formed on portions of the first main surface S 1 exposed in the slits 90 S by a plating method.
  • the catalyst layer 80 is, for example, a discontinuous layer containing a noble metal.
  • the catalyst layer 80 is a particulate layer formed of catalyst particles 81 containing a noble metal.
  • the noble metal is, for example, one or more of gold, silver, platinum, rhodium, palladium, and ruthenium.
  • the catalyst layer 80 and the catalyst particles 81 may further contain a metal other than a noble metal such as titanium.
  • the plating method used to form the catalyst layer 80 is, for example, electroplating, reduction plating, or displacement plating. Of these methods, displacement plating is particularly favorable because it is possible to directly and almost evenly deposit the noble metal on the regions of the first main surface S 1 that are not covered with the first layer 90 .
  • a region in the vicinity of a boundary between the first region A 1 and the second region A 2 differs from a region sufficiently spaced apart from the boundary in a balance between supply of a metal from a plating solution and consumption of the metal due to its deposition.
  • the metal deposits in the slit 90 S more easily as compared to the region sufficiently spaced apart from the boundary. Therefore, the catalyst layer 80 comes to include a first catalyst portion 80 a in which the metal deposits at a proper density and a second catalyst portion 80 b in which the metal deposits at a high density.
  • the second catalyst portion 80 b is prone to generate a process defect.
  • a second layer 95 is formed as shown in FIGS. 6 to 8 .
  • the second layer 95 includes a portion 95 A extending in the length direction of the slits 90 S and a portion 95 B extending in a direction in which the slits 90 S are arranged.
  • the second layer 95 is a second mask layer that prevents an etching agent 100 , which will be described later, from reaching the second catalyst portion 80 b .
  • the second layer 95 is formed so as to cover a portion of the catalyst layer 80 that is adjacent to the boundary between the first region A 1 and the second region A 2 , and to expose a portion of the catalyst layer 80 that is spaced apart from the boundary. Accordingly, the second layer 95 covers the second catalyst portion 80 b , without covering at least a part of the first catalyst portion 80 a.
  • the second layer 95 is formed so that widths of portions located on the first region A 1 , namely, widths D 1 and D 2 in FIG. 8 , are preferably within a range of 20 ⁇ m to 100 ⁇ m, more preferably within a range of 20 ⁇ m to 50 ⁇ m. If the widths are increased, the whole second catalyst portion 80 b can be reliably covered with the second layer 95 . However, if the widths are increased, the area of the portion of the first catalyst portion 80 a that is covered with the second layer 95 becomes larger.
  • the widths D 1 and D 2 may be equal to each other. Alternatively, the widths D 1 and D 2 may be different. For example, the width D 1 may be greater than the width D 2 .
  • the second layer 95 is formed so that the thickness is preferably within a range of 0.1 ⁇ m to 10 ⁇ m, more preferably within a range of 0.5 ⁇ m to 1 ⁇ m. If the second layer 95 is thick, the whole second catalyst portion 80 b can be reliably covered with the second layer 95 . However, if the second layer 95 is thick, the costs will be increased.
  • Examples of the material of the second layer 95 include organic materials such as polyimide, fluororesin, phenol resin, acrylic resin, and novolac resin, and inorganic materials such as silicon oxide and silicon nitride.
  • the second layer 95 can be formed by, for example, existing semiconductor processes.
  • the second layer 95 made of an organic material can be formed by, for example, photolithography.
  • the second layer 95 made of an inorganic material can be formed by, for example, deposition of an inorganic material layer by vapor deposition, formation of a mask by photolithography, and patterning of the inorganic material layer by etching.
  • the material of the second layer 95 is preferably an organic material.
  • the material of the second layer 95 may adhere to a portion of the first catalyst portion 80 a that should not be covered with the second layer 95 . Such an adhered material reduces the catalyst activity. Therefore, after the second layer 95 is formed, it is preferable to remove the adhered material from the exposed portion of the first catalyst portion 80 a by, for example, etching. For example, if an organic material is used as the material of the second layer 95 , it is preferable to perform ashing. If this treatment is performed on the structure shown in FIG. 6 , the second layer 95 is thinned as shown in FIG. 7 .
  • the substrate 10 is etched with an assist from a noble metal as a catalyst to form the recesses on the first main surface S 1 .
  • the substrate 10 is etched with an etching agent 100 .
  • the substrate 10 is immersed in the etching agent 100 in liquid form to bring the etching agent 100 into contact with the substrate 10 .
  • the etching agent 100 contains an oxidizer and hydrogen fluoride.
  • the concentration of hydrogen fluoride in the etching agent 100 is preferably within a range of 1 mol/L to 20 mol/L, more preferably within a range of 5 mol/L to 10 mol/L, and further preferably within a range of 3 mol/L to 7 mol/L.
  • the hydrogen fluoride concentration is low, it is difficult to achieve a high etching rate.
  • the hydrogen fluoride concentration is high, excess side etching may occur.
  • the oxidizer can be selected from, for example, hydrogen peroxide, nitric acid, AgNO 3 , KAuCl 4 , HAuCl 4 , K 2 PtCl 6 , H 2 PtCl 6 , Fe(NO 3 ) 3 , Ni(NO 3 ) 2 , Mg(NO 3 ) 2 , Na 2 S 2 O 8 , K 2 S 2 O 8 , KMnO 4 , and K 2 Cr 2 O 7 .
  • Hydrogen peroxide is favorable as the oxidizer because no harmful byproducts are produced, and a semiconductor element is not contaminated.
  • the concentration of the oxidizer in the etching agent 100 is preferably within a range of 0.2 mol/L to 8 mol/L, more preferably within a range of 2 mol/L to 4 mol/L, and further preferably within a range of 3 mol/L to 4 mol/L.
  • the etching agent 100 may further contain a buffer.
  • the buffer contains, for example, at least one of ammonium fluoride and ammonia.
  • the buffer is ammonium fluoride.
  • the buffer is a mixture of ammonium fluoride and ammonia.
  • the etching agent 100 may further contain other components such as water.
  • the material of the substrate 10 i.e. silicon in this embodiment, is oxidized in regions of the substrate 10 that are close to the catalyst particles 81 and that the etching agent 100 can reach. Then, oxide generated thereby is dissolved and removed by hydrofluoric acid. In contrast, in regions of the substrate 10 where the catalyst particles 81 are not present in the vicinity, the aforementioned reaction does not occur. Furthermore, in regions of the substrate 10 where the catalyst particles 81 are present in the vicinity, if the etching agent 100 cannot reach the regions due to the second layer 95 , the aforementioned reaction does not occur. Therefore, only the portions that are close to the catalyst particles 81 and that the etching agent 100 can reach are selectively etched.
  • the catalyst particles 81 move toward the second main surface S 2 as the etching progresses, and etching similar to the above is performed there. As a result, as shown in FIG. 10 , at the positions of portions of the first catalyst layer 80 a that are not covered with the second layer 95 , etching progresses from the first main surface S 1 toward the second main surface S 2 in a direction perpendicular to the first main surface S 1 .
  • the recesses TR shown in FIG. 11 are formed on the first main surface S 1 .
  • the first layer 90 may be removed from the substrate 10 after the catalyst layer 80 is formed and before the second layer 95 is formed.
  • the conductive layer 20 a shown in FIG. 2 is formed on the substrate 10 to obtain the conductive substrate CS.
  • the conductive layer 20 a is the lower electrode of the capacitor.
  • the conductive layer 20 a can be formed by, for example, doping the surface region of the substrate 10 with impurities at a high concentration.
  • the conductive layer 20 a made of polysilicon can be formed by, for example, LPCVD (low pressure chemical vapor deposition).
  • the conductive layer 20 a made of metal can be formed by, for example, electrolytic plating, reduction plating, or displacement plating.
  • a plating solution is a liquid containing a salt of a metal to be plated.
  • a general plating solution such as a copper sulfate plating solution containing copper sulfate pentahydrate and sulfuric acid, a copper pyrophosphate plating solution containing copper pyrophosphate and potassium pyrophosphate, and a nickel sulfamate plating solution containing nickel sulfamate and boron, can be used.
  • the conductive layer 20 a is preferably formed by a plating method using a plating solution containing a salt of a metal to be plated, a surfactant, and carbon dioxide in a supercritical or subcritical state.
  • the surfactant is interposed between particles made of supercritical carbon dioxide and a continuous phase of a solution containing a salt of a metal to be plated. That is, the surfactant is allowed to form micelles in the plating solution, and supercritical carbon dioxide is incorporated in these micelles.
  • the supply of the metal to be plated may be insufficient in the vicinity of the bottom portions of the recesses. This is particularly noticeable when a ratio D/W of the depth D to a width or diameter W of the recesses is large.
  • the micelles incorporating supercritical carbon dioxide can easily enter narrow gaps. As the micelles move, the solution containing the salt of the metal to be plated also moves. Therefore, according to a plating method using a plating solution containing a salt of a metal to be plated, a surfactant, and carbon dioxide in a supercritical or subcritical state, the conductive layer 20 a having a uniform thickness can be easily formed.
  • the conductive layer 20 a is formed by doping the surface region of the substrate 10 with impurities at a high concentration.
  • the surface region of the substrate 10 on the first main surface S 1 side is used as the conductive layer 20 a.
  • the dielectric layer 30 is formed on the conductive layer 20 a .
  • the dielectric layer 30 can be formed by, for example, CVD (chemical vapor deposition).
  • the dielectric layer 30 can be formed by oxidizing, nitriding, or oxynitriding the surface of the conductive layer 20 a.
  • the conductive layer 20 b is formed on the dielectric layer 30 .
  • the conductive layer 20 b is an upper electrode of the capacitor.
  • a conductive layer made of polysilicon or metal is formed.
  • Such a conductive layer 20 b can be formed by, for example, the same method as described above for the conductive layer 20 a.
  • an opening is formed in the dielectric layer 30 .
  • a portion of the dielectric layer 30 that is located on the first main surface S 1 is opened in a frame shape.
  • This opening can be formed by, for example, formation of a mask by photolithography and patterning by etching.
  • the first internal electrode 70 a and the second internal electrode 70 b can be formed by, for example, a combination of film formation by sputtering or plating, and photolithography.
  • the insulating layer 60 is formed.
  • the insulating layer 60 is opened at the positions corresponding to a part of the first internal electrode 70 a and a part of the second internal electrode 70 b .
  • the insulating layer 60 can be formed by, for example, a combination of film formation by CVD and photolithography.
  • the first external electrode 70 c and the second external electrode 70 d are formed on the insulating layer 60 . Specifically, first, the first metal layers 70 c 1 and 70 d 1 are formed. Next, the second metal layers 70 c 2 and 70 d 2 are formed. The first metal layers 70 c 1 and 70 d 1 and the second metal layers 70 c 2 and 70 d 2 can be formed by, for example, a combination of film formation by sputtering or plating, and photolithography.
  • this capacitor 1 the recesses TR are provided on the first main surface S 1 , and the stacked structure including the dielectric layer 30 and the conductive layer 20 b is provided not only on the first main surface S 1 but also in the recesses TR. Therefore, this capacitor 1 can achieve a large electric capacitance.
  • the catalyst layer 80 includes a first catalyst portion 80 a in which the noble metal deposits at a proper density and a second catalyst portion 80 b in which the noble metal deposits at a high density.
  • a region in the vicinity of the boundary between the first region A 1 and the second region A 2 differs from a region sufficiently spaced apart from the boundary in a balance between supply of a metal from a plating solution and consumption of the metal due to its deposition. More specifically, this is because no slit 90 S is provided in the first layer 90 at a position corresponding to the second region A 2 and therefore, the area of a region to which the plating solution in the vicinity of the boundary between the first region A 1 and the second region A 2 should supply the metal is smaller than the area of a region to which the plating solution sufficiently spaced apart from the boundary should supply the metal.
  • the etching described above with reference to FIGS. 9 and 10 is performed without forming the second layer 95 , the etching progresses in a direction perpendicular to the first main surface S 1 in a region in which the first catalyst portion 80 a is formed.
  • process defects occur in a region in which the second catalyst portion 80 b is formed; for example, the etching progresses in a direction inclined with respect to the first main surface S 1 , the direction of progress of etching varies, or the etching in the direction perpendicular to the first main surface S 1 is not effectively performed.
  • a structure shown in FIG. 12 is obtained.
  • the etching agent 100 is prevented from being supplied to the second catalyst portion 80 b . Therefore, the etching does not progress at the position corresponding to the second layer 95 and the aforementioned process defects do not occur. Accordingly, for example, a structure shown in FIG. 13 is obtained.
  • An etching method comprises forming a mask layer on a substrate, the substrate containing a semiconductor material and having a main surface, the main surface including a first region and a second region adjacent to each other, the mask layer including a first portion and a second portion, the first portion covering the first region and being provided with a plurality of openings or one or more openings defining a plurality of island-shaped portions, the second portion being a continuous layer covering the second region, and a height of the second portion at a position adjacent to a boundary between the first region and the second region with reference to the main surfaces being higher than a height of the first portion with reference to the main surfaces; forming a catalyst layer containing a noble metal on a portion(s) of the main surfaces exposed in the plurality of openings or the one or more openings by a plating method; and etching the substrate with an etching agent containing an oxidizer and hydrogen fluoride in a presence of the catalyst layer and the mask layer.
  • a method for manufacturing a structural body according to the second embodiment comprises forming one or more recesses on the substrate by the above etching method.
  • a method for manufacturing a semiconductor device comprises forming one or more recesses on the substrate by the above etching method; forming a lower electrode on side walls of the one or more recesses; forming a dielectric layer on the lower electrode; and forming an upper electrode on the dielectric layer.
  • a method for manufacturing a structural body, specifically a capacitor, which is an example of a semiconductor device, utilizing the above etching method is described below.
  • the capacitor 1 described in the first embodiment can be manufactured.
  • the capacitor 1 is manufactured by the following method.
  • a mask layer 98 is formed on a first main surface S 1 of a substrate 10 .
  • the substrate 10 is the same as that of the first embodiment described above.
  • the mask layer 98 includes a first portion 98 a and a second portion 98 b.
  • the first portion 98 a is a portion of the mask layer 98 that covers a first region A 1 .
  • the first portion 98 a is provided with a plurality of openings.
  • the openings are a plurality of slits 90 S arranged in the width direction.
  • the slits 90 S have a length direction parallel to the Y direction, and are arranged in the X direction.
  • the openings in the first portion 98 a may have a form other than the slit.
  • the first portion 98 a may include a plurality of though holes each opened in a circular, elliptical, or polygonal shape and arranged in two directions intersecting each other.
  • the first portion 98 a may be provided with one or more openings that define a plurality of island-shaped portions, instead of a plurality of openings.
  • pillar-shaped projections can be generated at the positions corresponding to the island-shaped portions by etching, which will be described later.
  • the second portion 98 b is a portion of the mask layer 98 that covers the second region A 2 .
  • the second portion 98 b is a continuous film.
  • Height H 2 A or H 2 B of the second portion 98 b at a position adjacent to the boundary between the first region A 1 and the second region A 2 with reference to the first main surface S 1 is greater than a height H 1 of the first portion 98 a with reference to the first main surface S 1 .
  • the mask layer 98 is a stacked body of the first layer 90 and the second layer 96 shown in FIGS. 14 and 15 .
  • the first portion 98 a is a portion that covers the first region A 1 of the first layer 90 .
  • the second portion 98 b is a combination of the second layer 96 and a portion of the first layer 90 that covers the second region A 2 .
  • the first layer 90 is formed on the first main surface S 1 .
  • the first layer 90 is the same as that of the first embodiment described above. In other words, the first layer 90 serves the same function as that of the first embodiment described above.
  • the first layer 90 covers the first region A 1 and the second region A 2 .
  • the openings are a plurality of slits 90 S arranged in the width direction.
  • the slits 90 S have a length direction parallel to the Y direction, and are arranged in the X direction.
  • the openings in the first layer 90 may have a form other than the slit.
  • the first layer 90 may include a plurality of through holes each opened in a circular, elliptical, or polygonal shape and arranged in two directions intersecting each other.
  • the first layer 90 may be provided with one or more openings that define a plurality of island-shaped portions, instead of a plurality of openings.
  • the portion of the first layer 90 that covers the second region A 2 is a continuous film.
  • the portion of the first layer 90 that covers the second region A 2 is equal in height to the portion of the first layer 90 that covers the first region A 1 .
  • the first layer 90 As a material of the first layer 90 , for example, those described in the first embodiment can be used.
  • the first layer 90 can be formed by, for example, the same method as in the first embodiment described above.
  • the second layer 96 is formed on the first layer 90 .
  • the second layer 96 exposes the portion of the first layer 90 that covers the first region A 1 .
  • the second layer 96 covers the second region A 2 of the first layer 90 at least at the position adjacent to the boundary between the first region A 1 and the second region A 2 .
  • the second layer 96 has a frame shape surrounding the first region A 1 .
  • the second layer 96 As a material of the second layer 96 , for example, those described above for the second layer 95 in the first embodiment can be used.
  • the second layer 96 can be formed by, for example, the same method as described above for the second layer 95 in the first embodiment.
  • the second layer 96 prevents the metal from being excessively supplied from the plating solution to the first main surface S 1 in the region in the vicinity of the boundary between the first region A 1 and the second region A 2 . Accordingly, the density of the catalyst metal can be substantially equal in both the slit 90 S in the vicinity of the boundary between the first region A 1 and the second region A 2 and the slit 90 S sufficiently spaced apart from the boundary.
  • the mask layer 98 may be formed integrally. For example, first, a photosensitive resin layer is formed on the first layer 90 .
  • the photosensitive resin for example, a positive-type photoresist is used.
  • exposure using, for example, a grating mask is performed, or exposure is performed twice or more, on the photosensitive resin layer.
  • first and second exposure portions which are different in the exposure amount, and a non-exposure portion are formed in the photosensitive resin layer.
  • development or the like is performed, so that an integrally formed mask layer 98 is obtained.
  • the ratio of the height H 2 A or H 2 B of the second portion 98 b at a position adjacent to the boundary with reference to the first main surface S 1 to the height H 1 of the first portion 98 a with reference to the first main surface S 1 is preferably within a range of 2 to 5, and more preferably, within a range of 2 to 3.
  • the height H 1 is the thickness of the first layer 90 .
  • the height H 2 A is a height of the second portion 98 b with reference to the first main surface S 1 at a position adjacent to a portion of the boundary that extends along the length direction of the slit 90 S.
  • the height H 2 A is a height of the portion 96 A of the second layer 96 that extends in the length direction of the slit 90 S with reference to the first main surface S 1 .
  • the height H 2 B is a height of the second portion 98 b with reference to the first main surface S 1 at the position adjacent to a portion of the boundary that extends along the direction of arrangement of the slits 90 S.
  • the height H 2 B is a height of the portion 96 B of the second layer 96 that extends in the direction of arrangement of the slits 90 S with reference to the first main surface S 1 .
  • the ratio of a height HA or HB of the second portion 98 b with reference to the first portion 98 a to a distance DA or DB in a direction parallel to the first main surface S 1 from a highest portion of the second portion 98 b with reference to the first main surface S 1 to the plurality of openings or one or more openings is preferably within a range of 1 to 4, and more preferably within a range of 2 to 4.
  • the distance DA is a distance in the direction of arrangement of the slits 90 S from the portion 96 A of the second layer 96 that extends in the length direction of the slits 90 S to the slits 90 S.
  • the distance DB is a distance in the length direction of the slits 90 S from the portion 96 B of the second layer 96 that extends in the direction of arrangement of the slits 90 S to the slits 90 S.
  • the height HA is a height of the second portion 98 b with reference to the first portion 98 a at the position adjacent to a portion of the boundary that extends along the length direction the slits 90 S.
  • the height HA is a thickness of a portion of the second layer 96 that extends in the length direction of the slits 90 S.
  • the height HB is a height of the second portion 98 b with reference to the first portion 98 a at the position adjacent to a portion of the boundary that extends along the direction of arrangement of the slits 90 S.
  • the height HB is a thickness of a portion of the second layer 96 that extends in the direction of arrangement of the slits 90 S.
  • the amount of supply of the metal from the plating solution to the first main surface S 1 is reduced in a region in the vicinity of the boundary between the first region A 1 and the second region A 2 in the plating treatment for forming the catalyst layer 80 .
  • the height H 1 is preferably within a range of 0.1 ⁇ m to 10 ⁇ m, and more preferably within a range of 0.5 ⁇ m to 1 ⁇ m.
  • the heights H 2 A and H 2 B are preferably within a range of 0.2 ⁇ m to 20 ⁇ m, and more preferably within a range of 1 ⁇ m to 3 ⁇ m.
  • the heights H 2 A and H 2 B may be equal to each other or different from each other.
  • the heights HA and HB are preferably within a range of 0.1 ⁇ m to 10 ⁇ m, and more preferably within a range of 0.5 ⁇ m to 2 ⁇ m.
  • the heights HA and HB may be equal to each other or different from each other.
  • the distances DA and DB are preferably within a range of 0.05 ⁇ m to 0.5 ⁇ m, and more preferably within a range of 0.1 ⁇ m to 0.2 ⁇ m.
  • the distances DA and DB may be equal to each other or different from each other.
  • the catalyst layer 80 is formed on portions of the first main surface S 1 that are exposed in the slits 90 S, as shown in FIG. 16 .
  • a material of the catalyst layer 80 for example, those described above in the first embodiment can be used.
  • the catalyst layer 80 can be formed by, for example, the same method as in the first embodiment described above.
  • the substrate 10 is etched with the etching agent 100 containing an oxidizer and hydrogen fluoride in a presence of the catalyst layer 80 and the mask layer 98 . Accordingly, the recesses TR are formed on the first main surface S 1 .
  • etching agent 100 for example, those described above in the first embodiment can be used.
  • the etching is performed by, for example, the same method as in the first embodiment described above.
  • the mask layer 98 and the catalyst layer 80 are removed from the substrate 10 .
  • the conductive layer 20 a , the dielectric layer 30 , and the conductive layer 20 b are formed as in the first embodiment described above.
  • the first internal electrode 70 a , the second internal electrode 70 b , the insulating layer 60 , the first external electrode 70 c , and the second external electrode 70 d are formed, and dicing is performed. In the manner described above, the capacitor 1 shown in FIGS. 1 and 2 is obtained.
  • this capacitor 1 the recesses TR are provided on the first main surface S 1 , and the stacked structure including the dielectric layer 30 and the conductive layer 20 b is provided not only on the first main surface S 1 but also in the recesses TR. Therefore, this capacitor 1 can achieve a large electric capacitance.
  • the second layer 96 prevents the metal from being excessively supplied from the plating solution to the first main surface S 1 in the region in the vicinity of the boundary between the first region A 1 and the second region A 2 . Accordingly, the density of the catalyst metal can be substantially equal in both the slit 90 S in the vicinity of the boundary between the first region A 1 and the second region A 2 and the slit 90 S sufficiently spaced apart from the boundary. Therefore, similarly to the first embodiment, a process defect in etching with a catalyst is less prone to occur.
  • the height of the portion of the first region A 1 that corresponds to the slits 90 S may be made higher than the height of the remainder portion of the first region A 1 , prior to forming the catalyst layer 80 .
  • the height of a portion of the first region A 1 that is covered with the first layer 90 may be reduced by etching.
  • the height of a portion of the first region A 1 that corresponds to the slits 90 S may be increased by epitaxial growth. In this way, the direction of progress of etching is not easily varied.
  • the second layer 96 is formed along the whole of the boundary between the first region A 1 and the second region A 2 .
  • the portion 96 B of the second layer 96 that extends in the direction of arrangement of the slits 90 S may be formed only in the vicinity of the portion 96 A of the second layer 96 that extends in the length direction of the slits 90 S, as shown in FIG. 18 .
  • the recesses TR are trenches, projections interposed between the adjacent recesses TR are shaped like a partition wall. In this case, in etching for forming the recesses TR, if a process defect occurs in the whole length of a certain recess TR, the projection adjacent to the recess TR may break. On the other hand, in etching for forming the recesses TR, if a process defect occurs only at the end portions of a certain recess TR, the projection adjacent to the recess TR is less prone to break.
  • the projection between the adjacent recesses TR is less prone to break in the etching for forming the recesses TR.

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Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0882703A (ja) 1994-09-09 1996-03-26 Nikon Corp 高アスペクト比、微細パターンの素子の製造方法
JPH09321042A (ja) 1996-05-30 1997-12-12 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6265075B1 (en) * 1999-07-20 2001-07-24 International Business Machines Corporation Circuitized semiconductor structure and method for producing such
US20080032242A1 (en) 2004-06-30 2008-02-07 Yasuo Masuda Method of Forming Plated Product Using Negative Photoresist Composition and Photosensitive Composition Used Therein
US20080090074A1 (en) 2004-11-09 2008-04-17 Osaka University Method Of Forming Pores In Crystal Substrate, And Crystal Substrate Containing Pores Formed By the same
US20110266521A1 (en) 2010-03-09 2011-11-03 Board Of Regents Of The University Of Texas System Porous and non-porous nanostructures
US20150130028A1 (en) 2013-11-13 2015-05-14 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor chip, semiconductor chip, and semiconductor device
US20170062230A1 (en) * 2015-09-01 2017-03-02 Kabushiki Kaisha Toshiba Etching method, article manufacturing method, and etching apparatus
JP2017195383A (ja) 2017-05-25 2017-10-26 株式会社東芝 エッチング方法、物品の製造方法、及びエッチング装置
JP2017201660A (ja) 2016-05-04 2017-11-09 株式会社ザイキューブ 半導体基板への孔の形成方法及びそれに用いるマスク構造
US20180033634A1 (en) * 2016-07-28 2018-02-01 Kabushiki Kaisha Toshiba Etching method, method of manufacturing semiconductor chip, and method of manufacturing article
US20190252199A1 (en) * 2018-02-09 2019-08-15 Kabushiki Kaisha Toshiba Etching method, method of manufacturing semiconductor chip, and method of manufacturing article
WO2019171470A1 (ja) 2018-03-06 2019-09-12 株式会社 東芝 コンデンサ及びその製造方法
JP2019535133A (ja) 2016-09-21 2019-12-05 モレキュラー インプリンツ， インコーポレイテッドＭｏｌｅｃｕｌａｒ Ｉｍｐｒｉｎｔｓ，Ｉｎｃ． 構造のマイクロリソグラフィ加工
US20200235200A1 (en) 2019-01-21 2020-07-23 Kabushiki Kaisha Toshiba Capacitor
US20210296432A1 (en) * 2020-03-23 2021-09-23 Kabushiki Kaisha Toshiba Structure and method of producing the same
US20220115238A1 (en) * 2020-10-09 2022-04-14 Kabushiki Kaisha Toshiba Etching method, method of manufacturing semiconductor chip, and method of manufacturing article

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10134599B2 (en) 2016-02-24 2018-11-20 The Board Of Trustees Of The University Of Illinois Self-anchored catalyst metal-assisted chemical etching
JP6970263B2 (ja) 2018-02-09 2021-11-24 株式会社東芝 エッチング方法、半導体チップの製造方法及び物品の製造方法

Patent Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0882703A (ja) 1994-09-09 1996-03-26 Nikon Corp 高アスペクト比、微細パターンの素子の製造方法
JPH09321042A (ja) 1996-05-30 1997-12-12 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6265075B1 (en) * 1999-07-20 2001-07-24 International Business Machines Corporation Circuitized semiconductor structure and method for producing such
US20080032242A1 (en) 2004-06-30 2008-02-07 Yasuo Masuda Method of Forming Plated Product Using Negative Photoresist Composition and Photosensitive Composition Used Therein
JP4376706B2 (ja) 2004-06-30 2009-12-02 東京応化工業株式会社 ネガ型ホトレジスト組成物を用いたメッキ形成物の形成方法
US20080090074A1 (en) 2004-11-09 2008-04-17 Osaka University Method Of Forming Pores In Crystal Substrate, And Crystal Substrate Containing Pores Formed By the same
JP2011101009A (ja) 2004-11-09 2011-05-19 Sharp Corp 単結晶基板
US20110266521A1 (en) 2010-03-09 2011-11-03 Board Of Regents Of The University Of Texas System Porous and non-porous nanostructures
JP2013527103A (ja) 2010-03-09 2013-06-27 ボード・オブ・リージェンツ・オブ・ザ・ユニバーシティ・オブ・テキサス・システム 多孔質および非孔質のナノ構造体
US20150130028A1 (en) 2013-11-13 2015-05-14 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor chip, semiconductor chip, and semiconductor device
US20170062230A1 (en) * 2015-09-01 2017-03-02 Kabushiki Kaisha Toshiba Etching method, article manufacturing method, and etching apparatus
JP2017201660A (ja) 2016-05-04 2017-11-09 株式会社ザイキューブ 半導体基板への孔の形成方法及びそれに用いるマスク構造
US20180033634A1 (en) * 2016-07-28 2018-02-01 Kabushiki Kaisha Toshiba Etching method, method of manufacturing semiconductor chip, and method of manufacturing article
US10838298B2 (en) 2016-09-21 2020-11-17 Molecular Imprints, Inc. Microlithographic fabrication of structures
JP2019535133A (ja) 2016-09-21 2019-12-05 モレキュラー インプリンツ， インコーポレイテッドＭｏｌｅｃｕｌａｒ Ｉｍｐｒｉｎｔｓ，Ｉｎｃ． 構造のマイクロリソグラフィ加工
JP2017195383A (ja) 2017-05-25 2017-10-26 株式会社東芝 エッチング方法、物品の製造方法、及びエッチング装置
US20190252199A1 (en) * 2018-02-09 2019-08-15 Kabushiki Kaisha Toshiba Etching method, method of manufacturing semiconductor chip, and method of manufacturing article
JP2019140225A (ja) 2018-02-09 2019-08-22 株式会社東芝 エッチング方法、半導体チップの製造方法及び物品の製造方法
US10854466B2 (en) 2018-02-09 2020-12-01 Kabushiki Kaisha Toshiba Etching method, method of manufacturing semiconductor chip, and method of manufacturing article
JPWO2019171750A1 (ja) 2018-03-06 2020-04-16 株式会社東芝 コンデンサ及びその製造方法
US20200219656A1 (en) 2018-03-06 2020-07-09 Kabushiki Kaisha Toshiba Capacitor and manufacturing method thereof
WO2019171470A1 (ja) 2018-03-06 2019-09-12 株式会社 東芝 コンデンサ及びその製造方法
US20200235200A1 (en) 2019-01-21 2020-07-23 Kabushiki Kaisha Toshiba Capacitor
JP2020119936A (ja) 2019-01-21 2020-08-06 株式会社東芝 コンデンサ
US20210296432A1 (en) * 2020-03-23 2021-09-23 Kabushiki Kaisha Toshiba Structure and method of producing the same
US20220115238A1 (en) * 2020-10-09 2022-04-14 Kabushiki Kaisha Toshiba Etching method, method of manufacturing semiconductor chip, and method of manufacturing article

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